From nobody Sat Sep 21 05:55:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28253C6379F for ; Wed, 22 Feb 2023 09:26:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231757AbjBVJ0W (ORCPT ); Wed, 22 Feb 2023 04:26:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231429AbjBVJ0H (ORCPT ); Wed, 22 Feb 2023 04:26:07 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E150367EC; Wed, 22 Feb 2023 01:26:04 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E9E6366021BA; Wed, 22 Feb 2023 09:26:01 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1677057963; bh=op8NGiC4mCc8OttiZfVKxYJjou9svW4e8fQKxfR3sSo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Az23soXZzRNS6np6JpXQt3EUrls9IhACRN3Ul349+paoMGp+0xDt7H5ZmesQl3joK 0OlKUvTGUuR+uGm/28C3iipWLlHjs8Gd0GBfyiPwoqaUqD+lHJXPhLd6zpThnz+gNo dQr3WuLWU9uMnT15u/5PyNtLyNeevDamiE6aL8quQaSshbzq1leV/RIrOoagkPJIE4 ioCNql+kVu8IAQEVnBcmo68k2PvFTSONVU+kd2dknHzJoAY/y1uzPuMTozN1JklAKK 4Rtccza3PAPDWc4p7oBzBZNGPWapDhcY6PFmcdfgfq7dgmZLkfZTAMkx/3mWht9z1N U/Cm6FLIOArmQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 05/54] clk: mediatek: mt2712: Migrate topckgen/mcucfg to mtk_clk_simple_probe() Date: Wed, 22 Feb 2023 10:24:54 +0100 Message-Id: <20230222092543.19187-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230222092543.19187-1-angelogioacchino.delregno@collabora.com> References: <20230222092543.19187-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that the common mtk_clk_simple_{probe,remove}() functions can deal with divider clocks it is possible to migrate more clock drivers to it: in this case, it's about topckgen. While at it, also perform a fast migration for mcucfg. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2712.c | 127 +++++------------------------- 1 file changed, 21 insertions(+), 106 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 94f8fc2a4f7b..db20c46e088b 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -36,14 +36,11 @@ static const struct mtk_fixed_clk top_fixed_clks[] =3D { FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), }; =20 -static const struct mtk_fixed_factor top_early_divs[] =3D { +static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 1), FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 2), -}; - -static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 1), FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, @@ -1295,114 +1292,30 @@ static int clk_mt2712_apmixed_probe(struct platfor= m_device *pdev) return r; } =20 -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt2712_top_init_early(struct device_node *node) -{ - int r, i; - - if (!top_clk_data) { - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - for (i =3D 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - } - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} - -CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen", - clk_mt2712_top_init_early); - -static int clk_mt2712_top_probe(struct platform_device *pdev) -{ - int r, i; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); - return PTR_ERR(base); - } - - if (!top_clk_data) { - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - } else { - for (i =3D 0; i < CLK_TOP_NR_CLK; i++) { - if (top_clk_data->hws[i] =3D=3D ERR_PTR(-EPROBE_DEFER)) - top_clk_data->hws[i] =3D ERR_PTR(-ENOENT); - } - } - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), top_clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - return r; -} - -static int clk_mt2712_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); - return PTR_ERR(base); - } - - clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); - - r =3D mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt2712_clk_lock, clk_data); - if (r) - dev_err(&pdev->dev, "Could not register composites: %d\n", r); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt2712_clk_lock, +}; =20 - return r; -} +static const struct mtk_clk_desc mcu_desc =3D { + .composite_clks =3D mcu_muxes, + .num_composite_clks =3D ARRAY_SIZE(mcu_muxes), + .clk_lock =3D &mt2712_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt2712[] =3D { { .compatible =3D "mediatek,mt2712-apmixedsys", .data =3D clk_mt2712_apmixed_probe, - }, { - .compatible =3D "mediatek,mt2712-topckgen", - .data =3D clk_mt2712_top_probe, - }, { - .compatible =3D "mediatek,mt2712-mcucfg", - .data =3D clk_mt2712_mcu_probe, }, { /* sentinel */ } @@ -1440,7 +1353,9 @@ static const struct mtk_clk_desc peri_desc =3D { =20 static const struct of_device_id of_match_clk_mt2712_simple[] =3D { { .compatible =3D "mediatek,mt2712-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt2712-mcucfg", .data =3D &mcu_desc }, { .compatible =3D "mediatek,mt2712-pericfg", .data =3D &peri_desc, }, + { .compatible =3D "mediatek,mt2712-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 --=20 2.39.2