From nobody Sun Nov 10 22:10:20 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E3CBC6379F for ; Wed, 22 Feb 2023 09:26:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231626AbjBVJ0t (ORCPT ); Wed, 22 Feb 2023 04:26:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231737AbjBVJ0T (ORCPT ); Wed, 22 Feb 2023 04:26:19 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E712F28D1B; Wed, 22 Feb 2023 01:26:11 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A757166021A4; Wed, 22 Feb 2023 09:26:09 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1677057970; bh=61bmCGgO46/vig9rcN72PXOmhMCDa6XWRrTizTTJ3+I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B1soAwS6+GoOQb7eiV0OW/4q8cEz28wKVdhBp8KzyZ4NDgedwbmVO/ra8wMDQcWcL z46ZEcDauwJq8S0MpCk8zxJXiiNaIrc9O0BIAUfc9TiZ4kKWQqc2OsobQrUSAhn1hS KAI/tyGQbI+mgbi5m5mjTKO0e7zSsA3n4t4toDAo5ezAqPo/rEnhvEQ5Oj1vJYjTKk ibwL3uNURxiNLfvEQ5JQGWWKqBJ/+Mt+FZER9PL2tL3FXBPfq1YD61OOwvuiHI78kS sRY5E6pwB9LTj6AvYHwHrJP7+7KDMHBpbZBZL/8C5cLNU6YC5JBoN/LPw9eU0433tz Uqm5Wd+YWyuTg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 11/54] clk: mediatek: mt8365: Move apmixedsys clock driver to its own file Date: Wed, 22 Feb 2023 10:25:00 +0100 Message-Id: <20230222092543.19187-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230222092543.19187-1-angelogioacchino.delregno@collabora.com> References: <20230222092543.19187-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating all other mt8365 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 164 +++++++++++++++++++ drivers/clk/mediatek/clk-mt8365.c | 143 ---------------- 3 files changed, 165 insertions(+), 144 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8365-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 3c7dd19cdddf..b004a47026d4 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -112,7 +112,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195) +=3D clk-mt8195-apmixed= sys.o clk-mt8195-topckgen.o clk-mt8195-venc.o clk-mt8195-vpp0.o clk-mt8195-vpp1.o \ clk-mt8195-wpe.o clk-mt8195-imp_iic_wrap.o \ clk-mt8195-apusys_pll.o -obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365.o +obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365.o clk-mt8365-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) +=3D clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) +=3D clk-mt8365-cam.o obj-$(CONFIG_COMMON_CLK_MT8365_MFG) +=3D clk-mt8365-mfg.o diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8365-apmixedsys.c new file mode 100644 index 000000000000..6f0fdf92bbd2 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2023 Collabora Ltd. + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-mtk.h" + +#define MT8365_PLL_FMAX (3800UL * MHZ) +#define MT8365_PLL_FMIN (1500UL * MHZ) +#define CON0_MT8365_RST_BAR BIT(23) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ + _rst_bar_mask, _pcw_chg_reg) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D _rst_bar_mask, \ + .fmax =3D MT8365_PLL_FMAX, \ + .fmin =3D MT8365_PLL_FMIN, \ + .pcwbits =3D _pcwbits, \ + .pcwibits =3D 8, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .tuner_en_reg =3D _tuner_en_reg, \ + .tuner_en_bit =3D _tuner_en_bit, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .pcw_chg_reg =3D _pcw_chg_reg, \ + .div_table =3D _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, \ + _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ + _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ + _pcw_chg_reg) \ + +static const struct mtk_pll_div_table armpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, + { .div =3D 1, .freq =3D 1500 * MHZ }, + { .div =3D 2, .freq =3D 750 * MHZ }, + { .div =3D 3, .freq =3D 375 * MHZ }, + { .div =3D 4, .freq =3D 182500000 }, + { } /* sentinel */ +}; + +static const struct mtk_pll_div_table mfgpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, + { .div =3D 1, .freq =3D 1600 * MHZ }, + { .div =3D 2, .freq =3D 800 * MHZ }, + { .div =3D 3, .freq =3D 400 * MHZ }, + { .div =3D 4, .freq =3D 200 * MHZ }, + { } /* sentinel */ +}; + +static const struct mtk_pll_div_table dsppll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, + { .div =3D 1, .freq =3D 1600 * MHZ }, + { .div =3D 2, .freq =3D 600 * MHZ }, + { .div =3D 3, .freq =3D 400 * MHZ }, + { .div =3D 4, .freq =3D 200 * MHZ }, + { } /* sentinel */ +}; + +static const struct mtk_pll_data plls[] =3D { + PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, + 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, + HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, CON0_MT8365_RST_BAR= , 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, + HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, CON0_MT8365_RST_BAR= , 0), + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, + 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, + 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, + 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, + 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, + 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, + 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), + PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, + 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), + PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, + 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), +}; + +static int clk_mt8365_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct clk_hw *hw; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + hw =3D devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, + base + 0x204, 0, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[CLK_APMIXED_UNIV_EN] =3D hw; + + hw =3D devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, + base + 0x204, 1, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[CLK_APMIXED_USB20_EN] =3D hw; + + ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_plls; + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8365_apmixed[] =3D { + { .compatible =3D "mediatek,mt8365-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8365_apmixed_drv =3D { + .probe =3D clk_mt8365_apmixed_probe, + .driver =3D { + .name =3D "clk-mt8365-apmixed", + .of_match_table =3D of_match_clk_mt8365_apmixed, + }, +}; +builtin_platform_driver(clk_mt8365_apmixed_drv) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index c9faa07ec0a6..91449a7cf608 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -17,7 +17,6 @@ #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-pll.h" =20 static DEFINE_SPINLOCK(mt8365_clk_lock); =20 @@ -757,145 +756,6 @@ static const struct mtk_simple_gate peri_clks[] =3D { { CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 }, }; =20 -#define MT8365_PLL_FMAX (3800UL * MHZ) -#define MT8365_PLL_FMIN (1500UL * MHZ) -#define CON0_MT8365_RST_BAR BIT(23) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ - _rst_bar_mask, _pcw_chg_reg) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D _rst_bar_mask, \ - .fmax =3D MT8365_PLL_FMAX, \ - .fmin =3D MT8365_PLL_FMIN, \ - .pcwbits =3D _pcwbits, \ - .pcwibits =3D 8, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .tuner_en_reg =3D _tuner_en_reg, \ - .tuner_en_bit =3D _tuner_en_bit, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .pcw_chg_reg =3D _pcw_chg_reg, \ - .div_table =3D _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, \ - _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ - _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ - _pcw_chg_reg) \ - -static const struct mtk_pll_div_table armpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, - { .div =3D 1, .freq =3D 1500 * MHZ }, - { .div =3D 2, .freq =3D 750 * MHZ }, - { .div =3D 3, .freq =3D 375 * MHZ }, - { .div =3D 4, .freq =3D 182500000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table mfgpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, - { .div =3D 1, .freq =3D 1600 * MHZ }, - { .div =3D 2, .freq =3D 800 * MHZ }, - { .div =3D 3, .freq =3D 400 * MHZ }, - { .div =3D 4, .freq =3D 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table dsppll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, - { .div =3D 1, .freq =3D 1600 * MHZ }, - { .div =3D 2, .freq =3D 600 * MHZ }, - { .div =3D 3, .freq =3D 400 * MHZ }, - { .div =3D 4, .freq =3D 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] =3D { - PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, - 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, - HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, - CON0_MT8365_RST_BAR, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, - HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, - CON0_MT8365_RST_BAR, 0), - PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, - 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, - 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, - 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, - 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, - 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, - 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), - PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, - 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), - PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, - 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), -}; - -static int clk_mt8365_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - struct clk_hw *hw; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - hw =3D devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, - base + 0x204, 0, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - clk_data->hws[CLK_APMIXED_UNIV_EN] =3D hw; - - hw =3D devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, - base + 0x204, 1, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - clk_data->hws[CLK_APMIXED_USB20_EN] =3D hw; - - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_plls; - - return 0; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - - return ret; -} - static int clk_mt8365_register_mtk_simple_gates(struct device *dev, void __iomem *bas= e, struct clk_hw_onecell_data *clk_data, @@ -1104,9 +964,6 @@ static int clk_mt8365_mcu_probe(struct platform_device= *pdev) =20 static const struct of_device_id of_match_clk_mt8365[] =3D { { - .compatible =3D "mediatek,mt8365-apmixedsys", - .data =3D clk_mt8365_apmixed_probe, - }, { .compatible =3D "mediatek,mt8365-topckgen", .data =3D clk_mt8365_top_probe, }, { --=20 2.39.2