From nobody Thu Nov 14 06:54:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36471C61DA3 for ; Tue, 21 Feb 2023 15:38:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233971AbjBUPiX (ORCPT ); Tue, 21 Feb 2023 10:38:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234606AbjBUPiD (ORCPT ); Tue, 21 Feb 2023 10:38:03 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07A2E2BF3A; Tue, 21 Feb 2023 07:37:54 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E3C9666021D3; Tue, 21 Feb 2023 15:37:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676993873; bh=d98v4XkYuSdlaBMRVhy8ckf3WPpqfT9gFqNu9PlgtLo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UzrE+LbQ/q/0oEUfdmGWDjpM6NnJzjiNqoBtqiibNwJyOF6/8O7KN8y54F0CMgd9y stIgTD8qLHyWnvwds8ShWi8WDhOJdDF8LXMThS8yUsuTwO9XvQfQVafex2aLd3OczH WAmHckmNQJcvQhmyKFYTlguwycU553zByLkDfXZ+aSJiuhLiR77aKQk6pS/Lu1sesA W1xqD0lj0CWJIjhbpjlBN/1pxG8rP08/Rt78pgudRFgmG8PUOa7rQM6OcJbNnCOXs6 6BQAyJzAdFlIxXawaNBxgj800LlZwNc6FMLN0k2sGuxI5QKkBhGtGYygRhnIXmyG3R sN4UBYv7JHEfQ== From: AngeloGioacchino Del Regno To: airlied@gmail.com Cc: daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, steven.price@arm.com, alyssa.rosenzweig@collabora.com, matthias.bgg@gmail.com, robh@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org, AngeloGioacchino Del Regno Subject: [PATCH v2 10/10] drm/panfrost: Add new compatible for Mali on the MT8183 SoC Date: Tue, 21 Feb 2023 16:37:40 +0100 Message-Id: <20230221153740.1620529-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230221153740.1620529-1-angelogioacchino.delregno@collabora.com> References: <20230221153740.1620529-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The "mediatek,mt8183-mali" compatible uses platform data that calls for getting (and managing) two regulators ("mali" and "sram") but devfreq does not support this usecase, resulting in DVFS not working. Since a lot of MediaTek SoCs need to set the voltages for the GPU SRAM regulator in a specific relation to the GPU VCORE regulator, a MediaTek SoC specific driver was introduced to automatically satisfy, through coupling, these constraints: this means that there is at all no need to manage both regulators in panfrost but to otherwise just manage the main "mali" (-> gpu vcore) regulator instead. Keeping in mind that we cannot break the ABI, the most sensible route (avoiding hacks and uselessly overcomplicated code) to get a MT8183 node with one power supply was to add a new "mediatek,mt8183b-mali" compatible, which effectively deprecates the former. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price Reviewed-by: Chen-Yu Tsai --- drivers/gpu/drm/panfrost/panfrost_drv.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 5d25e77e1037..14cdeaeeb5c4 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -654,6 +654,14 @@ static const struct panfrost_compatible amlogic_data = =3D { .vendor_quirk =3D panfrost_gpu_amlogic_quirk, }; =20 +/* + * The old data with two power supplies for MT8183 is here only to + * keep retro-compatibility with older devicetrees, as DVFS will + * not work with this one. + * + * On new devicetrees please use the _b variant with a single and + * coupled regulators instead. + */ static const char * const mediatek_mt8183_supplies[] =3D { "mali", "sram",= NULL }; static const char * const mediatek_mt8183_pm_domains[] =3D { "core0", "cor= e1", "core2" }; static const struct panfrost_compatible mediatek_mt8183_data =3D { @@ -663,6 +671,14 @@ static const struct panfrost_compatible mediatek_mt818= 3_data =3D { .pm_domain_names =3D mediatek_mt8183_pm_domains, }; =20 +static const char * const mediatek_mt8183_b_supplies[] =3D { "mali", NULL = }; +static const struct panfrost_compatible mediatek_mt8183_b_data =3D { + .num_supplies =3D ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1, + .supply_names =3D mediatek_mt8183_b_supplies, + .num_pm_domains =3D ARRAY_SIZE(mediatek_mt8183_pm_domains), + .pm_domain_names =3D mediatek_mt8183_pm_domains, +}; + static const char * const mediatek_mt8192_supplies[] =3D { "mali", NULL }; static const char * const mediatek_mt8192_pm_domains[] =3D { "core0", "cor= e1", "core2", "core3", "core4" }; @@ -691,6 +707,7 @@ static const struct of_device_id dt_match[] =3D { { .compatible =3D "arm,mali-bifrost", .data =3D &default_data, }, { .compatible =3D "arm,mali-valhall-jm", .data =3D &default_data, }, { .compatible =3D "mediatek,mt8183-mali", .data =3D &mediatek_mt8183_data= }, + { .compatible =3D "mediatek,mt8183b-mali", .data =3D &mediatek_mt8183_b_d= ata }, { .compatible =3D "mediatek,mt8192-mali", .data =3D &mediatek_mt8192_data= }, {} }; --=20 2.39.2