From nobody Thu Sep 11 02:23:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04CF3C6379F for ; Tue, 21 Feb 2023 14:12:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234274AbjBUOMK convert rfc822-to-8bit (ORCPT ); Tue, 21 Feb 2023 09:12:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233858AbjBUOL6 (ORCPT ); Tue, 21 Feb 2023 09:11:58 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3861327D4E; Tue, 21 Feb 2023 06:11:55 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id A975024E1D4; Tue, 21 Feb 2023 22:11:53 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 21 Feb 2023 22:11:53 +0800 Received: from localhost.localdomain (183.27.98.67) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 21 Feb 2023 22:11:52 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , Krzysztof Kozlowski , Philipp Zabel , Emil Renner Berthing CC: Rob Herring , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , , Subject: [PATCH v1 2/3] clk: starfive: Add StarFive JH7110 PLL clock driver Date: Tue, 21 Feb 2023 22:11:46 +0800 Message-ID: <20230221141147.303642-3-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221141147.303642-1-xingyu.wu@starfivetech.com> References: <20230221141147.303642-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.67] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add driver for the StarFive JH7110 PLL clock controller and modify the JH7110 system clock driver to rely on this PLL clocks. Signed-off-by: Xingyu Wu --- drivers/clk/starfive/Kconfig | 9 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jh7110-pll.c | 433 ++++++++++++++++++ .../clk/starfive/clk-starfive-jh7110-pll.h | 286 ++++++++++++ .../clk/starfive/clk-starfive-jh7110-sys.c | 40 +- 5 files changed, 742 insertions(+), 27 deletions(-) create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 2aa664f2cdee..5bac840ba682 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -21,12 +21,21 @@ config CLK_STARFIVE_JH7100_AUDIO Say Y or M here to support the audio clocks on the StarFive JH7100 SoC. =20 +config CLK_STARFIVE_JH7110_PLL + bool "StarFive JH7110 PLL clock support" + depends on SOC_STARFIVE || COMPILE_TEST + default SOC_STARFIVE + help + Say yes here to support the PLL clock controller on the + StarFive JH7110 SoC. + config CLK_STARFIVE_JH7110_SYS bool "StarFive JH7110 system clock support" depends on SOC_STARFIVE || COMPILE_TEST select AUXILIARY_BUS select CLK_STARFIVE_JH71X0 select RESET_STARFIVE_JH7110 + select CLK_STARFIVE_JH7110_PLL default SOC_STARFIVE help Say yes here to support the system clock controller on the diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index f3df7d957b1e..b48e539e52b0 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) +=3D clk-starfive-jh71x0.o obj-$(CONFIG_CLK_STARFIVE_JH7100) +=3D clk-starfive-jh7100.o obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) +=3D clk-starfive-jh7100-audio.o =20 +obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) +=3D clk-starfive-jh7110-pll.o obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) +=3D clk-starfive-jh7110-sys.o obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) +=3D clk-starfive-jh7110-aon.o diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/s= tarfive/clk-starfive-jh7110-pll.c new file mode 100644 index 000000000000..320297859a23 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7110 PLL Clock Generator Driver + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Xingyu Wu + * + * This driver is about to register JH7110 PLL clock generator and support= ops. + * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2. + * Each PLL clocks work in integer mode or fraction mode by some dividers, + * and the configuration registers and dividers are set in several syscon = registers. + * The formula for calculating frequency is: + * Fvco =3D Fref * (NI + NF) / M / Q1 + * Fref: OSC source clock rate + * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[= 11:0]. + * NF: fractional frequency dividing ratio, set by frac[23:0]. NF =3D frac= [23:0] / 2^24 =3D 0 ~ 0.999. + * M: frequency dividing ratio of pre-divider, set by prediv[5:0]. + * Q1: frequency dividing ratio of post divider, set by postdiv1[1:0], Q1= =3D 1,2,4,8. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-starfive-jh7110-pll.h" + +static struct jh7110_clk_pll_data *jh7110_pll_data_from(struct clk_hw *hw) +{ + return container_of(hw, struct jh7110_clk_pll_data, hw); +} + +static struct jh7110_clk_pll_priv *jh7110_pll_priv_from(struct jh7110_clk_= pll_data *data) +{ + return container_of(data, struct jh7110_clk_pll_priv, data[data->idx]); +} + +static unsigned long pll_get_freq(struct jh7110_clk_pll_data *data, unsign= ed long parent_rate) +{ + u32 dacpd; + u32 dsmpd; + u32 fbdiv; + u32 prediv; + u32 postdiv1; + u32 frac; + u32 reg_value; + unsigned long frac_cal; + unsigned long freq; + struct pll_syscon_offset *offset =3D &data->offset; + struct pll_syscon_mask *mask =3D &data->mask; + struct pll_syscon_shift *shift =3D &data->shift; + struct jh7110_clk_pll_priv *priv =3D jh7110_pll_priv_from(data); + + if (regmap_read(priv->syscon_regmap, + offset->dacpd_offset, ®_value)) + goto read_register_error; + dacpd =3D (reg_value & mask->dacpd_mask) >> shift->dacpd_shift; + + if (regmap_read(priv->syscon_regmap, + offset->dsmpd_offset, ®_value)) + goto read_register_error; + dsmpd =3D (reg_value & mask->dsmpd_mask) >> shift->dsmpd_shift; + + if (regmap_read(priv->syscon_regmap, + offset->fbdiv_offset, ®_value)) + goto read_register_error; + fbdiv =3D (reg_value & mask->fbdiv_mask) >> shift->fbdiv_shift; + /* fbdiv value should be 8 to 4095 */ + if (fbdiv < 8) + goto read_register_error; + + if (regmap_read(priv->syscon_regmap, + offset->prediv_offset, ®_value)) + goto read_register_error; + prediv =3D (reg_value & mask->prediv_mask) >> shift->prediv_shift; + + if (regmap_read(priv->syscon_regmap, + offset->postdiv1_offset, ®_value)) + goto read_register_error; + /* postdiv1 =3D 2 ^ reg_value */ + postdiv1 =3D 1 << ((reg_value & mask->postdiv1_mask) >> + shift->postdiv1_shift); + + if (regmap_read(priv->syscon_regmap, + offset->frac_offset, ®_value)) + goto read_register_error; + frac =3D (reg_value & mask->frac_mask) >> shift->frac_shift; + + /* Integer Mode or Fraction Mode */ + /* The decimal places are counted by expanding them by a factor of FRAC_P= ATR_SIZE. */ + if (dacpd =3D=3D 1 && dsmpd =3D=3D 1) + frac_cal =3D 0; + else + frac_cal =3D (unsigned long)frac * FRAC_PATR_SIZE / (1 << 24); + + freq =3D parent_rate / FRAC_PATR_SIZE * + (fbdiv * FRAC_PATR_SIZE + frac_cal) / prediv / postdiv1; + + dev_dbg(priv->dev, "pll%d calculate freq:%ld\n", data->idx, freq); + return freq; + +read_register_error: + dev_err(priv->dev, "PLL read syscon error.\n"); + return 0; +} + +static int pll_select_freq_syscon(struct jh7110_clk_pll_data *data, unsign= ed long target_rate) +{ + unsigned int id; + unsigned int pll_arry_size; + const struct starfive_pll_syscon_value *syscon_value; + struct jh7110_clk_pll_priv *priv =3D jh7110_pll_priv_from(data); + + if (data->idx =3D=3D JH7110_CLK_PLL0_OUT) + pll_arry_size =3D ARRAY_SIZE(jh7110_pll0_syscon_freq); + else if (data->idx =3D=3D JH7110_CLK_PLL1_OUT) + pll_arry_size =3D ARRAY_SIZE(jh7110_pll1_syscon_freq); + else + pll_arry_size =3D ARRAY_SIZE(jh7110_pll2_syscon_freq); + + for (id =3D 0; id < pll_arry_size; id++) { + if (data->idx =3D=3D JH7110_CLK_PLL0_OUT) + syscon_value =3D &jh7110_pll0_syscon_freq[id]; + else if (data->idx =3D=3D JH7110_CLK_PLL1_OUT) + syscon_value =3D &jh7110_pll1_syscon_freq[id]; + else + syscon_value =3D &jh7110_pll2_syscon_freq[id]; + + if (target_rate =3D=3D syscon_value->freq) + goto select_end; + } + + dev_err(priv->dev, "pll%d frequency:%ld do not match, please check it.\n", + data->idx, target_rate); + return -EINVAL; + +select_end: + data->freq_select_idx =3D id; + return 0; +} + +static int pll_set_freq_syscon(struct jh7110_clk_pll_data *data) +{ + int ret; + const struct starfive_pll_syscon_value *syscon_value; + unsigned int freq_idx =3D data->freq_select_idx; + struct pll_syscon_offset *offset =3D &data->offset; + struct pll_syscon_mask *mask =3D &data->mask; + struct pll_syscon_shift *shift =3D &data->shift; + struct jh7110_clk_pll_priv *priv =3D jh7110_pll_priv_from(data); + + if (data->idx =3D=3D JH7110_CLK_PLL0_OUT) + syscon_value =3D &jh7110_pll0_syscon_freq[freq_idx]; + else if (data->idx =3D=3D JH7110_CLK_PLL1_OUT) + syscon_value =3D &jh7110_pll1_syscon_freq[freq_idx]; + else + syscon_value =3D &jh7110_pll2_syscon_freq[freq_idx]; + + ret =3D regmap_update_bits(priv->syscon_regmap, offset->dacpd_offset, mas= k->dacpd_mask, + (syscon_value->dacpd << shift->dacpd_shift)); + if (ret) + goto set_failed; + + ret =3D regmap_update_bits(priv->syscon_regmap, offset->dsmpd_offset, mas= k->dsmpd_mask, + (syscon_value->dsmpd << shift->dsmpd_shift)); + if (ret) + goto set_failed; + + ret =3D regmap_update_bits(priv->syscon_regmap, offset->prediv_offset, ma= sk->prediv_mask, + (syscon_value->prediv << shift->prediv_shift)); + if (ret) + goto set_failed; + + ret =3D regmap_update_bits(priv->syscon_regmap, offset->fbdiv_offset, mas= k->fbdiv_mask, + (syscon_value->fbdiv << shift->fbdiv_shift)); + if (ret) + goto set_failed; + + ret =3D regmap_update_bits(priv->syscon_regmap, offset->postdiv1_offset, + mask->postdiv1_mask, + ((syscon_value->postdiv1 >> 1) << shift->postdiv1_shift)); + if (ret) + goto set_failed; + /* frac */ + if (syscon_value->dacpd =3D=3D 0 && syscon_value->dsmpd =3D=3D 0) { + ret =3D regmap_update_bits(priv->syscon_regmap, offset->frac_offset, + mask->frac_mask, + (syscon_value->frac << shift->frac_shift)); + if (ret) + goto set_failed; + } + + dev_dbg(priv->dev, "pll%d set syscon register done and rate is %ld\n", + data->idx, syscon_value->freq); + return 0; + +set_failed: + dev_err(priv->dev, "pll set syscon failed:%d\n", ret); + return ret; +} + +static unsigned long jh7110_clk_pll_recalc_rate(struct clk_hw *hw, unsigne= d long parent_rate) +{ + struct jh7110_clk_pll_data *data =3D jh7110_pll_data_from(hw); + + return pll_get_freq(data, parent_rate); +} + +static int jh7110_clk_pll_determine_rate(struct clk_hw *hw, struct clk_rat= e_request *req) +{ + int ret; + struct jh7110_clk_pll_data *data =3D jh7110_pll_data_from(hw); + + ret =3D pll_select_freq_syscon(data, req->rate); + if (ret) + return ret; + + if (data->idx =3D=3D JH7110_CLK_PLL0_OUT) + req->rate =3D jh7110_pll0_syscon_freq[data->freq_select_idx].freq; + else if (data->idx =3D=3D JH7110_CLK_PLL1_OUT) + req->rate =3D jh7110_pll1_syscon_freq[data->freq_select_idx].freq; + else + req->rate =3D jh7110_pll2_syscon_freq[data->freq_select_idx].freq; + + return 0; +} + +static int jh7110_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct jh7110_clk_pll_data *data =3D jh7110_pll_data_from(hw); + + return pll_set_freq_syscon(data); +} + +#ifdef CONFIG_DEBUG_FS +static void jh7110_clk_pll_debug_init(struct clk_hw *hw, struct dentry *de= ntry) +{ + static const struct debugfs_reg32 jh7110_clk_pll_reg =3D { + .name =3D "CTRL", + .offset =3D 0, + }; + struct jh7110_clk_pll_data *data =3D jh7110_pll_data_from(hw); + struct jh7110_clk_pll_priv *priv =3D jh7110_pll_priv_from(data); + struct debugfs_regset32 *regset; + + regset =3D devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL); + if (!regset) + return; + + regset->regs =3D &jh7110_clk_pll_reg; + regset->nregs =3D 1; + + debugfs_create_regset32("registers", 0400, dentry, regset); +} +#else +#define jh7110_clk_pll_debug_init NULL +#endif + +static const struct clk_ops jh7110_clk_pll_ops =3D { + .recalc_rate =3D jh7110_clk_pll_recalc_rate, + .determine_rate =3D jh7110_clk_pll_determine_rate, + .set_rate =3D jh7110_clk_pll_set_rate, + .debug_init =3D jh7110_clk_pll_debug_init, +}; + +static int pll_data_offset_get(struct jh7110_clk_pll_data *data, int index) +{ + struct pll_syscon_offset *offset =3D &data->offset; + struct pll_syscon_mask *mask =3D &data->mask; + struct pll_syscon_shift *shift =3D &data->shift; + + if (index =3D=3D JH7110_CLK_PLL0_OUT) { + offset->dacpd_offset =3D PLL0_DACPD_OFFSET; + offset->dsmpd_offset =3D PLL0_DSMPD_OFFSET; + offset->fbdiv_offset =3D PLL0_FBDIV_OFFSET; + offset->frac_offset =3D PLL0_FRAC_OFFSET; + offset->prediv_offset =3D PLL0_PREDIV_OFFSET; + offset->postdiv1_offset =3D PLL0_POSTDIV1_OFFSET; + + mask->dacpd_mask =3D PLL0_DACPD_MASK; + mask->dsmpd_mask =3D PLL0_DSMPD_MASK; + mask->fbdiv_mask =3D PLL0_FBDIV_MASK; + mask->frac_mask =3D PLL0_FRAC_MASK; + mask->prediv_mask =3D PLL0_PREDIV_MASK; + mask->postdiv1_mask =3D PLL0_POSTDIV1_MASK; + + shift->dacpd_shift =3D PLL0_DACPD_SHIFT; + shift->dsmpd_shift =3D PLL0_DSMPD_SHIFT; + shift->fbdiv_shift =3D PLL0_FBDIV_SHIFT; + shift->frac_shift =3D PLL0_FRAC_SHIFT; + shift->prediv_shift =3D PLL0_PREDIV_SHIFT; + shift->postdiv1_shift =3D PLL0_POSTDIV1_SHIFT; + } else if (index =3D=3D JH7110_CLK_PLL1_OUT) { + offset->dacpd_offset =3D PLL1_DACPD_OFFSET; + offset->dsmpd_offset =3D PLL1_DSMPD_OFFSET; + offset->fbdiv_offset =3D PLL1_FBDIV_OFFSET; + offset->frac_offset =3D PLL1_FRAC_OFFSET; + offset->prediv_offset =3D PLL1_PREDIV_OFFSET; + offset->postdiv1_offset =3D PLL1_POSTDIV1_OFFSET; + + mask->dacpd_mask =3D PLL1_DACPD_MASK; + mask->dsmpd_mask =3D PLL1_DSMPD_MASK; + mask->fbdiv_mask =3D PLL1_FBDIV_MASK; + mask->frac_mask =3D PLL1_FRAC_MASK; + mask->prediv_mask =3D PLL1_PREDIV_MASK; + mask->postdiv1_mask =3D PLL1_POSTDIV1_MASK; + + shift->dacpd_shift =3D PLL1_DACPD_SHIFT; + shift->dsmpd_shift =3D PLL1_DSMPD_SHIFT; + shift->fbdiv_shift =3D PLL1_FBDIV_SHIFT; + shift->frac_shift =3D PLL1_FRAC_SHIFT; + shift->prediv_shift =3D PLL1_PREDIV_SHIFT; + shift->postdiv1_shift =3D PLL1_POSTDIV1_SHIFT; + } else if (index =3D=3D JH7110_CLK_PLL2_OUT) { + offset->dacpd_offset =3D PLL2_DACPD_OFFSET; + offset->dsmpd_offset =3D PLL2_DSMPD_OFFSET; + offset->fbdiv_offset =3D PLL2_FBDIV_OFFSET; + offset->frac_offset =3D PLL2_FRAC_OFFSET; + offset->prediv_offset =3D PLL2_PREDIV_OFFSET; + offset->postdiv1_offset =3D PLL2_POSTDIV1_OFFSET; + + mask->dacpd_mask =3D PLL2_DACPD_MASK; + mask->dsmpd_mask =3D PLL2_DSMPD_MASK; + mask->fbdiv_mask =3D PLL2_FBDIV_MASK; + mask->frac_mask =3D PLL2_FRAC_MASK; + mask->prediv_mask =3D PLL2_PREDIV_MASK; + mask->postdiv1_mask =3D PLL2_POSTDIV1_MASK; + + shift->dacpd_shift =3D PLL2_DACPD_SHIFT; + shift->dsmpd_shift =3D PLL2_DSMPD_SHIFT; + shift->fbdiv_shift =3D PLL2_FBDIV_SHIFT; + shift->frac_shift =3D PLL2_FRAC_SHIFT; + shift->prediv_shift =3D PLL2_PREDIV_SHIFT; + shift->postdiv1_shift =3D PLL2_POSTDIV1_SHIFT; + } else { + return -ENOENT; + } + + return 0; +} + +static struct clk_hw *jh7110_pll_clk_get(struct of_phandle_args *clkspec, = void *data) +{ + struct jh7110_clk_pll_priv *priv =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx < JH7110_PLLCLK_END) + return &priv->data[idx].hw; + + return ERR_PTR(-EINVAL); +} + +static int jh7110_pll_clk_probe(struct platform_device *pdev) +{ + int ret; + struct of_phandle_args args; + struct regmap *pll_syscon_regmap; + unsigned int idx; + struct jh7110_clk_pll_priv *priv; + struct jh7110_clk_pll_data *data; + char *pll_name[JH7110_PLLCLK_END] =3D { + "pll0_out", + "pll1_out", + "pll2_out" + }; + + priv =3D devm_kzalloc(&pdev->dev, + struct_size(priv, data, JH7110_PLLCLK_END), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D &pdev->dev; + ret =3D of_parse_phandle_with_fixed_args(pdev->dev.of_node, "starfive,sys= reg", 0, 0, &args); + if (ret) { + dev_err(&pdev->dev, "Failed to parse starfive,sys-syscon : %d\n", ret); + return ret; + } + + pll_syscon_regmap =3D syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(pll_syscon_regmap)) + return PTR_ERR(pll_syscon_regmap); + + priv->syscon_regmap =3D pll_syscon_regmap; + + for (idx =3D 0; idx < JH7110_PLLCLK_END; idx++) { + struct clk_parent_data parents =3D { + .index =3D 0, + }; + struct clk_init_data init =3D { + .name =3D pll_name[idx], + .ops =3D &jh7110_clk_pll_ops, + .parent_data =3D &parents, + .num_parents =3D 1, + .flags =3D 0, + }; + + data =3D &priv->data[idx]; + + ret =3D pll_data_offset_get(data, idx); + if (ret) + return ret; + + data->hw.init =3D &init; + data->idx =3D idx; + + ret =3D devm_clk_hw_register(&pdev->dev, &data->hw); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_clk_get, priv); +} + +static const struct of_device_id jh7110_pll_clk_match[] =3D { + { .compatible =3D "starfive,jh7110-pll" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_pll_clk_match); + +static struct platform_driver jh7110_pll_clk_driver =3D { + .driver =3D { + .name =3D "clk-starfive-jh7110-pll", + .of_match_table =3D jh7110_pll_clk_match, + }, +}; +builtin_platform_driver_probe(jh7110_pll_clk_driver, jh7110_pll_clk_probe); diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.h b/drivers/clk/s= tarfive/clk-starfive-jh7110-pll.h new file mode 100644 index 000000000000..813477e29514 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * StarFive JH7110 PLL Clock Generator Driver + * + * Copyright (C) 2022 Xingyu Wu + */ + +#ifndef _CLK_STARFIVE_JH7110_PLL_H_ +#define _CLK_STARFIVE_JH7110_PLL_H_ + +/* The decimal places are counted by expanding them by a factor of FRAC_PA= TR_SIZE. */ +#define FRAC_PATR_SIZE 1000 + +#define PLL0_DACPD_OFFSET 0x18 +#define PLL0_DACPD_SHIFT 24 +#define PLL0_DACPD_MASK 0x1000000 +#define PLL0_DSMPD_OFFSET 0x18 +#define PLL0_DSMPD_SHIFT 25 +#define PLL0_DSMPD_MASK 0x2000000 +#define PLL0_FBDIV_OFFSET 0x1c +#define PLL0_FBDIV_SHIFT 0 +#define PLL0_FBDIV_MASK 0xFFF +#define PLL0_FRAC_OFFSET 0x20 +#define PLL0_FRAC_SHIFT 0 +#define PLL0_FRAC_MASK 0xFFFFFF +#define PLL0_POSTDIV1_OFFSET 0x20 +#define PLL0_POSTDIV1_SHIFT 28 +#define PLL0_POSTDIV1_MASK 0x30000000 +#define PLL0_PREDIV_OFFSET 0x24 +#define PLL0_PREDIV_SHIFT 0 +#define PLL0_PREDIV_MASK 0x3F + +#define PLL1_DACPD_OFFSET 0x24 +#define PLL1_DACPD_SHIFT 15 +#define PLL1_DACPD_MASK 0x8000 +#define PLL1_DSMPD_OFFSET 0x24 +#define PLL1_DSMPD_SHIFT 16 +#define PLL1_DSMPD_MASK 0x10000 +#define PLL1_FBDIV_OFFSET 0x24 +#define PLL1_FBDIV_SHIFT 17 +#define PLL1_FBDIV_MASK 0x1FFE0000 +#define PLL1_FRAC_OFFSET 0x28 +#define PLL1_FRAC_SHIFT 0 +#define PLL1_FRAC_MASK 0xFFFFFF +#define PLL1_POSTDIV1_OFFSET 0x28 +#define PLL1_POSTDIV1_SHIFT 28 +#define PLL1_POSTDIV1_MASK 0x30000000 +#define PLL1_PREDIV_OFFSET 0x2c +#define PLL1_PREDIV_SHIFT 0 +#define PLL1_PREDIV_MASK 0x3F + +#define PLL2_DACPD_OFFSET 0x2c +#define PLL2_DACPD_SHIFT 15 +#define PLL2_DACPD_MASK 0x8000 +#define PLL2_DSMPD_OFFSET 0x2c +#define PLL2_DSMPD_SHIFT 16 +#define PLL2_DSMPD_MASK 0x10000 +#define PLL2_FBDIV_OFFSET 0x2c +#define PLL2_FBDIV_SHIFT 17 +#define PLL2_FBDIV_MASK 0x1FFE0000 +#define PLL2_FRAC_OFFSET 0x30 +#define PLL2_FRAC_SHIFT 0 +#define PLL2_FRAC_MASK 0xFFFFFF +#define PLL2_POSTDIV1_OFFSET 0x30 +#define PLL2_POSTDIV1_SHIFT 28 +#define PLL2_POSTDIV1_MASK 0x30000000 +#define PLL2_PREDIV_OFFSET 0x34 +#define PLL2_PREDIV_SHIFT 0 +#define PLL2_PREDIV_MASK 0x3F + +struct pll_syscon_offset { + u32 dacpd_offset; + u32 dsmpd_offset; + u32 fbdiv_offset; + u32 frac_offset; + u32 prediv_offset; + u32 postdiv1_offset; +}; + +struct pll_syscon_mask { + u32 dacpd_mask; + u32 dsmpd_mask; + u32 fbdiv_mask; + u32 frac_mask; + u32 prediv_mask; + u32 postdiv1_mask; +}; + +struct pll_syscon_shift { + u32 dacpd_shift; + u32 dsmpd_shift; + u32 fbdiv_shift; + u32 frac_shift; + u32 prediv_shift; + u32 postdiv1_shift; +}; + +struct jh7110_clk_pll_data { + struct clk_hw hw; + unsigned int idx; + unsigned int freq_select_idx; + + struct pll_syscon_offset offset; + struct pll_syscon_mask mask; + struct pll_syscon_shift shift; +}; + +struct jh7110_clk_pll_priv { + struct device *dev; + struct regmap *syscon_regmap; + struct jh7110_clk_pll_data data[]; +}; + +struct starfive_pll_syscon_value { + unsigned long freq; + u32 prediv; + u32 fbdiv; + u32 postdiv1; +/* Both daxpd and dsmpd set 1 while integer multiple mode */ +/* Both daxpd and dsmpd set 0 while fraction multiple mode */ + u32 dacpd; + u32 dsmpd; +/* frac value should be decimals multiplied by 2^24 */ + u32 frac; +}; + +enum starfive_pll0_freq { + PLL0_FREQ_375 =3D 0, + PLL0_FREQ_500, + PLL0_FREQ_625, + PLL0_FREQ_750, + PLL0_FREQ_875, + PLL0_FREQ_1000, + PLL0_FREQ_1250, + PLL0_FREQ_1375, + PLL0_FREQ_1500, + PLL0_FREQ_MAX +}; + +enum starfive_pll1_freq { + PLL1_FREQ_1066 =3D 0, + PLL1_FREQ_1200, + PLL1_FREQ_1400, + PLL1_FREQ_1600, + PLL1_FREQ_MAX +}; + +enum starfive_pll2_freq { + PLL2_FREQ_1188 =3D 0, + PLL2_FREQ_12288, + PLL2_FREQ_MAX +}; + +static const struct starfive_pll_syscon_value + jh7110_pll0_syscon_freq[] =3D { + [PLL0_FREQ_375] =3D { + .freq =3D 375000000, + .prediv =3D 8, + .fbdiv =3D 125, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_500] =3D { + .freq =3D 500000000, + .prediv =3D 6, + .fbdiv =3D 125, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_625] =3D { + .freq =3D 625000000, + .prediv =3D 24, + .fbdiv =3D 625, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_750] =3D { + .freq =3D 750000000, + .prediv =3D 4, + .fbdiv =3D 125, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_875] =3D { + .freq =3D 875000000, + .prediv =3D 24, + .fbdiv =3D 875, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_1000] =3D { + .freq =3D 1000000000, + .prediv =3D 3, + .fbdiv =3D 125, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_1250] =3D { + .freq =3D 1250000000, + .prediv =3D 12, + .fbdiv =3D 625, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_1375] =3D { + .freq =3D 1375000000, + .prediv =3D 24, + .fbdiv =3D 1375, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL0_FREQ_1500] =3D { + .freq =3D 1500000000, + .prediv =3D 2, + .fbdiv =3D 125, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, +}; + +static const struct starfive_pll_syscon_value + jh7110_pll1_syscon_freq[] =3D { + [PLL1_FREQ_1066] =3D { + .freq =3D 1066000000, + .prediv =3D 12, + .fbdiv =3D 533, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL1_FREQ_1200] =3D { + .freq =3D 1200000000, + .prediv =3D 1, + .fbdiv =3D 50, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL1_FREQ_1400] =3D { + .freq =3D 1400000000, + .prediv =3D 6, + .fbdiv =3D 350, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL1_FREQ_1600] =3D { + .freq =3D 1600000000, + .prediv =3D 3, + .fbdiv =3D 200, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, +}; + +static const struct starfive_pll_syscon_value + jh7110_pll2_syscon_freq[] =3D { + [PLL2_FREQ_1188] =3D { + .freq =3D 1188000000, + .prediv =3D 2, + .fbdiv =3D 99, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, + [PLL2_FREQ_12288] =3D { + .freq =3D 1228800000, + .prediv =3D 5, + .fbdiv =3D 256, + .postdiv1 =3D 1, + .dacpd =3D 1, + .dsmpd =3D 1, + }, +}; + +#endif diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/s= tarfive/clk-starfive-jh7110-sys.c index 6e230b81a387..228119b55a93 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -26,6 +26,9 @@ #define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6) #define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7) #define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8) +#define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_END + 9) +#define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10) +#define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11) =20 static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst =3D { /* root */ @@ -329,11 +332,8 @@ static struct clk_hw *jh7110_sysclk_get(struct of_phan= dle_args *clkspec, void *d struct jh71x0_clk_priv *priv =3D data; unsigned int idx =3D clkspec->args[0]; =20 - if (idx < JH7110_SYSCLK_PLL0_OUT) - return &priv->reg[idx].hw; - if (idx < JH7110_SYSCLK_END) - return priv->pll[idx - JH7110_SYSCLK_PLL0_OUT]; + return &priv->reg[idx].hw; =20 return ERR_PTR(-EINVAL); } @@ -345,7 +345,7 @@ static int __init jh7110_syscrg_probe(struct platform_d= evice *pdev) int ret; =20 priv =3D devm_kzalloc(&pdev->dev, - struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT), + struct_size(priv, reg, JH7110_SYSCLK_END), GFP_KERNEL); if (!priv) return -ENOMEM; @@ -358,25 +358,7 @@ static int __init jh7110_syscrg_probe(struct platform_= device *pdev) =20 dev_set_drvdata(priv->dev, (void *)(&priv->base)); =20 - /* 24MHz -> 1000.0MHz */ - priv->pll[0] =3D devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", - "osc", 0, 125, 3); - if (IS_ERR(priv->pll[0])) - return PTR_ERR(priv->pll[0]); - - /* 24MHz -> 1066.0MHz */ - priv->pll[1] =3D devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", - "osc", 0, 533, 12); - if (IS_ERR(priv->pll[1])) - return PTR_ERR(priv->pll[1]); - - /* 24MHz -> 1188.0MHz */ - priv->pll[2] =3D devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", - "osc", 0, 99, 2); - if (IS_ERR(priv->pll[2])) - return PTR_ERR(priv->pll[2]); - - for (idx =3D 0; idx < JH7110_SYSCLK_PLL0_OUT; idx++) { + for (idx =3D 0; idx < JH7110_SYSCLK_END; idx++) { u32 max =3D jh7110_sysclk_data[idx].max; struct clk_parent_data parents[4] =3D {}; struct clk_init_data init =3D { @@ -393,10 +375,8 @@ static int __init jh7110_syscrg_probe(struct platform_= device *pdev) for (i =3D 0; i < init.num_parents; i++) { unsigned int pidx =3D jh7110_sysclk_data[idx].parents[i]; =20 - if (pidx < JH7110_SYSCLK_PLL0_OUT) + if (pidx < JH7110_SYSCLK_END) parents[i].hw =3D &priv->reg[pidx].hw; - else if (pidx < JH7110_SYSCLK_END) - parents[i].hw =3D priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; else if (pidx =3D=3D JH7110_SYSCLK_OSC) parents[i].fw_name =3D "osc"; else if (pidx =3D=3D JH7110_SYSCLK_GMAC1_RMII_REFIN) @@ -415,6 +395,12 @@ static int __init jh7110_syscrg_probe(struct platform_= device *pdev) parents[i].fw_name =3D "tdm_ext"; else if (pidx =3D=3D JH7110_SYSCLK_MCLK_EXT) parents[i].fw_name =3D "mclk_ext"; + else if (pidx =3D=3D JH7110_SYSCLK_PLL0_OUT) + parents[i].fw_name =3D "pll0_out"; + else if (pidx =3D=3D JH7110_SYSCLK_PLL1_OUT) + parents[i].fw_name =3D "pll1_out"; + else if (pidx =3D=3D JH7110_SYSCLK_PLL2_OUT) + parents[i].fw_name =3D "pll2_out"; } =20 clk->hw.init =3D &init; --=20 2.25.1