From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94DA3C6379F for ; Tue, 21 Feb 2023 12:15:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234091AbjBUMPi (ORCPT ); Tue, 21 Feb 2023 07:15:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234429AbjBUMP1 (ORCPT ); Tue, 21 Feb 2023 07:15:27 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74F2E4499; Tue, 21 Feb 2023 04:14:59 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6KHE021153; Tue, 21 Feb 2023 06:06:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676981180; bh=ZgK1Q7UxoYFIJ7lBntlYuht9796aFLvImb8AVSWmmFs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HwuVv2cyqpPmMR792sSOZiB4KU1SyyzuTj/QvWNO/GyaZXqToyzUT7mDWfFNz3lL5 ztkAtJEK/DzETm2cUC/sFplXZEyxsbUoPhVPwVSGQsge4SNmvrkSZRpgVY7JIf2rVI LqWS575u6e0U/gzyV4LR3IHPk5+k00EFNJnbuW0A= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31LC6KuV125664 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Feb 2023 06:06:20 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:20 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:20 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbO030829; Tue, 21 Feb 2023 06:06:17 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 1/9] dt-bindings: mfd: ti,j721e-system-controller: Fix mux node regex Date: Tue, 21 Feb 2023 17:36:04 +0530 Message-ID: <20230221120612.27366-2-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mux-controller nodes may not have "reg" property. Update the regex for such nodes to resolve the dtbs warnings Signed-off-by: Ravi Gunasekaran --- .../bindings/mfd/ti,j721e-system-controller.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controll= er.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.= yaml index 76ef4352e13c..532bfa45e6a0 100644 --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml @@ -45,7 +45,7 @@ properties: =20 patternProperties: # Optional children - "^mux-controller@[0-9a-f]+$": + "^mux-controller(@|-)[0-9a-f]+$": type: object description: This is the SERDES lane control mux. @@ -94,6 +94,12 @@ examples: /* SERDES4 lane0/1/2/3 select */ }; =20 + usb_serdes_mux: mux-controller-80 { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x0 0x8000000>; + }; + clock-controller@4140 { compatible =3D "ti,am654-ehrpwm-tbclk", "syscon"; reg =3D <0x4140 0x18>; --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A822C61DA3 for ; Tue, 21 Feb 2023 12:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234692AbjBUMIa (ORCPT ); Tue, 21 Feb 2023 07:08:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234685AbjBUMI1 (ORCPT ); Tue, 21 Feb 2023 07:08:27 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21FF35B86; Tue, 21 Feb 2023 04:07:50 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6OcI053088; Tue, 21 Feb 2023 06:06:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676981184; bh=cExpIumSTLuVMmqSbxDSSZTlNuqqHrIuMxc8UKNUbgU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CZ0GZrGXjkFwxpcIhXkI/mCGB5cxd80oO6wBZEvLaTH/ZyolnSiLUYlbUEi6s4zgO zTjwJWxfvB5mBNV63JLQ/7Sz1aUM/G444+7QRiCNH2x9yrY0OnrGiSUAyvlOG8Toiv 7pXb3T0ORt2985j7Wm1OgRxIwFKJqUr3bxGsYjoY= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31LC6O4J125754 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Feb 2023 06:06:24 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:24 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:23 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbP030829; Tue, 21 Feb 2023 06:06:20 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 2/9] arm64: dts: ti: k3-j721s2-main: Add support for USB Date: Tue, 21 Feb 2023 17:36:05 +0530 Message-ID: <20230221120612.27366-3-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-2-mranostay@ti.com Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v5 series [1]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. Links: [1] - https://lore.kernel.org/all/134c28a0-2d49-549c-dc8d-0887d8fd29c3@ti.c= om/ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 8915132efcc1..84e5689fff9f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -26,6 +26,20 @@ }; }; =20 + scm_conf: syscon@104000 { + compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg =3D <0x00 0x00104000 0x00 0x18000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + }; + gic500: interrupt-controller@1800000 { compatible =3D "arm,gic-v3"; #address-cells =3D <2>; @@ -745,6 +759,38 @@ }; }; =20 + usbss0: cdns-usb@4104000 { + compatible =3D "ti,j721e-usb"; + reg =3D <0x00 0x04104000 0x00 0x100>; + clocks =3D <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names =3D "ref", "lpm"; + assigned-clocks =3D <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents =3D <&k3_clks 360 17>; + power-domains =3D <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-coherent; + + status =3D "disabled"; + + usb0: usb@6000000 { + compatible =3D "cdns,usb3"; + reg =3D <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D , + , + ; + interrupt-names =3D "host", "peripheral", "otg"; + maximum-speed =3D "super-speed"; + dr_mode =3D "otg"; + + status =3D "disabled"; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90409C6379F for ; Tue, 21 Feb 2023 12:17:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234382AbjBUMRF (ORCPT ); Tue, 21 Feb 2023 07:17:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234384AbjBUMRA (ORCPT ); Tue, 21 Feb 2023 07:17:00 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEA1728D1A; Tue, 21 Feb 2023 04:16:19 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6R2H021167; Tue, 21 Feb 2023 06:06:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676981188; bh=STaZP5eMagXDr9/1rKY8OPG84+UZYc/AF85n7ywcYYQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N0Riutxk+MKUA8TmMjwksi7mZ+XPB3xBQ5cRkT9S3LLpM9RNR0RI7g/PBF/n1quDZ /o0QaKsh3XrHKHrLMe3+SC/NyFsdWlHWGHxPsfRoVu9GN1ero+Yl597v5b4x+zS88U cQ1zR+LwZcNQs+Upl0hHQC01/OJ059L3cubgGySw= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31LC6RDm125793 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Feb 2023 06:06:27 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:27 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:27 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbQ030829; Tue, 21 Feb 2023 06:06:24 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 3/9] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Date: Tue, 21 Feb 2023 17:36:06 +0530 Message-ID: <20230221120612.27366-4-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-3-mranostay@ti.com Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v7 series [1]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. Links: [1] - https://lore.kernel.org/lkml/4173e0c6-61d9-5b79-44ec-317870de070b@ti.= com/ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 60 +++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 84e5689fff9f..af6c93f0a055 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ =20 +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible =3D "mmio-sram"; @@ -33,11 +44,18 @@ #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00104000 0x18000>; =20 - usb_serdes_mux: mux-controller@0 { + usb_serdes_mux: mux-controller-0 { compatible =3D "mmio-mux"; #mux-control-cells =3D <1>; mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + + serdes_ln_ctrl: mux-controller-80 { + compatible =3D "mmio-mux"; + #mux-control-cells =3D <1>; + mux-reg-masks =3D <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; }; =20 gic500: interrupt-controller@1800000 { @@ -791,6 +809,46 @@ }; }; =20 + serdes_wiz0: wiz@5060000 { + compatible =3D "ti,j721s2-wiz-10g"; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names =3D "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes =3D <4>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + ranges =3D <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks =3D <&k3_clks 365 3>; + assigned-clock-parents =3D <&k3_clks 365 7>; + + status =3D "disabled"; + + serdes0: serdes@5060000 { + compatible =3D "ti,j721e-serdes-10g"; + reg =3D <0x05060000 0x00010000>; + reg-names =3D "torrent_phy"; + resets =3D <&serdes_wiz0 0>; + reset-names =3D "torrent_reset"; + clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names =3D "refclk", "phy_en_refclk"; + assigned-clocks =3D <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents =3D <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + + status =3D "disabled"; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD098C6379F for ; Tue, 21 Feb 2023 13:42:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234060AbjBUNmh (ORCPT ); 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Tue, 21 Feb 2023 06:06:31 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:31 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:31 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbR030829; Tue, 21 Feb 2023 06:06:28 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 4/9] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Date: Tue, 21 Feb 2023 17:36:07 +0530 Message-ID: <20230221120612.27366-5-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add support for two instance of OSPI in J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Reviewed-by: Vaishnav Achath Link: https://lore.kernel.org/r/20221122101616.770050-4-mranostay@ti.com Signed-off-by: Ravi Gunasekaran --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..7e0e608578e1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,51 @@ ti,cpts-periodic-outputs =3D <2>; }; }; + + fss: bus@47000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + status =3D "disabled"; + + ospi0: spi@47040000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 109 5>; + assigned-clocks =3D <&k3_clks 109 5>; + assigned-clock-parents =3D <&k3_clks 109 7>; + assigned-clock-rates =3D <166666666>; + power-domains =3D <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + ospi1: spi@47050000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 110 5>; + power-domains =3D <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + }; }; --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 528DCC64EC4 for ; Tue, 21 Feb 2023 12:08:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234718AbjBUMIe (ORCPT ); Tue, 21 Feb 2023 07:08:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234705AbjBUMIa (ORCPT ); Tue, 21 Feb 2023 07:08:30 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10A7D16AD1; Tue, 21 Feb 2023 04:07:53 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6ZjD053105; Tue, 21 Feb 2023 06:06:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676981195; bh=+qLiTsayYHbh2GfM0OGFpeGV419NZjeCvNPA06E5bHo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eo+mF2pEvQ0+LnNuURiMHqaonkeP+NPWaSSWWHxP2r/3cxsaDkibBMgxQrRcTeWwt DJxPsdxVoXL9JpSIZmiWaUN6E4adQ/dDl8CLZTeQzgpzLjwb17pqlUEOGjJRjfo0ef QdMY5ibtpYeFw+WvDzig8ljPysh+5h/cuZ2CsaKQ= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31LC6Zib006314 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Feb 2023 06:06:35 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:34 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:34 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbS030829; Tue, 21 Feb 2023 06:06:31 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 5/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Date: Tue, 21 Feb 2023 17:36:08 +0530 Message-ID: <20230221120612.27366-6-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-5-mranostay@ti.com Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v5 series [1]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. Links: [1] - https://lore.kernel.org/all/71ce4ecd-2a50-c69d-28be-f1a8d769970e@ti.c= om/ .../dts/ti/k3-j721s2-common-proc-board.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..907f34ff22a5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ =20 #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include =20 / { compatible =3D "ti,j721s2-evm", "ti,j721s2"; @@ -296,6 +299,30 @@ phy-handle =3D <&phy0>; }; =20 +&serdes_ln_ctrl { + idle-states =3D , , + , ; +}; + +&serdes_refclk { + clock-frequency =3D <100000000>; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&serdes0 { + status =3D "okay"; + serdes0_pcie_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35F59C64EC4 for ; Tue, 21 Feb 2023 12:16:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234318AbjBUMQV (ORCPT ); Tue, 21 Feb 2023 07:16:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233940AbjBUMQT (ORCPT ); Tue, 21 Feb 2023 07:16:19 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D1A925BB4; Tue, 21 Feb 2023 04:15:27 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6cY8021192; Tue, 21 Feb 2023 06:06:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676981198; bh=CNIbcwwC91I2sSzLDl1hacbAFEa/o5qAF2xRE+4EIB8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bOa2LCbcQB8Qg/ehX7STBJOTPjZFEIDHlVCoR0eY03BstAUUSzNJ9/xsYX9RJOv4m r2ZhN6nl0NqgdaE7sZ0okfpR4QYKw0Iii2ONULgjNFJ3NWKZt2u7Q6G2cEz6Mt6+TG odsuDU4N9UQFw83Px/4r5wBJcqXGAtiAobHMmPCA= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31LC6cTZ006333 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Feb 2023 06:06:38 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:38 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:38 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbT030829; Tue, 21 Feb 2023 06:06:35 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 6/9] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support Date: Tue, 21 Feb 2023 17:36:09 +0530 Message-ID: <20230221120612.27366-7-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-6-mranostay@ti.com Signed-off-by: Ravi Gunasekaran Reviewed-by tag. --- I had reviewed this patch in the v5 series [1]. Since I'm taking over upstreaming this series, I removed the self Reviewed-by tag. Links: [1] - https://lore.kernel.org/all/96058a13-4903-2b8c-8de2-f37fdfd3672b@ti.c= om/ .../dts/ti/k3-j721s2-common-proc-board.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 907f34ff22a5..fa38940fe6cd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,12 @@ J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; =20 &wkup_pmx0 { @@ -323,6 +329,24 @@ }; }; =20 +&usb_serdes_mux { + idle-states =3D <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + status =3D "okay"; + pinctrl-0 =3D <&main_usbss0_pins_default>; + pinctrl-names =3D "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + status =3D "okay"; + dr_mode =3D "otg"; + maximum-speed =3D "high-speed"; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64CA6C61DA3 for ; Tue, 21 Feb 2023 12:08:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234722AbjBUMIt (ORCPT ); Tue, 21 Feb 2023 07:08:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234728AbjBUMIo (ORCPT ); Tue, 21 Feb 2023 07:08:44 -0500 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5954B8690; Tue, 21 Feb 2023 04:08:14 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6gu0044757; Tue, 21 Feb 2023 06:06:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1676981202; bh=2XQl5+vFrjlxmT5nCudDl+bB2CLT4xbLK2HQoQEPGsw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LxJolV4cqBDifjGFYD6EIuzW5P+i8u2fUkSJzeZOsNB8wRvSChdMHXstDVc0keuSk DI9TuJNrUbyhVIo3hFs8+qa3JCUglhcurvRaeTfGWUb4dV8Bxtry8VglcF2M8qGVJd KEfepxFImNFaYGcFMdpPuiZSuR/Mg4CGOHswzopU= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 31LC6gPv058182 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Feb 2023 06:06:42 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:41 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:42 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbU030829; Tue, 21 Feb 2023 06:06:38 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 7/9] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes Date: Tue, 21 Feb 2023 17:36:10 +0530 Message-ID: <20230221120612.27366-8-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Reviewed-by: Vaishnav Achath Link: https://lore.kernel.org/r/20221122101616.770050-7-mranostay@ti.com Signed-off-by: Ravi Gunasekaran --- .../dts/ti/k3-j721s2-common-proc-board.dts | 39 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 43 +++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index fa38940fe6cd..76b420379645 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -206,6 +206,20 @@ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; =20 &main_gpio2 { @@ -347,6 +361,31 @@ maximum-speed =3D "high-speed"; }; =20 +&fss { + status =3D "okay"; +}; + +&ospi1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <40000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..9fe255f0576e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ }; }; =20 +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins =3D < @@ -79,3 +101,24 @@ pinctrl-names =3D "default"; phys =3D <&transceiver0>; }; + +&ospi0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-tx-bus-width =3D <8>; + spi-rx-bus-width =3D <8>; + spi-max-frequency =3D <25000000>; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <4>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CEDDC61DA3 for ; Tue, 21 Feb 2023 12:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234711AbjBUMIm (ORCPT ); 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Tue, 21 Feb 2023 06:06:45 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Feb 2023 06:06:45 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Feb 2023 06:06:45 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbV030829; Tue, 21 Feb 2023 06:06:42 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 8/9] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Date: Tue, 21 Feb 2023 17:36:11 +0530 Message-ID: <20230221120612.27366-9-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju Add PCIe1 RC device tree node for the single PCIe instance present on the j721s2. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-8-mranostay@ti.com Signed-off-by: Ravi Gunasekaran --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index af6c93f0a055..c3ca8a016793 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -849,6 +849,49 @@ }; }; =20 + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 41>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb013>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.17.1 From nobody Tue Sep 9 17:43:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D4AEC61DA3 for ; Tue, 21 Feb 2023 12:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234730AbjBUMIp (ORCPT ); Tue, 21 Feb 2023 07:08:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234722AbjBUMIk (ORCPT ); Tue, 21 Feb 2023 07:08:40 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4186B7682; Tue, 21 Feb 2023 04:08:10 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6nZG021211; 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Tue, 21 Feb 2023 06:06:49 -0600 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 31LC6CbW030829; Tue, 21 Feb 2023 06:06:45 -0600 From: Ravi Gunasekaran To: , , , , , , , CC: , , Subject: [PATCH v10 9/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Tue, 21 Feb 2023 17:36:12 +0530 Message-ID: <20230221120612.27366-10-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230221120612.27366-1-r-gunasekaran@ti.com> References: <20230221120612.27366-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Link: https://lore.kernel.org/r/20221122101616.770050-9-mranostay@ti.com Signed-off-by: Ravi Gunasekaran --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 76b420379645..b195f250891a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -386,6 +386,14 @@ }; }; =20 +&pcie1_rc { + status =3D "okay"; + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + num-lanes =3D <1>; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.17.1