From nobody Thu Nov 14 06:37:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49EC3C7618D for ; Tue, 21 Feb 2023 11:58:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234610AbjBUL61 (ORCPT ); Tue, 21 Feb 2023 06:58:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234554AbjBUL5X (ORCPT ); Tue, 21 Feb 2023 06:57:23 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB27328202; Tue, 21 Feb 2023 03:56:50 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7266966021A2; Tue, 21 Feb 2023 11:56:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676980584; bh=OrbmHKPT4S5tKnKiFgQbhyo4lMcbxfeglgNt8q9Xn5U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JpfAVJX+2Z4My4N+1qomIqJXIdOedNxFEyF9oaBoy7Mh5IeW2kHeGZ4MOfOleUWeW cqF9bLIrkbDOjOghHisbfh5hDb6COlhgoHFw4p6kwua0wJMcDxWxDNkym+RUvfI7N7 xTtw/UyuCZ5Yo5vStRBo+jGzI4dOIq+03d27bDQ5w9uA+yJMYJBEORyHsjmTSr1mUp 0qjU0Nf/x8niueM4RQCmOkvFldS9GWZ286gAe9zUeTwHu3VsmGFKsVcXwHIRjpKVq4 nYQ5uR14QzdRMIM/C1CUK8aBKmywoiXt8IkOxZRVnoSlqy4emO253ZanacxUvyBOpU W8876Jy+3SuhA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 22/54] clk: mediatek: Consistently use GATE_MTK() macro Date: Tue, 21 Feb 2023 12:55:17 +0100 Message-Id: <20230221115549.360132-23-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> References: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the various MediaTek clock drivers are, in a way or another, redefining the GATE_MTK() macro with different names: while some are doing that by actually using GATE_MTK(), others are copying it entirely (hence, entirely redefining it). Change all clock drivers to always and consistently use this macro. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2701-aud.c | 40 +++-------- drivers/clk/mediatek/clk-mt2701-bdp.c | 20 ++---- drivers/clk/mediatek/clk-mt2701-eth.c | 10 +-- drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +-- drivers/clk/mediatek/clk-mt2701-hif.c | 10 +-- drivers/clk/mediatek/clk-mt2701-img.c | 10 +-- drivers/clk/mediatek/clk-mt2701-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt2701-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt2701.c | 40 +++-------- drivers/clk/mediatek/clk-mt2712-bdp.c | 10 +-- drivers/clk/mediatek/clk-mt2712-img.c | 10 +-- drivers/clk/mediatek/clk-mt2712-jpgdec.c | 10 +-- drivers/clk/mediatek/clk-mt2712-mfg.c | 10 +-- drivers/clk/mediatek/clk-mt2712-mm.c | 30 ++------ drivers/clk/mediatek/clk-mt2712-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt2712-venc.c | 10 +-- drivers/clk/mediatek/clk-mt2712.c | 66 ++++-------------- drivers/clk/mediatek/clk-mt6765-audio.c | 20 ++---- drivers/clk/mediatek/clk-mt6765-cam.c | 10 +-- drivers/clk/mediatek/clk-mt6765-img.c | 10 +-- drivers/clk/mediatek/clk-mt6765-mipi0a.c | 10 +-- drivers/clk/mediatek/clk-mt6765-mm.c | 10 +-- drivers/clk/mediatek/clk-mt6765-vcodec.c | 10 +-- drivers/clk/mediatek/clk-mt6765.c | 80 +++++----------------- drivers/clk/mediatek/clk-mt6797-img.c | 10 +-- drivers/clk/mediatek/clk-mt6797-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt6797-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt6797-venc.c | 10 +-- drivers/clk/mediatek/clk-mt6797.c | 42 ++++-------- drivers/clk/mediatek/clk-mt7622-aud.c | 40 +++-------- drivers/clk/mediatek/clk-mt7622-eth.c | 20 ++---- drivers/clk/mediatek/clk-mt7622-hif.c | 22 ++---- drivers/clk/mediatek/clk-mt7622.c | 61 ++++------------- drivers/clk/mediatek/clk-mt7629-eth.c | 20 ++---- drivers/clk/mediatek/clk-mt7629-hif.c | 22 ++---- drivers/clk/mediatek/clk-mt7629.c | 40 +++-------- drivers/clk/mediatek/clk-mt7986-eth.c | 24 ++----- drivers/clk/mediatek/clk-mt7986-infracfg.c | 24 ++----- drivers/clk/mediatek/clk-mt8135.c | 30 ++------ drivers/clk/mediatek/clk-mt8167-aud.c | 11 +-- drivers/clk/mediatek/clk-mt8167-img.c | 10 +-- drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 10 +-- drivers/clk/mediatek/clk-mt8167-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt8167-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt8173-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt8516-aud.c | 10 +-- drivers/clk/mediatek/clk-mt8516.c | 60 ++++------------ 47 files changed, 223 insertions(+), 839 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index 1a32d8b7db84..21f7cc106bbe 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -15,41 +15,17 @@ =20 #include =20 -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 static const struct mtk_gate_regs audio0_cg_regs =3D { .set_ofs =3D 0x0, diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/c= lk-mt2701-bdp.c index 435ed4819d56..b0f057207945 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs bdp1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_BDP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &bdp0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_BDP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_BDP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &bdp1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_BDP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate bdp_clks[] =3D { GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index f3cb78e7f6e9..4c830ebdd761 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs eth_cg_regs =3D { .sta_ofs =3D 0x0030, }; =20 -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate eth_clks[] =3D { GATE_DUMMY(CLK_DUMMY, "eth_dummy"), diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 499a170ba5f9..ae094046890a 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -16,14 +16,8 @@ =20 #include =20 -#define GATE_G3D(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &g3d_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_G3D(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &g3d_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate_regs g3d_cg_regs =3D { .sta_ofs =3D 0x0, diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index d5465d782993..3583bd1240d5 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs hif_cg_regs =3D { .sta_ofs =3D 0x0030, }; =20 -#define GATE_HIF(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &hif_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_HIF(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate hif_clks[] =3D { GATE_DUMMY(CLK_DUMMY, "hif_dummy"), diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/c= lk-mt2701-img.c index 7e53deb7f990..eb172473f075 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0000, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/cl= k-mt2701-mm.c index a8d94ca0eefd..993d904d619f 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs disp1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_DISP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &disp0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_DISP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_DISP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &disp1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_DISP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate mm_clks[] =3D { GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/= clk-mt2701-vdec.c index d3089da0ab62..0f07c5d731df 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x0008, }; =20 -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 06ca81359d35..dfe328f7a44b 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -636,14 +636,8 @@ static const struct mtk_gate_regs top_aud_cg_regs =3D { .sta_ofs =3D 0x012C, }; =20 -#define GATE_TOP_AUD(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top_aud_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr) =20 static const struct mtk_gate top_clks[] =3D { GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", @@ -702,14 +696,8 @@ static const struct mtk_gate_regs infra_cg_regs =3D { .sta_ofs =3D 0x0048, }; =20 -#define GATE_ICG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_ICG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate infra_clks[] =3D { GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0), @@ -823,23 +811,11 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { .sta_ofs =3D 0x001c, }; =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate peri_clks[] =3D { GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31), diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/c= lk-mt2712-bdp.c index 684d03e9f6de..5e668651dd90 100644 --- a/drivers/clk/mediatek/clk-mt2712-bdp.c +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs bdp_cg_regs =3D { .sta_ofs =3D 0x100, }; =20 -#define GATE_BDP(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &bdp_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_BDP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) =20 static const struct mtk_gate bdp_clks[] =3D { GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/c= lk-mt2712-img.c index 335049cdc856..3ffa51384e6b 100644 --- a/drivers/clk/mediatek/clk-mt2712-img.c +++ b/drivers/clk/mediatek/clk-mt2712-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediate= k/clk-mt2712-jpgdec.c index 07ba7c5e80af..8c768d5ce24d 100644 --- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs jpgdec_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_JPGDEC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &jpgdec_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_JPGDEC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &jpgdec_cg_regs, _shift, &mtk_clk_gate_ops_= setclr_inv) =20 static const struct mtk_gate jpgdec_clks[] =3D { GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/c= lk-mt2712-mfg.c index 42f8cf3ecf4c..8949315c2dd2 100644 --- a/drivers/clk/mediatek/clk-mt2712-mfg.c +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_MFG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mfg_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/cl= k-mt2712-mm.c index 615f6b0fe96e..850cef9f2009 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -30,32 +30,14 @@ static const struct mtk_gate_regs mm2_cg_regs =3D { .sta_ofs =3D 0x220, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mm_clks[] =3D { /* MM0 */ diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/= clk-mt2712-vdec.c index 6296ed5c5b55..572290dd43c8 100644 --- a/drivers/clk/mediatek/clk-mt2712-vdec.c +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x8, }; =20 -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { /* VDEC0 */ diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/= clk-mt2712-venc.c index b9bfc35de629..9588eb03016e 100644 --- a/drivers/clk/mediatek/clk-mt2712-venc.c +++ b/drivers/clk/mediatek/clk-mt2712-venc.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &venc_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 937c370d6765..d0e6a4fbfa99 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -814,23 +814,11 @@ static const struct mtk_gate_regs top1_cg_regs =3D { .sta_ofs =3D 0x424, }; =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } - -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) =20 static const struct mtk_gate top_clks[] =3D { /* TOP0 */ @@ -854,14 +842,8 @@ static const struct mtk_gate_regs infra_cg_regs =3D { .sta_ofs =3D 0x48, }; =20 -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate infra_clks[] =3D { GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), @@ -891,32 +873,14 @@ static const struct mtk_gate_regs peri2_cg_regs =3D { .sta_ofs =3D 0x42c, }; =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) + +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) + +#define GATE_PERI2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri2_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate peri_clks[] =3D { /* PERI0 */ diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek= /clk-mt6765-audio.c index 0aa6c0d352ca..5682e0302eee 100644 --- a/drivers/clk/mediatek/clk-mt6765-audio.c +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs audio1_cg_regs =3D { .sta_ofs =3D 0x4, }; =20 -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 static const struct mtk_gate audio_clks[] =3D { /* AUDIO0 */ diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/c= lk-mt6765-cam.c index 25f2bef38126..6e7d192c19cb 100644 --- a/drivers/clk/mediatek/clk-mt6765-cam.c +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs cam_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_CAM(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &cam_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_CAM(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate cam_clks[] =3D { GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0), diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/c= lk-mt6765-img.c index a62303ef4f41..cfbc907988af 100644 --- a/drivers/clk/mediatek/clk-mt6765-img.c +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0), diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediate= k/clk-mt6765-mipi0a.c index 25c829fc3866..f2b9dc808480 100644 --- a/drivers/clk/mediatek/clk-mt6765-mipi0a.c +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mipi0a_cg_regs =3D { .sta_ofs =3D 0x80, }; =20 -#define GATE_MIPI0A(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mipi0a_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_MIPI0A(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mipi0a_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 static const struct mtk_gate mipi0a_clks[] =3D { GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A, diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/cl= k-mt6765-mm.c index bda774668a36..a4570c9dbefa 100644 --- a/drivers/clk/mediatek/clk-mt6765-mm.c +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mm_cg_regs =3D { .sta_ofs =3D 0x100, }; =20 -#define GATE_MM(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm_cg_regs, _shift, &mtk_clk_gate_ops_setc= lr) =20 static const struct mtk_gate mm_clks[] =3D { /* MM */ diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediate= k/clk-mt6765-vcodec.c index 2bc1fbde87da..75d72b9b4032 100644 --- a/drivers/clk/mediatek/clk-mt6765-vcodec.c +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &venc_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0), diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index 6f5c92a7f620..0c20ce678350 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -483,32 +483,14 @@ static const struct mtk_gate_regs top2_cg_regs =3D { .sta_ofs =3D 0x320, }; =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) =20 -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 static const struct mtk_gate top_clks[] =3D { /* TOP0 */ @@ -559,41 +541,17 @@ static const struct mtk_gate_regs ifr5_cg_regs =3D { .sta_ofs =3D 0xc8, }; =20 -#define GATE_IFR2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_IFR3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr3_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_IFR4(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr4_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR4(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr4_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_IFR5(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr5_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr5_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 static const struct mtk_gate ifr_clks[] =3D { /* INFRA_TOPAXI */ @@ -674,14 +632,8 @@ static const struct mtk_gate_regs apmixed_cg_regs =3D { .sta_ofs =3D 0x14, }; =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &apmixed_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr_inv) =20 static const struct mtk_gate apmixed_clks[] =3D { /* AUDIO0 */ diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/c= lk-mt6797-img.c index 7c6a53fbb8be..06441393478f 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0000, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11), diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index 706c9775646d..e7a5a43f91f1 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -23,23 +23,11 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ -} +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ -} +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mm_clks[] =3D { GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/= clk-mt6797-vdec.c index 6120fccc859f..8622ddd87a5b 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x0008, }; =20 -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ -} +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ -} +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8), diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/= clk-mt6797-venc.c index 834d3834d2bb..928d611a476e 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs =3D { .sta_ofs =3D 0x0000, }; =20 -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &venc_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index 105a512857b3..17b23ee4faee 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -421,40 +421,22 @@ static const struct mtk_gate_regs infra2_cg_regs =3D { .sta_ofs =3D 0x00b0, }; =20 -#define GATE_ICG0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ -} +#define GATE_ICG0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_ICG1(_id, _name, _parent, _shift) \ - GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_ICG1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - .flags =3D _flags, \ -} +#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) =20 -#define GATE_ICG2(_id, _name, _parent, _shift) \ - GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_ICG2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - .flags =3D _flags, \ -} +#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) =20 /* * Clock gates dramc and dramc_b are needed by the DRAM controller. diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index b8aabfeb1cba..27c543759f2a 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -16,41 +16,17 @@ =20 #include =20 -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 static const struct mtk_gate_regs audio0_cg_regs =3D { .set_ofs =3D 0x0, diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index aee583fa77d0..66b163cc1633 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -16,14 +16,8 @@ =20 #include =20 -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate_regs eth_cg_regs =3D { .set_ofs =3D 0x30, @@ -45,14 +39,8 @@ static const struct mtk_gate_regs sgmii_cg_regs =3D { .sta_ofs =3D 0xE4, }; =20 -#define GATE_SGMII(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &sgmii_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate sgmii_clks[] =3D { GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index ab5cad0c2b1c..bcd1dfc6e8e0 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -16,23 +16,11 @@ =20 #include =20 -#define GATE_PCIE(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &pcie_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } - -#define GATE_SSUSB(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ssusb_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PCIE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_SSUSB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate_regs pcie_cg_regs =3D { .set_ofs =3D 0x30, diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 5a82c2270bfb..41af8d420bbf 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -50,59 +50,24 @@ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ NULL, "clkxtal") =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &apmixed_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv) =20 -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static DEFINE_SPINLOCK(mt7622_clk_lock); =20 diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index a4ae7d6c7a71..719a47fef798 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -16,14 +16,8 @@ =20 #include =20 -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate_regs eth_cg_regs =3D { .set_ofs =3D 0x30, @@ -45,14 +39,8 @@ static const struct mtk_gate_regs sgmii_cg_regs =3D { .sta_ofs =3D 0xE4, }; =20 -#define GATE_SGMII(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &sgmii_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate sgmii_clks[2][4] =3D { { diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index c3eb09ea6036..78d85542e4f1 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -16,23 +16,11 @@ =20 #include =20 -#define GATE_PCIE(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &pcie_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } - -#define GATE_SSUSB(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ssusb_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PCIE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_SSUSB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate_regs pcie_cg_regs =3D { .set_ofs =3D 0x30, diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index cf062d4a7ecc..09c85fda43d8 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -50,41 +50,17 @@ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ NULL, "clk20m") =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &apmixed_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr_inv) =20 -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static DEFINE_SPINLOCK(mt7629_clk_lock); =20 diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/c= lk-mt7986-eth.c index 703872239ecc..e04bc6845ea6 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -22,12 +22,8 @@ static const struct mtk_gate_regs sgmii0_cg_regs =3D { .sta_ofs =3D 0xe4, }; =20 -#define GATE_SGMII0(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &sgmii0_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 static const struct mtk_gate sgmii0_clks[] __initconst =3D { GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), @@ -42,12 +38,8 @@ static const struct mtk_gate_regs sgmii1_cg_regs =3D { .sta_ofs =3D 0xe4, }; =20 -#define GATE_SGMII1(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &sgmii1_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 static const struct mtk_gate sgmii1_clks[] __initconst =3D { GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), @@ -62,12 +54,8 @@ static const struct mtk_gate_regs eth_cg_regs =3D { .sta_ofs =3D 0x30, }; =20 -#define GATE_ETH(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate eth_clks[] __initconst =3D { GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/media= tek/clk-mt7986-infracfg.c index e80c92167c8f..0a4bf87ee160 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -87,26 +87,14 @@ static const struct mtk_gate_regs infra2_cg_regs =3D { .sta_ofs =3D 0x68, }; =20 -#define GATE_INFRA0(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &infra0_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_INFRA1(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &infra1_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_INFRA2(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &infra2_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 static const struct mtk_gate infra_clks[] =3D { /* INFRA0 */ diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 2b9c925c2a2b..97a115d2c3da 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -401,14 +401,8 @@ static const struct mtk_gate_regs infra_cg_regs =3D { .sta_ofs =3D 0x0048, }; =20 -#define GATE_ICG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_ICG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate infra_clks[] __initconst =3D { GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), @@ -438,23 +432,11 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { .sta_ofs =3D 0x001c, }; =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate peri_gates[] __initconst =3D { /* PERI0 */ diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index eec9de190cb6..8869c53da79c 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -23,14 +23,9 @@ static const struct mtk_gate_regs aud_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_AUD(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &aud_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) + =20 static const struct mtk_gate aud_clks[] =3D { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index 5cd51d894d32..6a068f2a9dce 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -23,14 +23,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0), diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 2cf88d5d245d..7fcb944134b6 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -23,14 +23,8 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_MFG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mfg_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/cl= k-mt8167-mm.c index 78c023b0565a..5a5192d0dc45 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -29,23 +29,11 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { .sta_ofs =3D 0x110, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mm_clks[] =3D { /* MM0 */ diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index c3e2253a57d7..b3eccc2eca58 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -29,23 +29,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x8, }; =20 -#define GATE_VDEC0_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { /* VDEC0 */ diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/cl= k-mt8173-mm.c index ffec2d917661..435cfae25492 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -25,23 +25,11 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mt8173_mm_clks[] =3D { GATE_DUMMY(CLK_DUMMY, "mm_dummy"), diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/c= lk-mt8516-aud.c index 00f356fe7c7a..a6ae8003b9ff 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -22,14 +22,8 @@ static const struct mtk_gate_regs aud_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_AUD(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &aud_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) =20 static const struct mtk_gate aud_clks[] __initconst =3D { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index 2c0cae7b3bcf..6983d3a48dc9 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -525,59 +525,23 @@ static const struct mtk_gate_regs top5_cg_regs =3D { .sta_ofs =3D 0x44, }; =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP2_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP4_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top4_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP4_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP5(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top5_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 static const struct mtk_gate top_clks[] __initconst =3D { /* TOP1 */ --=20 2.39.1