From nobody Thu Nov 14 06:36:02 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D55CC61DA3 for ; Tue, 21 Feb 2023 11:58:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234543AbjBUL5e (ORCPT ); Tue, 21 Feb 2023 06:57:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234489AbjBUL5E (ORCPT ); Tue, 21 Feb 2023 06:57:04 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2105F27D55; Tue, 21 Feb 2023 03:56:40 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3FDF666021D5; Tue, 21 Feb 2023 11:56:18 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676980579; bh=EfVsMWfXlW7Nej60ln7osuE3Ve3dZUUh6F8ZrFmhc+I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RDJ4CQo/XMaMxcQaMfNZqHd/IX+qUxtzk83G0VR2Fe2KRwF08qgCR8m9XZZzN7qRw Xtp47tWSImBqsbLyePXLerPsxm7gYnPh6rP/Bka0OJFBmL5AKBaLrqLRGaT3j0QTLw Dt+TE20EbKdg2S3Fc8ClMfU5AwtEOlFU++eInhOjr3l6iOjWDU5C/8wuiZkXBOD5+M arLaA/R4V5TnMgbuV9VM+igqq+I9TOlzbQjW91DbHYgAiSb3rrkeUaClpOMUieHPHS Z6h9g2k6uVHp9Wir3BKLedtLg3ahgyfC5hIFWxU8iVov8bDfYHNY04631it7Ivhpnr ww0m9FgpMLhUg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 18/54] clk: mediatek: mt8167: Convert to mtk_clk_simple_{probe,remove}() Date: Tue, 21 Feb 2023 12:55:13 +0100 Message-Id: <20230221115549.360132-19-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> References: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert topckgen and infracfg clock drivers to use the common mtk_clk_simple_probe() mechanism and change this from the old "static" CLK_OF_DECLARE to be a platform driver, allowing it to eventually be built as a module. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8167-aud.c | 31 +++++---- drivers/clk/mediatek/clk-mt8167-img.c | 32 ++++----- drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 32 ++++----- drivers/clk/mediatek/clk-mt8167-vdec.c | 33 ++++----- drivers/clk/mediatek/clk-mt8167.c | 86 +++++++++--------------- 5 files changed, 101 insertions(+), 113 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index 2d890a440863..eec9de190cb6 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -48,19 +48,22 @@ static const struct mtk_gate aud_clks[] =3D { GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), }; =20 -static void __init mtk_audsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR_CLK); - - mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_da= ta); +static const struct mtk_clk_desc aud_desc =3D { + .clks =3D aud_clks, + .num_clks =3D ARRAY_SIZE(aud_clks), +}; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_audsys[] =3D { + { .compatible =3D "mediatek,mt8167-audsys", .data =3D &aud_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init); +static struct platform_driver clk_mt8167_audsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-audsys", + .of_match_table =3D of_match_clk_mt8167_audsys, + }, +}; +module_platform_driver(clk_mt8167_audsys_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index 23950186ee02..5cd51d894d32 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -41,20 +41,22 @@ static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9), }; =20 -static void __init mtk_imgsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_IMG_NR_CLK); - - mtk_clk_register_gates(NULL, node, img_clks, ARRAY_SIZE(img_clks), clk_da= ta); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc img_desc =3D { + .clks =3D img_clks, + .num_clks =3D ARRAY_SIZE(img_clks), +}; =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_imgsys[] =3D { + { .compatible =3D "mediatek,mt8167-imgsys", .data =3D &img_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8167-imgsys", mtk_imgsys_init); +static struct platform_driver clk_mt8167_imgsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-imgsys", + .of_match_table =3D of_match_clk_mt8167_imgsys, + }, +}; +module_platform_driver(clk_mt8167_imgsys_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 40b2d45f3fe3..2cf88d5d245d 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -39,20 +39,22 @@ static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3), }; =20 -static void __init mtk_mfgcfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_MFG_NR_CLK); - - mtk_clk_register_gates(NULL, node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_da= ta); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc mfg_desc =3D { + .clks =3D mfg_clks, + .num_clks =3D ARRAY_SIZE(mfg_clks), +}; =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_mfgcfg[] =3D { + { .compatible =3D "mediatek,mt8167-mfgcfg", .data =3D &mfg_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init); +static struct platform_driver clk_mt8167_mfgcfg_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-mfgcfg", + .of_match_table =3D of_match_clk_mt8167_mfgcfg, + }, +}; +module_platform_driver(clk_mt8167_mfgcfg_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index 905529789a7c..c3e2253a57d7 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -54,21 +54,22 @@ static const struct mtk_gate vdec_clks[] =3D { GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0), }; =20 -static void __init mtk_vdecsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_VDEC_NR_CLK); - - mtk_clk_register_gates(NULL, node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc vdec_desc =3D { + .clks =3D vdec_clks, + .num_clks =3D ARRAY_SIZE(vdec_clks), +}; =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_vdec[] =3D { + { .compatible =3D "mediatek,mt8167-vdecsys", .data =3D &vdec_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init); +static struct platform_driver clk_mt8167_vdec_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-vdecsys", + .of_match_table =3D of_match_clk_mt8167_vdec, + }, +}; +module_platform_driver(clk_mt8167_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index f604add9b546..507e1ebe3ba8 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "clk-gate.h" #include "clk-mtk.h" @@ -857,59 +858,38 @@ static const struct mtk_gate top_clks[] =3D { GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), }; =20 -static void __init mtk_topckgen_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data =3D mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK); +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .fixed_clks =3D fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt8167_clk_lock, +}; =20 - mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), - clk_data); - mtk_clk_register_gates(NULL, node, top_clks, ARRAY_SIZE(top_clks), clk_da= ta); +static const struct mtk_clk_desc infra_desc =3D { + .composite_clks =3D ifr_muxes, + .num_composite_clks =3D ARRAY_SIZE(ifr_muxes), + .clk_lock =3D &mt8167_clk_lock, +}; =20 - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(NULL, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8167_clk_lock, clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt8167_clk_lock, clk_data); +static const struct of_device_id of_match_clk_mt8167[] =3D { + { .compatible =3D "mediatek,mt8167-topckgen", .data =3D &topck_desc }, + { .compatible =3D "mediatek,mt8167-infracfg", .data =3D &infra_desc }, + { /* sentinel */ } +}; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init= ); - -static void __init mtk_infracfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data =3D mtk_alloc_clk_data(CLK_IFR_NR_CLK); - - mtk_clk_register_composites(NULL, ifr_muxes, - ARRAY_SIZE(ifr_muxes), base, - &mt8167_clk_lock, clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init= ); +static struct platform_driver clk_mt8167_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167", + .of_match_table =3D of_match_clk_mt8167, + }, +}; +module_platform_driver(clk_mt8167_drv); --=20 2.39.1