From nobody Thu Nov 14 06:39:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C767AC6379F for ; Tue, 21 Feb 2023 11:57:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234524AbjBUL51 (ORCPT ); Tue, 21 Feb 2023 06:57:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234484AbjBUL5B (ORCPT ); Tue, 21 Feb 2023 06:57:01 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9CF828852; Tue, 21 Feb 2023 03:56:37 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 51F4166021D2; Tue, 21 Feb 2023 11:56:14 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676980575; bh=WzEqGHU4wPUr1FqrefeofMY/SCcyC9H6YipRxwjIHNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DegaVBEQyk49BEy3VpgwuIWepzXKzKsafiPeAuu99c5J5iPf7bn5ypCJMUadgPVa3 SmaXbuVkRYPvVd14LO4qkUkOLiZx8g3d/56W8owjayf70IleoXTBGFaaEOv2SdNrGP Bf6B880XzbdcFJUe+accY2An83h7piplNOIxe01EP8m8+JCSljtmMuAsUeQCfrt7Wp cj57RxAHiDNvKvXTLMBwrlAvUdUf6BLgtZz3u2mSPMfeht0YFgl6iZCzc9V85RwnTx bTcZchLrIZuP3BmxLhSMHpJMguozhkHJ+OWk6t1qT18/6Z99YM2u2FKzssOyAUQHfT kS2xPDmT0Bj6g== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 15/54] clk: mediatek: mt8167: Compress GATE_TOPx macros Date: Tue, 21 Feb 2023 12:55:10 +0100 Message-Id: <20230221115549.360132-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> References: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros. No functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8167.c | 80 +++++++------------------------ 1 file changed, 16 insertions(+), 64 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index 91669ebafaf9..12384da4002d 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -736,77 +736,29 @@ static const struct mtk_gate_regs top5_cg_regs =3D { .sta_ofs =3D 0x44, }; =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP0_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP0_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP2_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP4_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top4_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP4_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP5(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top5_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 static const struct mtk_gate top_clks[] __initconst =3D { /* TOP0 */ --=20 2.39.1