From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F3A1C64EC7 for ; Mon, 20 Feb 2023 15:01:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232282AbjBTPBd (ORCPT ); Mon, 20 Feb 2023 10:01:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232200AbjBTPBZ (ORCPT ); Mon, 20 Feb 2023 10:01:25 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38E4F1D90A; Mon, 20 Feb 2023 07:01:19 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6F54F6602166; Mon, 20 Feb 2023 15:01:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905277; bh=l5BdwmfyxbZlaujYTSJF7PTIlSpQy1drDejxx2IavtU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q9k3WpRwohnh0ddpZBv2F8RzE2vZ8ybMmqPZ3Ol+zbDQ8DevqOR15+5wuoRGu/L/X hOowa9m7SNzaY51EuCVlT17vgVyhGWbWGEogWs076oXe6Fp21dWj576jUOFVaMM1ed Q+Xtl27e0I5oWtH+ZWCh3up7LxbSqAYsYP2Py3Vdho7H+U8/i4U12Xel5vfX90Vx3f V7z4B1Et8q3j86dr5yXgY/udJTrGa8IxpG7LWaLjbpoxpKa8GnNzvGvcPhSVHHy9YN Y6nkeZvlH0yQxC/e0dzYE+QibiSHiWAUaMteXYqnTUrU+MtAGyPuavQk3xIhYmDEci 3f7vka0niC4xg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 01/55] clk: mediatek: clk-mtk: Switch to device_get_match_data() Date: Mon, 20 Feb 2023 16:00:17 +0100 Message-Id: <20230220150111.77897-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of using of_device_get_match_data(), switch to the generic device_get_match_data(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mtk.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index c90c0a6b501b..71eb591cd00c 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include =20 @@ -471,7 +470,7 @@ int mtk_clk_simple_probe(struct platform_device *pdev) void __iomem *base; int num_clks, r; =20 - mcd =3D of_device_get_match_data(&pdev->dev); + mcd =3D device_get_match_data(&pdev->dev); if (!mcd) return -EINVAL; =20 @@ -586,7 +585,7 @@ EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); =20 int mtk_clk_simple_remove(struct platform_device *pdev) { - const struct mtk_clk_desc *mcd =3D of_device_get_match_data(&pdev->dev); + const struct mtk_clk_desc *mcd =3D device_get_match_data(&pdev->dev); struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); struct device_node *node =3D pdev->dev.of_node; =20 --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 861E6C636CC for ; Mon, 20 Feb 2023 15:01:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232291AbjBTPBk (ORCPT ); Mon, 20 Feb 2023 10:01:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232257AbjBTPB1 (ORCPT ); Mon, 20 Feb 2023 10:01:27 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82D8F1DBBA; Mon, 20 Feb 2023 07:01:20 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D24F36602168; Mon, 20 Feb 2023 15:01:17 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905279; bh=iO2EFs+uVUr3LJJKJ1mXQIFQpij+PavyEEfSYdwBwPs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d9mVk9to/vBTsg168Vu8lh5qODN0aJ/6bDATohmPNx3tVcTwVohtWvTkDKUQ5FD2g 7RBWzwHqfOCy6Z/L1PF/3Zdbe1JfC6JNV2LG51N7C89mPsUKU3yYZId42HrRcR9eaY TmDXNYH6Qn8hYh31yBtCRUcKIIxYpRoXj+2mhZf1toUqPtVwYlLEjZd8xB+hNsOO3y 7UBo9VwvIq29IFLgqDmm7Z/tZLTqDubJJMg0iAjIo44dO1gP7QeWuphaKMpudVXprf DwLdbw0rQ7oSlqBfdAkb5rDjgQ53YhuUkFN5he+7nxa6FvtxWEDBnBWeAXG7AVqdFt zYMzO/wvtwfIw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 02/55] clk: mediatek: clk-mtk: Introduce clk_mtk_pdev_{probe,remove}() Date: Mon, 20 Feb 2023 16:00:18 +0100 Message-Id: <20230220150111.77897-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce functions clk_mtk_pdev_probe() and clk_mtk_pdev_remove(): these will be useful to commonize the probe and remove handlers for multimedia (clk-mtxxxx-mm) drivers as these are registered by the mtk-mmsys driver instead of having their own devicetree compatible. In order to do this, the main logic of clk_mtk_simple{probe,remove}() was moved to new static __clk_mtk_simple_{probe,remove}() functions that take as parameter a pointer to struct device_node because when registering the clocks from mtk-mmsys we want to pass a pointer to the clock driver's parent (which is, obviously, mtk-mmsys) struct device_node instead. As for the clock driver's platform data: for the devicetree case, we keep using the standard match_data mechanism, else we retrieve it from an id_table. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mtk.c | 54 +++++++++++++++++++++++++++++----- drivers/clk/mediatek/clk-mtk.h | 2 ++ 2 files changed, 48 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 71eb591cd00c..a69d3f0a38c7 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -462,17 +462,25 @@ void mtk_clk_unregister_dividers(const struct mtk_clk= _divider *mcds, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_dividers); =20 -int mtk_clk_simple_probe(struct platform_device *pdev) +static int __mtk_clk_simple_probe(struct platform_device *pdev, + struct device_node *node) { + const struct platform_device_id *id; const struct mtk_clk_desc *mcd; struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; void __iomem *base; int num_clks, r; =20 mcd =3D device_get_match_data(&pdev->dev); - if (!mcd) - return -EINVAL; + if (!mcd) { + /* Clock driver wasn't registered from devicetree */ + id =3D platform_get_device_id(pdev); + if (id) + mcd =3D (const struct mtk_clk_desc *)id->driver_data; + + if (!mcd) + return -EINVAL; + } =20 /* Composite clocks needs us to pass iomem pointer */ if (mcd->composite_clks) { @@ -581,13 +589,12 @@ int mtk_clk_simple_probe(struct platform_device *pdev) iounmap(base); return r; } -EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); =20 -int mtk_clk_simple_remove(struct platform_device *pdev) +static int __mtk_clk_simple_remove(struct platform_device *pdev, + struct device_node *node) { - const struct mtk_clk_desc *mcd =3D device_get_match_data(&pdev->dev); struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - struct device_node *node =3D pdev->dev.of_node; + const struct mtk_clk_desc *mcd =3D device_get_match_data(&pdev->dev); =20 of_clk_del_provider(node); if (mcd->clks) @@ -608,6 +615,37 @@ int mtk_clk_simple_remove(struct platform_device *pdev) =20 return 0; } + +int mtk_clk_pdev_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + + return __mtk_clk_simple_probe(pdev, node); +} +EXPORT_SYMBOL_GPL(mtk_clk_pdev_probe); + +int mtk_clk_simple_probe(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + + return __mtk_clk_simple_probe(pdev, node); +} +EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); + +int mtk_clk_pdev_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + + return __mtk_clk_simple_remove(pdev, node); +} +EXPORT_SYMBOL_GPL(mtk_clk_pdev_remove); + +int mtk_clk_simple_remove(struct platform_device *pdev) +{ + return __mtk_clk_simple_remove(pdev, pdev->dev.of_node); +} EXPORT_SYMBOL_GPL(mtk_clk_simple_remove); =20 MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 41f4fa3b0c21..b8e0ff8f52fa 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -236,6 +236,8 @@ struct mtk_clk_desc { unsigned int mfg_clk_idx; }; =20 +int mtk_clk_pdev_probe(struct platform_device *pdev); +int mtk_clk_pdev_remove(struct platform_device *pdev); int mtk_clk_simple_probe(struct platform_device *pdev); int mtk_clk_simple_remove(struct platform_device *pdev); =20 --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42599C636CC for ; Mon, 20 Feb 2023 15:01:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230121AbjBTPBv (ORCPT ); Mon, 20 Feb 2023 10:01:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbjBTPB3 (ORCPT ); Mon, 20 Feb 2023 10:01:29 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3D061DBB4; Mon, 20 Feb 2023 07:01:21 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 40E096602169; Mon, 20 Feb 2023 15:01:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905280; bh=P3W6+B36W4E9DtgYTRH6j92qmH82MuwCqGFuyNJSHpI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LeGwRXeUaUfj8PlHauxgLOWkJcRXn3Yc2LATyyYoNS72wQyz/+QRzzvGm7wfKL/s9 FqLxMoIpIKRJSNP4f50Fi6qihDvilUIxO9slTgjwAkdcu75lNj2OTHbJ8gzHRg2Bko Ri0acn56nZ+Naw5En7ry4tfQQmdoQb2aNqhHWVPFkbUg2paaIUin+8DZbZpzgfvBCN fgcQEhgY727SEDOeE4DISCMu5r/6vbx6b+06EYIWRySLSARdP6rkfybcEtUy2whso5 qfjHdhrOreUtNkbVVILs7KCGg02Nr9E2C1PV59v7uuZ8U8aespO08SOkR2i9h3hbj3 ODfLcISxZ+0ww== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 03/55] clk: mediatek: Migrate to mtk_clk_pdev_probe() for multimedia clocks Date: Mon, 20 Feb 2023 16:00:19 +0100 Message-Id: <20230220150111.77897-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Reduce duplication and simplify all MediaTek multimedia clock drivers by migrating away from defining custom probe functions for each driver and instead use mtk_clk_pdev_probe(). While at it, also add a .remove() callback to all of the multimedia clock drivers where missing. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2701-mm.c | 31 +++++--------- drivers/clk/mediatek/clk-mt2712-mm.c | 31 +++++--------- drivers/clk/mediatek/clk-mt6779-mm.c | 24 +++++------ drivers/clk/mediatek/clk-mt6795-mm.c | 55 +++++------------------- drivers/clk/mediatek/clk-mt6797-mm.c | 31 +++++--------- drivers/clk/mediatek/clk-mt8167-mm.c | 47 +++++---------------- drivers/clk/mediatek/clk-mt8173-mm.c | 58 +++++--------------------- drivers/clk/mediatek/clk-mt8183-mm.c | 24 +++++------ drivers/clk/mediatek/clk-mt8186-mm.c | 56 +++++-------------------- drivers/clk/mediatek/clk-mt8192-mm.c | 29 +++++-------- drivers/clk/mediatek/clk-mt8195-vdo0.c | 55 +++++------------------- drivers/clk/mediatek/clk-mt8195-vdo1.c | 57 ++++++------------------- drivers/clk/mediatek/clk-mt8195-vpp0.c | 54 +++++------------------- drivers/clk/mediatek/clk-mt8195-vpp1.c | 54 +++++------------------- drivers/clk/mediatek/clk-mt8365-mm.c | 39 +++++------------ 15 files changed, 165 insertions(+), 480 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/cl= k-mt2701-mm.c index 23d5ddcc1d37..a8d94ca0eefd 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -79,32 +79,23 @@ static const struct mtk_gate mm_clks[] =3D { GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14), }; =20 -static int clk_mt2701_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 - return r; -} +static const struct platform_device_id clk_mt2701_mm_id_table[] =3D { + { .name =3D "clk-mt2701-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt2701_mm_drv =3D { - .probe =3D clk_mt2701_mm_probe, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt2701-mm", }, + .id_table =3D clk_mt2701_mm_id_table, }; =20 builtin_platform_driver(clk_mt2701_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/cl= k-mt2712-mm.c index 25b8af640c12..615f6b0fe96e 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -126,32 +126,23 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6), }; =20 -static int clk_mt2712_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 - return r; -} +static const struct platform_device_id clk_mt2712_mm_id_table[] =3D { + { .name =3D "clk-mt2712-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt2712_mm_drv =3D { - .probe =3D clk_mt2712_mm_probe, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt2712-mm", }, + .id_table =3D clk_mt2712_mm_id_table, }; =20 builtin_platform_driver(clk_mt2712_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/cl= k-mt6779-mm.c index 2cccf62d3b36..219a3a7920cd 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -85,25 +85,23 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16), }; =20 -static int clk_mt6779_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct platform_device_id clk_mt6779_mm_id_table[] =3D { + { .name =3D "clk-mt6779-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt6779_mm_drv =3D { - .probe =3D clk_mt6779_mm_probe, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt6779-mm", }, + .id_table =3D clk_mt6779_mm_id_table, }; =20 module_platform_driver(clk_mt6779_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt6795-mm.c b/drivers/clk/mediatek/cl= k-mt6795-mm.c index eebb6143ada2..c0c61a08cd72 100644 --- a/drivers/clk/mediatek/clk-mt6795-mm.c +++ b/drivers/clk/mediatek/clk-mt6795-mm.c @@ -76,56 +76,23 @@ static const struct mtk_gate mm_gates[] =3D { GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9), }; =20 -static int clk_mt6795_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, mm_gates, - ARRAY_SIZE(mm_gates), clk_data); - if (ret) - goto free_clk_data; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(mm_gates, ARRAY_SIZE(mm_gates), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return ret; -} - -static int clk_mt6795_mm_remove(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(mm_gates, ARRAY_SIZE(mm_gates), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_gates, + .num_clks =3D ARRAY_SIZE(mm_gates), +}; =20 - return 0; -} +static const struct platform_device_id clk_mt6795_mm_id_table[] =3D { + { .name =3D "clk-mt6795-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt6795_mm_drv =3D { .driver =3D { .name =3D "clk-mt6795-mm", }, - .probe =3D clk_mt6795_mm_probe, - .remove =3D clk_mt6795_mm_remove, + .id_table =3D clk_mt6795_mm_id_table, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, }; module_platform_driver(clk_mt6795_mm_drv); =20 diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index deb16a6b16a5..706c9775646d 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -92,32 +92,23 @@ static const struct mtk_gate mm_clks[] =3D { "clk26m", 3), }; =20 -static int clk_mt6797_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 - return r; -} +static const struct platform_device_id clk_mt6797_mm_id_table[] =3D { + { .name =3D "clk-mt6797-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt6797_mm_drv =3D { - .probe =3D clk_mt6797_mm_probe, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt6797-mm", }, + .id_table =3D clk_mt6797_mm_id_table, }; =20 builtin_platform_driver(clk_mt6797_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/cl= k-mt8167-mm.c index c0b44104c765..78c023b0565a 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -86,47 +86,22 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21), }; =20 -struct clk_mt8167_mm_driver_data { - const struct mtk_gate *gates_clk; - int gates_num; +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), }; =20 -static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data =3D= { - .gates_clk =3D mm_clks, - .gates_num =3D ARRAY_SIZE(mm_clks), +static const struct platform_device_id clk_mt8167_mm_id_table[] =3D { + { .name =3D "clk-mt8167-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } }; =20 -static int clk_mt8167_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - const struct clk_mt8167_mm_driver_data *data; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - data =3D &mt8167_mmsys_driver_data; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, data->gates_clk, - data->gates_num, clk_data); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - return ret; - - return 0; -} - -static struct platform_driver clk_mt8173_mm_drv =3D { +static struct platform_driver clk_mt8167_mm_drv =3D { + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8167-mm", }, - .probe =3D clk_mt8167_mm_probe, + .id_table =3D clk_mt8167_mm_id_table, }; - -builtin_platform_driver(clk_mt8173_mm_drv); +builtin_platform_driver(clk_mt8167_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/cl= k-mt8173-mm.c index 315430ad1581..ffec2d917661 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -44,6 +44,7 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { } =20 static const struct mtk_gate mt8173_mm_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "mm_dummy"), /* MM0 */ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), @@ -100,62 +101,23 @@ static const struct mtk_gate mt8173_mm_clks[] =3D { GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20), }; =20 -struct clk_mt8173_mm_driver_data { - const struct mtk_gate *gates_clk; - int gates_num; +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mt8173_mm_clks, + .num_clks =3D ARRAY_SIZE(mt8173_mm_clks), }; =20 -static const struct clk_mt8173_mm_driver_data mt8173_mmsys_driver_data =3D= { - .gates_clk =3D mt8173_mm_clks, - .gates_num =3D ARRAY_SIZE(mt8173_mm_clks), +static const struct platform_device_id clk_mt8173_mm_id_table[] =3D { + { .name =3D "clk-mt8173-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } }; =20 -static int clk_mt8173_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - const struct clk_mt8173_mm_driver_data *data; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - data =3D &mt8173_mmsys_driver_data; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, data->gates_clk, - data->gates_num, clk_data); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - return ret; - - return 0; -} - -static int clk_mt8173_mm_remove(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - const struct clk_mt8173_mm_driver_data *data =3D &mt8173_mmsys_driver_dat= a; - - of_clk_del_provider(node); - mtk_clk_unregister_gates(data->gates_clk, data->gates_num, clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} - static struct platform_driver clk_mt8173_mm_drv =3D { .driver =3D { .name =3D "clk-mt8173-mm", }, - .probe =3D clk_mt8173_mm_probe, - .remove =3D clk_mt8173_mm_remove, + .id_table =3D clk_mt8173_mm_id_table, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, }; =20 builtin_platform_driver(clk_mt8173_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/cl= k-mt8183-mm.c index 358031530913..669dcdd66efb 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -82,25 +82,23 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13), }; =20 -static int clk_mt8183_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct platform_device_id clk_mt8183_mm_id_table[] =3D { + { .name =3D "clk-mt8183-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8183_mm_drv =3D { - .probe =3D clk_mt8183_mm_probe, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8183-mm", }, + .id_table =3D clk_mt8183_mm_id_table, }; =20 builtin_platform_driver(clk_mt8183_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/cl= k-mt8186-mm.c index 0b72607777fa..6506a8b848a9 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -58,55 +58,21 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM1(CLK_MM_DISP_26M, "mm_disp_26m_ck", "top_disp", 10), }; =20 -static int clk_mt8186_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - if (r) - goto free_mm_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data); -free_mm_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8186_mm_remove(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 +static const struct platform_device_id clk_mt8186_mm_id_table[] =3D { + { .name =3D "clk-mt8186-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; static struct platform_driver clk_mt8186_mm_drv =3D { - .probe =3D clk_mt8186_mm_probe, - .remove =3D clk_mt8186_mm_remove, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8186-mm", }, + .id_table =3D clk_mt8186_mm_id_table, }; builtin_platform_driver(clk_mt8186_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/cl= k-mt8192-mm.c index e9eb4cf8349a..638e6faae84c 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -80,30 +80,23 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25), }; =20 -static int clk_mt8192_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - if (r) - return r; +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct platform_device_id clk_mt8192_mm_id_table[] =3D { + { .name =3D "clk-mt8192-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8192_mm_drv =3D { - .probe =3D clk_mt8192_mm_probe, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8192-mm", }, + .id_table =3D clk_mt8192_mm_id_table, }; =20 builtin_platform_driver(clk_mt8192_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/= clk-mt8195-vdo0.c index 839b730688ac..492c1e133d0d 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -93,55 +93,22 @@ static const struct mtk_gate vdo0_clks[] =3D { "top_edp", 16, CLK_SET_RATE_PARENT), }; =20 -static int clk_mt8195_vdo0_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_VDO0_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(&pdev->dev, node, vdo0_clks, - ARRAY_SIZE(vdo0_clks), clk_data); - if (r) - goto free_vdo0_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); -free_vdo0_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vdo0_remove(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc vdo0_desc =3D { + .clks =3D vdo0_clks, + .num_clks =3D ARRAY_SIZE(vdo0_clks), +}; =20 - return 0; -} +static const struct platform_device_id clk_mt8195_vdo0_id_table[] =3D { + { .name =3D "clk-mt8195-vdo0", .driver_data =3D (kernel_ulong_t)&vdo0_des= c }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8195_vdo0_drv =3D { - .probe =3D clk_mt8195_vdo0_probe, - .remove =3D clk_mt8195_vdo0_remove, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8195-vdo0", }, + .id_table =3D clk_mt8195_vdo0_id_table, }; builtin_platform_driver(clk_mt8195_vdo0_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/= clk-mt8195-vdo1.c index 7df695b28925..76e9f4496e43 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -120,55 +120,22 @@ static const struct mtk_gate vdo1_clks[] =3D { GATE_VDO1_4(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0), }; =20 -static int clk_mt8195_vdo1_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_VDO1_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(&pdev->dev, node, vdo1_clks, - ARRAY_SIZE(vdo1_clks), clk_data); - if (r) - goto free_vdo1_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data); -free_vdo1_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vdo1_remove(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} +static const struct mtk_clk_desc vdo1_desc =3D { + .clks =3D vdo1_clks, + .num_clks =3D ARRAY_SIZE(vdo1_clks), +}; + +static const struct platform_device_id clk_mt8195_vdo1_id_table[] =3D { + { .name =3D "clk-mt8195-vdo1", .driver_data =3D (kernel_ulong_t)&vdo1_des= c }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8195_vdo1_drv =3D { - .probe =3D clk_mt8195_vdo1_probe, - .remove =3D clk_mt8195_vdo1_remove, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8195-vdo1", }, + .id_table =3D clk_mt8195_vdo1_id_table, }; builtin_platform_driver(clk_mt8195_vdo1_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/= clk-mt8195-vpp0.c index debff9a8c071..15f1a081358a 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -86,54 +86,22 @@ static const struct mtk_gate vpp0_clks[] =3D { GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_= wpe_vpp", 3), }; =20 -static int clk_mt8195_vpp0_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_VPP0_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(&pdev->dev, node, vpp0_clks, ARRAY_SIZE(vpp0= _clks), clk_data); - if (r) - goto free_vpp0_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); -free_vpp0_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vpp0_remove(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc vpp0_desc =3D { + .clks =3D vpp0_clks, + .num_clks =3D ARRAY_SIZE(vpp0_clks), +}; =20 - return 0; -} +static const struct platform_device_id clk_mt8195_vpp0_id_table[] =3D { + { .name =3D "clk-mt8195-vpp0", .driver_data =3D (kernel_ulong_t)&vpp0_des= c }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8195_vpp0_drv =3D { - .probe =3D clk_mt8195_vpp0_probe, - .remove =3D clk_mt8195_vpp0_remove, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8195-vpp0", }, + .id_table =3D clk_mt8195_vpp0_id_table, }; builtin_platform_driver(clk_mt8195_vpp0_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/= clk-mt8195-vpp1.c index beacbd94ef02..794f21cf5e65 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -84,54 +84,22 @@ static const struct mtk_gate vpp1_clks[] =3D { GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26), }; =20 -static int clk_mt8195_vpp1_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_VPP1_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(&pdev->dev, node, vpp1_clks, ARRAY_SIZE(vpp1= _clks), clk_data); - if (r) - goto free_vpp1_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); -free_vpp1_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vpp1_remove(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc vpp1_desc =3D { + .clks =3D vpp1_clks, + .num_clks =3D ARRAY_SIZE(vpp1_clks), +}; =20 - return 0; -} +static const struct platform_device_id clk_mt8195_vpp1_id_table[] =3D { + { .name =3D "clk-mt8195-vpp1", .driver_data =3D (kernel_ulong_t)&vpp1_des= c }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8195_vpp1_drv =3D { - .probe =3D clk_mt8195_vpp1_probe, - .remove =3D clk_mt8195_vpp1_remove, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8195-vpp1", }, + .id_table =3D clk_mt8195_vpp1_id_table, }; builtin_platform_driver(clk_mt8195_vpp1_drv); diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/cl= k-mt8365-mm.c index 22c75a03a645..9569be54127c 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -72,40 +72,23 @@ static const struct mtk_gate mm_clks[] =3D { GATE_MM1(CLK_MM_LVDSTX_CTS, "mm_flvdstx_cts", "lvdstx_dig_cts", 3), }; =20 -static int clk_mt8365_mm_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); - - ret =3D mtk_clk_register_gates(dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - if (ret) - goto err_free_clk_data; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto err_unregister_gates; - - return 0; - -err_unregister_gates: - mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data); - -err_free_clk_data: - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc mm_desc =3D { + .clks =3D mm_clks, + .num_clks =3D ARRAY_SIZE(mm_clks), +}; =20 - return ret; -} +static const struct platform_device_id clk_mt8365_mm_id_table[] =3D { + { .name =3D "clk-mt8365-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8365_mm_drv =3D { - .probe =3D clk_mt8365_mm_probe, + .probe =3D mtk_clk_pdev_probe, + .remove =3D mtk_clk_pdev_remove, .driver =3D { .name =3D "clk-mt8365-mm", }, + .id_table =3D clk_mt8365_mm_id_table, }; builtin_platform_driver(clk_mt8365_mm_drv); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDBABC64EC4 for ; Mon, 20 Feb 2023 15:01:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231815AbjBTPBs (ORCPT ); Mon, 20 Feb 2023 10:01:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232271AbjBTPB2 (ORCPT ); Mon, 20 Feb 2023 10:01:28 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2123D1DB9F; Mon, 20 Feb 2023 07:01:23 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A6628660216A; Mon, 20 Feb 2023 15:01:20 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905281; bh=OUjfvjH+xela87xq+mZBbq7prhZGbEBP6ki4p+S2LtM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P6aw+B3/fUi/jCcCD66fPPzxu3BDYMORkI9dk4mFLYheFXVX9JJ2yT0PP2tYBIz2g hpmbH+IhN0860H2CIXlLxjtFFPScYnP8ZxqftOJjD7bcz6hI+3mJ9FLwA3HUCNdjzz om4ZA8ggQXNqG5kcM93La4JPdrBiD1hTSWw43tEtIE18PLDTu0Pc5wTLjaWwZ/Neir bMUDK2KWTJk97vEUpZ5aZzkV3hUFhQ8SG8FrtDSugXALEDSSRN2sUC0ldxzr+dYGSY Dq6hmoouUM/wDf4re6URRXDunN0R7MTI2ZbXP56SqyrWpBL55NhDHkX2qshOM0u7uJ cyR/IuEKmLbgQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 04/55] clk: mediatek: Add divider clocks to mtk_clk_simple_{probe,remove}() Date: Mon, 20 Feb 2023 16:00:20 +0100 Message-Id: <20230220150111.77897-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for divider clocks register/unregister in the common mtk_clk_simple_probe() and mtk_clk_simple_remove() functions. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mtk.c | 19 +++++++++++++++++-- drivers/clk/mediatek/clk-mtk.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index a69d3f0a38c7..39bd360aa0c9 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -496,7 +496,7 @@ static int __mtk_clk_simple_probe(struct platform_devic= e *pdev, /* Calculate how many clk_hw_onecell_data entries to allocate */ num_clks =3D mcd->num_clks + mcd->num_composite_clks; num_clks +=3D mcd->num_fixed_clks + mcd->num_factor_clks; - num_clks +=3D mcd->num_mux_clks; + num_clks +=3D mcd->num_mux_clks + mcd->num_divider_clks; =20 clk_data =3D mtk_alloc_clk_data(num_clks); if (!clk_data) @@ -534,11 +534,19 @@ static int __mtk_clk_simple_probe(struct platform_dev= ice *pdev, goto unregister_muxes; } =20 + if (mcd->divider_clks) { + r =3D mtk_clk_register_dividers(mcd->divider_clks, + mcd->num_divider_clks, + base, mcd->clk_lock, clk_data); + if (r) + goto unregister_composites; + } + if (mcd->clks) { r =3D mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, clk_data); if (r) - goto unregister_composites; + goto unregister_dividers; } =20 if (mcd->clk_notifier_func) { @@ -567,6 +575,10 @@ static int __mtk_clk_simple_probe(struct platform_devi= ce *pdev, unregister_clks: if (mcd->clks) mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); +unregister_dividers: + if (mcd->divider_clks) + mtk_clk_unregister_dividers(mcd->divider_clks, + mcd->num_divider_clks, clk_data); unregister_composites: if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, @@ -599,6 +611,9 @@ static int __mtk_clk_simple_remove(struct platform_devi= ce *pdev, of_clk_del_provider(node); if (mcd->clks) mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->divider_clks) + mtk_clk_unregister_dividers(mcd->divider_clks, + mcd->num_divider_clks, clk_data); if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, mcd->num_composite_clks, clk_data); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index b8e0ff8f52fa..554aecdc1015 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -222,6 +222,8 @@ struct mtk_clk_desc { size_t num_clks; const struct mtk_composite *composite_clks; size_t num_composite_clks; + const struct mtk_clk_divider *divider_clks; + size_t num_divider_clks; const struct mtk_fixed_clk *fixed_clks; size_t num_fixed_clks; const struct mtk_fixed_factor *factor_clks; --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99E51C05027 for ; Mon, 20 Feb 2023 15:01:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232306AbjBTPBx (ORCPT ); Mon, 20 Feb 2023 10:01:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232096AbjBTPBa (ORCPT ); Mon, 20 Feb 2023 10:01:30 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 182EB17144; Mon, 20 Feb 2023 07:01:26 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 16340660216B; Mon, 20 Feb 2023 15:01:22 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905283; bh=QQ6XQKZ9bIiU19j7pgDvnLaRyc13kms874GygHnfkXs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ogXfY0dg/xi97t4wxtCWfs4lhpzJK9RzaON1Fh7RaDbyMFlQnTOiqxZW3/YUQBciZ 2RyKc3y/Lm2cjy6arfW3kOxaq5GIK/Y1aKmHh9QyZ+R9d8eMUero0yM9i9L1bhvt4Q PzErZ6Y60e74Qs5LivrShY4B3WuN14JtzLgbf4emd2F9j2+3V2W7cni7NaWhksPUSC UH6c8v5j0HOTUxEDqYqyqbZMm3VVlhlLZTAtH2mCYmEMISwo5TisZWlthb2cMjiijY DBdxgGt1ju7H9fDZxcqCmPcOgKokPtlZ2d0SdjCb35Fyx/ESS5+n64A1bVKsMRVm86 Z2vB4A5F/qIug== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 05/55] clk: mediatek: mt2712: Migrate topckgen/mcucfg to mtk_clk_simple_probe() Date: Mon, 20 Feb 2023 16:00:21 +0100 Message-Id: <20230220150111.77897-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that the common mtk_clk_simple_{probe,remove}() functions can deal with divider clocks it is possible to migrate more clock drivers to it: in this case, it's about topckgen. While at it, also perform a fast migration for mcucfg. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2712.c | 127 +++++------------------------- 1 file changed, 21 insertions(+), 106 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 94f8fc2a4f7b..db20c46e088b 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -36,14 +36,11 @@ static const struct mtk_fixed_clk top_fixed_clks[] =3D { FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), }; =20 -static const struct mtk_fixed_factor top_early_divs[] =3D { +static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 1), FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 2), -}; - -static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 1), FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, @@ -1295,114 +1292,30 @@ static int clk_mt2712_apmixed_probe(struct platfor= m_device *pdev) return r; } =20 -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt2712_top_init_early(struct device_node *node) -{ - int r, i; - - if (!top_clk_data) { - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - for (i =3D 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - } - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} - -CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen", - clk_mt2712_top_init_early); - -static int clk_mt2712_top_probe(struct platform_device *pdev) -{ - int r, i; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); - return PTR_ERR(base); - } - - if (!top_clk_data) { - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - } else { - for (i =3D 0; i < CLK_TOP_NR_CLK; i++) { - if (top_clk_data->hws[i] =3D=3D ERR_PTR(-EPROBE_DEFER)) - top_clk_data->hws[i] =3D ERR_PTR(-ENOENT); - } - } - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), top_clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - return r; -} - -static int clk_mt2712_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); - return PTR_ERR(base); - } - - clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); - - r =3D mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt2712_clk_lock, clk_data); - if (r) - dev_err(&pdev->dev, "Could not register composites: %d\n", r); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt2712_clk_lock, +}; =20 - return r; -} +static const struct mtk_clk_desc mcu_desc =3D { + .composite_clks =3D mcu_muxes, + .num_composite_clks =3D ARRAY_SIZE(mcu_muxes), + .clk_lock =3D &mt2712_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt2712[] =3D { { .compatible =3D "mediatek,mt2712-apmixedsys", .data =3D clk_mt2712_apmixed_probe, - }, { - .compatible =3D "mediatek,mt2712-topckgen", - .data =3D clk_mt2712_top_probe, - }, { - .compatible =3D "mediatek,mt2712-mcucfg", - .data =3D clk_mt2712_mcu_probe, }, { /* sentinel */ } @@ -1440,7 +1353,9 @@ static const struct mtk_clk_desc peri_desc =3D { =20 static const struct of_device_id of_match_clk_mt2712_simple[] =3D { { .compatible =3D "mediatek,mt2712-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt2712-mcucfg", .data =3D &mcu_desc }, { .compatible =3D "mediatek,mt2712-pericfg", .data =3D &peri_desc, }, + { .compatible =3D "mediatek,mt2712-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E95D2C05027 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905284; bh=q5zJyagO6AeWtRSKKswL/pqMWZmTofXZr4jnHJ4C2l8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QdkDcM/D8aTg0tT08xnLDMEAhY4qB5iMmkbphAwcnx687Ilcw7R/WhGlMzK7kOoNB XpmoFUQuwcRihIHt2+RT/63//tGYj3FfATm4QYusH6JMAKDea49n50Hx9GvKB+zKpE +Wq9wE0DLl+Shk9A/MNX3fI/CvZpCKc0q+gtXSb6OJa3giTxtPdjQQgKKFo7lRiVwu tUL6/c2z9H7mLww3BpTqXISTIPW+O21b5htS4Ow9l3oy6KjKWjVcXlSULTWfKpVrIe yBVvHlgMMjGC9p28l06kn8fmADvw7+tU5i0AXTXU0A6Tca4QKaC/Ch4UXPnmKVZDnL 1bms4Tsgn128g== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 06/55] clk: mediatek: mt2712: Compress clock arrays entries to 90 columns Date: Mon, 20 Feb 2023 16:00:22 +0100 Message-Id: <20230220150111.77897-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Compress the clock arrays entries to allow a maximum of 90 columns: this greatly increases readability and also generously reduces the amount of lines. While at it, also fix some indentation here and there. This is a cosmetic change. No functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2712.c | 681 +++++++++++------------------- 1 file changed, 246 insertions(+), 435 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index db20c46e088b..ce28ee47f5cf 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -37,184 +37,95 @@ static const struct mtk_fixed_clk top_fixed_clks[] =3D= { }; =20 static const struct mtk_fixed_factor top_divs[] =3D { - FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, - 1), - FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, - 2), - FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, - 1), - FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, - 2), - FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, - 3), - FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, - 1), - FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, - 1), - FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, - 2), - FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, - 2), - FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, - 4), - FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, - 8), - FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, - 16), - FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, - 3), - FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, - 2), - FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, - 4), - FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, - 5), - FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, - 2), - FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, - 4), - FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, - 7), - FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, - 2), - FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, - 1), - FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, - 7), - FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, - 26), - FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, - 52), - FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, - 104), - FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, - 208), - FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, - 8), - FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, - 3), - FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, - 8), - FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, - 5), - FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, - 8), - FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, - 1), - FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, - 1), - FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, - 1), - FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, - 1), - FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, - 1), - FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, - 1), - FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, - 1), - FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, - 2), - FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, - 4), - FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, - 8), - FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, - 16), - FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, - 1), - FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, - 2), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, - 4), - FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, - 8), - FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, - 16), - FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, - 1), - FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, - 2), - FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, - 4), - FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, - 8), - FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, - 1), - FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, - 2), - FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, - 4), - FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, - 8), - FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, - 1), - FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, - 1), - FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, - 1), - FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, - 2), - FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, - 1), - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, - 2), - FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, - 1), - FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, - 2), - FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, - 1), - FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, - 2), - FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, - 1), - FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, - 2), - FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, - 4), - FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, - 8), - FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, - 1), - FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, - 2), - FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, - 4), - FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, - 1), - FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, - 2), - FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, - 4), - FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, - 1), - FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, - 2), - FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, - 4), - FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, - 4), - FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, - 3), - FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, - 3), + FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 1), + FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 2), + FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 1), + FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, 2), + FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, 3), + FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, 1), + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2), + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, 3), + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5), + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, 7), + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7), + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, 26), + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, 52), + FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, 104), + FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, 208), + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3), + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5), + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), + FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, 1), + FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, 1), + FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, 1), + FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, 1), + FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, 1), + FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, 1), + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), + FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), + FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, 16), + FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), + FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), + FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, 16), + FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, 2), + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, 4), + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, 8), + FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, 1), + FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, 2), + FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, 4), + FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, 8), + FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, 1), + FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, 1), + FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, 1), + FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, 2), + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2), + FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), + FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, 2), + FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 1), + FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, 2), + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), + FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, 1), + FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, 2), + FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, 4), + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4), + FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), + FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, 2), + FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, 4), + FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, 4), + FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3), + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 3), }; =20 static const char * const axi_parents[] =3D { @@ -734,169 +645,118 @@ static const char * const audull_vtx_parents[] =3D { static struct mtk_composite top_muxes[] =3D { /* CLK_CFG_0 */ MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, - 7, CLK_IS_CRITICAL), + 7, CLK_IS_CRITICAL), MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, - 15, CLK_IS_CRITICAL), - MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", - mm_parents, 0x040, 24, 3, 31), + 15, CLK_IS_CRITICAL), + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", - pwm_parents, 0x050, 0, 2, 7), - MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", - vdec_parents, 0x050, 8, 4, 15), - MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", - venc_parents, 0x050, 16, 4, 23), - MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", - mfg_parents, 0x050, 24, 4, 31), + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7), + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15), + MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23), + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", - camtg_parents, 0x060, 0, 4, 7), - MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", - uart_parents, 0x060, 8, 1, 15), - MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", - spi_parents, 0x060, 16, 3, 23), - MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", - usb20_parents, 0x060, 24, 2, 31), + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7), + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15), + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 16, 3, 23), + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x060, 24, 2, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", - usb30_parents, 0x070, 0, 2, 7), - MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", - msdc50_0_h_parents, 0x070, 8, 3, 15), - MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", - msdc50_0_parents, 0x070, 16, 4, 23), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", - msdc30_1_parents, 0x070, 24, 3, 31), + MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x070, 0, 2, 7), + MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, + 0x070, 8, 3, 15), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, + 0x070, 16, 4, 23), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, + 0x070, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", - msdc30_1_parents, 0x080, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", - msdc30_3_parents, 0x080, 8, 4, 15), - MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", - audio_parents, 0x080, 16, 2, 23), - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", - aud_intbus_parents, 0x080, 24, 3, 31), + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_parents, + 0x080, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, + 0x080, 8, 4, 15), + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, + 0x080, 16, 2, 23), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, + 0x080, 24, 3, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", - pmicspi_parents, 0x090, 0, 3, 7), - MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", - dpilvds1_parents, 0x090, 8, 3, 15), - MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", - atb_parents, 0x090, 16, 2, 23), - MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", - nr_parents, 0x090, 24, 3, 31), + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x090, 0, 3= , 7), + MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", dpilvds1_parents, + 0x090, 8, 3, 15), + MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x090, 16, 2, 23), + MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_parents, 0x090, 24, 3, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", - nfi2x_parents, 0x0a0, 0, 4, 7), - MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", - irda_parents, 0x0a0, 8, 2, 15), - MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", - cci400_parents, 0x0a0, 16, 3, 23), - MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", - aud_1_parents, 0x0a0, 24, 2, 31), + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x0a0, 0, 4, 7), + MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0a0, 8, 2, 15), + MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x0a0, 16, 3, = 23), + MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", - aud_2_parents, 0x0b0, 0, 2, 7), - MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", - mem_mfg_parents, 0x0b0, 8, 2, 15), - MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", - axi_mfg_parents, 0x0b0, 16, 2, 23), - MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", - scam_parents, 0x0b0, 24, 2, 31), + MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0b0, 0, 2, 7), + MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", mem_mfg_parents, + 0x0b0, 8, 2, 15), + MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", axi_mfg_parents, + 0x0b0, 16, 2, 23), + MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x0b0, 24, 2, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", - nfiecc_parents, 0x0c0, 0, 3, 7), - MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", - pe2_mac_p0_parents, 0x0c0, 8, 3, 15), - MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", - pe2_mac_p0_parents, 0x0c0, 16, 3, 23), - MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", - dpilvds_parents, 0x0c0, 24, 3, 31), + MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 0x0c0, 0, 3, 7= ), + MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", pe2_mac_p0_parents, + 0x0c0, 8, 3, 15), + MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", pe2_mac_p0_parents, + 0x0c0, 16, 3, 23), + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0c0, 24, = 3, 31), /* CLK_CFG_9 */ - MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", - msdc50_0_h_parents, 0x0d0, 0, 3, 7), - MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", - hdcp_parents, 0x0d0, 8, 2, 15), - MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", - hdcp_24m_parents, 0x0d0, 16, 2, 23), - MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2, - 31, CLK_IS_CRITICAL), + MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", msdc50_0_h_parents, + 0x0d0, 0, 3, 7), + MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x0d0, 8, 2, 15), + MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, + 0x0d0, 16, 2, 23), + MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, + 0x0d0, 24, 2, 31, CLK_IS_CRITICAL), /* CLK_CFG_10 */ - MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", - spinor_parents, 0x500, 0, 4, 7), - MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", - apll_parents, 0x500, 8, 4, 15), - MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", - apll_parents, 0x500, 16, 4, 23), - MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", - a1sys_hp_parents, 0x500, 24, 3, 31), + MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 0x500, 0, 4, 7= ), + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x500, 8, 4, 15), + MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", apll_parents, 0x500, 16, 4, 23), + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, + 0x500, 24, 3, 31), /* CLK_CFG_11 */ - MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", - a2sys_hp_parents, 0x510, 0, 3, 7), - MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", - asm_l_parents, 0x510, 8, 2, 15), - MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", - asm_l_parents, 0x510, 16, 2, 23), - MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", - asm_l_parents, 0x510, 24, 2, 31), + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a2sys_hp_parents, 0x510, 0= , 3, 7), + MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 0x510, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 0x510, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 0x510, 24, 2, 31), /* CLK_CFG_12 */ - MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", - i2so1_parents, 0x520, 0, 2, 7), - MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", - i2so1_parents, 0x520, 8, 2, 15), - MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", - i2so1_parents, 0x520, 16, 2, 23), - MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", - i2so1_parents, 0x520, 24, 2, 31), + MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", i2so1_parents, 0x520, 0, 2, 7), + MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", i2so1_parents, 0x520, 8, 2, 15), + MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", i2so1_parents, 0x520, 16, 2, 23), + MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", i2so1_parents, 0x520, 24, 2, 31), /* CLK_CFG_13 */ - MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", - i2so1_parents, 0x530, 0, 2, 7), - MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", - i2so1_parents, 0x530, 8, 2, 15), - MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", - i2so1_parents, 0x530, 16, 2, 23), - MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", - i2so1_parents, 0x530, 24, 2, 31), + MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", i2so1_parents, 0x530, 0, 2, 7), + MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", i2so1_parents, 0x530, 8, 2, 15), + MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", i2so1_parents, 0x530, 16, 2, 23), + MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", i2so1_parents, 0x530, 24, 2, 31), /* CLK_CFG_14 */ - MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", - ether_125m_parents, 0x540, 0, 2, 7), - MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", - ether_50m_parents, 0x540, 8, 2, 15), - MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", - jpgdec_parents, 0x540, 16, 4, 23), - MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", - spislv_parents, 0x540, 24, 3, 31), + MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", ether_125m_parents, + 0x540, 0, 2, 7), + MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", ether_50m_parents, + 0x540, 8, 2, 15), + MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", jpgdec_parents, 0x540, 16, 4, = 23), + MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", spislv_parents, 0x540, 24, 3, = 31), /* CLK_CFG_15 */ - MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", - ether_parents, 0x550, 0, 2, 7), - MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", - camtg_parents, 0x550, 8, 4, 15), - MUX_GATE(CLK_TOP_DI_SEL, "di_sel", - di_parents, 0x550, 16, 3, 23), - MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", - tvd_parents, 0x550, 24, 2, 31), + MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", ether_parents, 0x550, 0= , 2, 7), + MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", camtg_parents, 0x550, 8, 4, 15= ), + MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 0x550, 16, 3, 23), + MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", tvd_parents, 0x550, 24, 2, 31), /* CLK_CFG_16 */ - MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", - i2c_parents, 0x560, 0, 3, 7), - MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", - pwm_parents, 0x560, 8, 2, 15), - MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", - msdc0p_aes_parents, 0x560, 16, 2, 23), - MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", - cmsys_parents, 0x560, 24, 3, 31), + MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x560, 0, 3, 7), + MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2= , 15), + MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", msdc0p_aes_parents, + 0x560, 16, 2, 23), + MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 0x560, 24, 3, 31), /* CLK_CFG_17 */ - MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", - gcpu_parents, 0x570, 0, 3, 7), + MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x570, 0, 3, 7), /* CLK_AUDDIV_4 */ - MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", - aud_apll1_parents, 0x134, 0, 1), - MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", - aud_apll2_parents, 0x134, 1, 1), - MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", - audull_vtx_parents, 0x134, 31, 1), - MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", - apll1_ref_parents, 0x134, 4, 3), - MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", - apll1_ref_parents, 0x134, 7, 3), + MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", aud_apll1_parents, 0x134, 0, = 1), + MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", aud_apll2_parents, 0x134, 1, = 1), + MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", audull_vtx_parents, + 0x134, 31, 1), + MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", apll1_ref_parents, 0x134, 4, = 3), + MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", apll1_ref_parents, 0x134, 7, = 3), }; =20 static const char * const mcu_mp0_parents[] =3D { @@ -923,13 +783,13 @@ static const char * const mcu_bus_parents[] =3D { static struct mtk_composite mcu_muxes[] =3D { /* mp0_pll_divider_cfg */ MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, - 9, 2, -1, CLK_IS_CRITICAL), + 9, 2, -1, CLK_IS_CRITICAL), /* mp2_pll_divider_cfg */ MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, - 9, 2, -1, CLK_IS_CRITICAL), + 9, 2, -1, CLK_IS_CRITICAL), /* bus_pll_divider_cfg */ MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, - 9, 2, -1, CLK_IS_CRITICAL), + 9, 2, -1, CLK_IS_CRITICAL), }; =20 static const struct mtk_clk_divider top_adj_divs[] =3D { @@ -1061,100 +921,54 @@ static const struct mtk_gate_regs peri2_cg_regs =3D= { =20 static const struct mtk_gate peri_clks[] =3D { /* PERI0 */ - GATE_PERI0(CLK_PERI_NFI, "per_nfi", - "axi_sel", 0), - GATE_PERI0(CLK_PERI_THERM, "per_therm", - "axi_sel", 1), - GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", - "pwm_sel", 2), - GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", - "pwm_sel", 3), - GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", - "pwm_sel", 4), - GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", - "pwm_sel", 5), - GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", - "pwm_sel", 6), - GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", - "pwm_sel", 7), - GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", - "pwm_sel", 8), - GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", - "pwm_sel", 9), - GATE_PERI0(CLK_PERI_PWM, "per_pwm", - "pwm_sel", 10), - GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", - "axi_sel", 13), - GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", - "msdc50_0_sel", 14), - GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", - "msdc30_1_sel", 15), - GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", - "msdc30_2_sel", 16), - GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", - "msdc30_3_sel", 17), - GATE_PERI0(CLK_PERI_UART0, "per_uart0", - "uart_sel", 20), - GATE_PERI0(CLK_PERI_UART1, "per_uart1", - "uart_sel", 21), - GATE_PERI0(CLK_PERI_UART2, "per_uart2", - "uart_sel", 22), - GATE_PERI0(CLK_PERI_UART3, "per_uart3", - "uart_sel", 23), - GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", - "axi_sel", 24), - GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", - "axi_sel", 25), - GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", - "axi_sel", 26), - GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", - "axi_sel", 27), - GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", - "axi_sel", 28), - GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", - "ltepll_fs26m", 29), - GATE_PERI0(CLK_PERI_SPI0, "per_spi0", - "spi_sel", 30), + GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0), + GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1), + GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2), + GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3), + GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4), + GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5), + GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6), + GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7), + GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8), + GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9), + GATE_PERI0(CLK_PERI_PWM, "per_pwm", "pwm_sel", 10), + GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", "axi_sel", 13), + GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", "msdc50_0_sel", 14), + GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", "msdc30_1_sel", 15), + GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", "msdc30_2_sel", 16), + GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", "msdc30_3_sel", 17), + GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20), + GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21), + GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22), + GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23), + GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", "axi_sel", 24), + GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", "axi_sel", 25), + GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", "axi_sel", 26), + GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", "axi_sel", 27), + GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", "axi_sel", 28), + GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", "ltepll_fs26m", 29), + GATE_PERI0(CLK_PERI_SPI0, "per_spi0", "spi_sel", 30), /* PERI1 */ - GATE_PERI1(CLK_PERI_SPI, "per_spi", - "spinor_sel", 1), - GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", - "axi_sel", 3), - GATE_PERI1(CLK_PERI_SPI2, "per_spi2", - "spi_sel", 5), - GATE_PERI1(CLK_PERI_SPI3, "per_spi3", - "spi_sel", 6), - GATE_PERI1(CLK_PERI_SPI5, "per_spi5", - "spi_sel", 8), - GATE_PERI1(CLK_PERI_UART4, "per_uart4", - "uart_sel", 9), - GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", - "uart_sel", 11), - GATE_PERI1(CLK_PERI_GMAC, "per_gmac", - "uart_sel", 12), - GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", - "uart_sel", 14), - GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", - "uart_sel", 15), - GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", - "uart_sel", 16), + GATE_PERI1(CLK_PERI_SPI, "per_spi", "spinor_sel", 1), + GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", "axi_sel", 3), + GATE_PERI1(CLK_PERI_SPI2, "per_spi2", "spi_sel", 5), + GATE_PERI1(CLK_PERI_SPI3, "per_spi3", "spi_sel", 6), + GATE_PERI1(CLK_PERI_SPI5, "per_spi5", "spi_sel", 8), + GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9), + GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11), + GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12), + GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14), + GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15), + GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", "uart_sel", 16), /* PERI2 */ - GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", - "msdc50_0_sel", 0), - GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", - "msdc30_1_sel", 1), - GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", - "msdc30_2_sel", 2), - GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", - "msdc30_3_sel", 3), - GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", - "msdc50_0_h_sel", 4), - GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", - "msdc50_3_h_sel", 5), - GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", - "axi_sel", 6), - GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", - "mem_sel", 7), + GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", "msdc50_0_sel", 0), + GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", "msdc30_1_sel", 1), + GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", "msdc30_2_sel", 2), + GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", "msdc30_3_sel", 3), + GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", "msdc50_0_h_sel",= 4), + GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", "msdc50_3_h_sel",= 5), + GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", "axi_sel", 6), + GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7), }; =20 #define MT2712_PLL_FMAX (3000UL * MHZ) @@ -1221,38 +1035,35 @@ static const struct mtk_pll_div_table mmpll_div_tab= le[] =3D { =20 static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100, - HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), + HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100, - HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), + HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100, - 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), + 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100, - 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), + 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100, - 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), + 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100, - 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), + 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100, - 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), + 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100, - 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), + 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100, - 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), + 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100, - 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), + 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100, - 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), + 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100, - 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, - mmpll_div_table), + 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table), PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100, - HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, - armca35pll_div_table), + HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_tab= le), PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100, - 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, - armca72pll_div_table), + 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table), PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100, - 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), + 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; =20 static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94558C64ED8 for ; Mon, 20 Feb 2023 15:02:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232334AbjBTPCH (ORCPT ); Mon, 20 Feb 2023 10:02:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232283AbjBTPBe (ORCPT ); Mon, 20 Feb 2023 10:01:34 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 460831DBA6; Mon, 20 Feb 2023 07:01:27 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id DB3E16602172; Mon, 20 Feb 2023 15:01:24 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905286; bh=hBKMIaocGmn56Ueun8XDpc5jewvKlJ1Bcnnlk9bLbIY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CR0Esl4VpgucDhXdfypjh06yKfjMp3hjCauJmaM0F0/2R76+7Q4JG1QpFusjwNCud rvAXeVZ9l+oj7EjvWElux8A5Kizta0/qjg24LDqZCZJdQ+MORg6vga/Dz6pKR3wZDy HB6hhisykHRPiKrtuY96RLoZq1X4YAF2zrnEoI79raMc1x0toeJwRpS20n71G42urx oUTcwHX4Y42vs2KBK1Hz5f0nCrPTmjR5dWVDfYdBTOhuioIJSue8L7zXkWPvfGH/eU zZka1E0aVh78E/Yuard3xRrDza2YIidAv5YozkPpAMS1vhJZDqcFM62ak32xjfSAbH AO16kmf8iXr1w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 07/55] clk: mediatek: mt2712: Add error handling to clk_mt2712_apmixed_probe() Date: Mon, 20 Feb 2023 16:00:23 +0100 Message-Id: <20230220150111.77897-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This function was completely missing error handling: add it. Fixes: e2f744a82d72 ("clk: mediatek: Add MT2712 clock support") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2712.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index ce28ee47f5cf..8aa361f0fa13 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1091,15 +1091,25 @@ static int clk_mt2712_apmixed_probe(struct platform= _device *pdev) struct device_node *node =3D pdev->dev.of_node; =20 clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_clk_data; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { + dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r); + goto unregister_plls; + } =20 - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + return 0; =20 +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); return r; } =20 --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A581FC05027 for ; Mon, 20 Feb 2023 15:02:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231470AbjBTPCL (ORCPT ); Mon, 20 Feb 2023 10:02:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232296AbjBTPBl (ORCPT ); Mon, 20 Feb 2023 10:01:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A92771DB9F; Mon, 20 Feb 2023 07:01:28 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4C0D46602173; Mon, 20 Feb 2023 15:01:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905287; bh=GdSL9o+qrqfTV42i6FES8JMTn86p5TawnKDDDvZtsns=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kue9It0/OiTFaYGFOKr80tdZRqFkKne+YqcJCE/HNQcbcsTN5VDt/dJteID+FNjXo bwH9hD3E3UoulaKHl4A50Q6acFvbCMbhSkiyRjdsWdsLtpidnMeQtV5mPzWQumVhWd LKbxFRbCYcoEg/qP9E5L3TPckUVmhvzOINhaAyOvjTNeIXI/3kt3hnBHJnQ9x4FxK+ qROc4RcOO2DbU8G6WIBZ4hzZdco2+rAb8W0DpB1JJJ4I71hnmtT/X8rmNAoi7rv0lr qBfaAx4TFr+4nd4eugfKZlxtd0In5zT9m/8xNTmUP3k1NTU3IJplVJ4CkypIpnvTsc tB7YbshGAUL2g== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 08/55] clk: mediatek: mt2712: Move apmixedsys clock driver to its own file Date: Mon, 20 Feb 2023 16:00:24 +0100 Message-Id: <20230220150111.77897-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The only clock driver that does not support mtk_clk_simple_probe() is apmixedsys: in preparation for enabling module build of non-critical mt2712 clocks, move this to its own file. While at it, also fix some indentation issues in the PLLs table. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 153 +++++++++++++++++ drivers/clk/mediatek/clk-mt2712.c | 164 ------------------- 3 files changed, 154 insertions(+), 165 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt2712-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e5d018270ed0..3c7dd19cdddf 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -38,7 +38,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) +=3D clk-mt2701-hi= f.o obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) +=3D clk-mt2701-img.o obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) +=3D clk-mt2701-mm.o obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) +=3D clk-mt2701-vdec.o -obj-$(CONFIG_COMMON_CLK_MT2712) +=3D clk-mt2712.o +obj-$(CONFIG_COMMON_CLK_MT2712) +=3D clk-mt2712.o clk-mt2712-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) +=3D clk-mt2712-bdp.o obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) +=3D clk-mt2712-img.o obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) +=3D clk-mt2712-jpgdec.o diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c new file mode 100644 index 000000000000..1e1a8272a4ac --- /dev/null +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017 MediaTek Inc. + * Weiyi Lu + * Copyright (c) 2023 Collabora Ltd. + * AngeloGioacchino Del Regno + */ +#include +#include +#include + +#include "clk-pll.h" +#include "clk-mtk.h" + +#include + +#define MT2712_PLL_FMAX (3000UL * MHZ) + +#define CON0_MT2712_RST_BAR BIT(24) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _div_table) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D CON0_MT2712_RST_BAR, \ + .fmax =3D MT2712_PLL_FMAX, \ + .pcwbits =3D _pcwbits, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .tuner_en_reg =3D _tuner_en_reg, \ + .tuner_en_bit =3D _tuner_en_bit, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .div_table =3D _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \ + _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ + _pcw_shift, NULL) + +static const struct mtk_pll_div_table armca35pll_div_table[] =3D { + { .div =3D 0, .freq =3D MT2712_PLL_FMAX }, + { .div =3D 1, .freq =3D 1202500000 }, + { .div =3D 2, .freq =3D 500500000 }, + { .div =3D 3, .freq =3D 315250000 }, + { .div =3D 4, .freq =3D 157625000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_div_table armca72pll_div_table[] =3D { + { .div =3D 0, .freq =3D MT2712_PLL_FMAX }, + { .div =3D 1, .freq =3D 994500000 }, + { .div =3D 2, .freq =3D 520000000 }, + { .div =3D 3, .freq =3D 315250000 }, + { .div =3D 4, .freq =3D 157625000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_div_table mmpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT2712_PLL_FMAX }, + { .div =3D 1, .freq =3D 1001000000 }, + { .div =3D 2, .freq =3D 601250000 }, + { .div =3D 3, .freq =3D 250250000 }, + { .div =3D 4, .freq =3D 125125000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data plls[] =3D { + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100, + HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100, + HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), + PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100, + 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), + PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100, + 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100, + 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100, + 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100, + 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), + PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100, + 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100, + 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), + PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100, + 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100, + 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100, + 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table), + PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100, + HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_tab= le), + PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100, + 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table), + PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100, + 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), +}; + +static int clk_mt2712_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + int r; + struct device_node *node =3D pdev->dev.of_node; + + clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_clk_data; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { + dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r); + goto unregister_plls; + } + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt2712_apmixed[] =3D { + { .compatible =3D "mediatek,mt2712-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt2712_apmixed_drv =3D { + .probe =3D clk_mt2712_apmixed_probe, + .driver =3D { + .name =3D "clk-mt2712-apmixed", + .of_match_table =3D of_match_clk_mt2712_apmixed, + }, +}; +builtin_platform_driver(clk_mt2712_apmixed_drv) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 8aa361f0fa13..c5fd76d1b9df 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -14,7 +14,6 @@ #include =20 #include "clk-gate.h" -#include "clk-pll.h" #include "clk-mtk.h" =20 #include @@ -971,101 +970,6 @@ static const struct mtk_gate peri_clks[] =3D { GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7), }; =20 -#define MT2712_PLL_FMAX (3000UL * MHZ) - -#define CON0_MT2712_RST_BAR BIT(24) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _div_table) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D CON0_MT2712_RST_BAR, \ - .fmax =3D MT2712_PLL_FMAX, \ - .pcwbits =3D _pcwbits, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .tuner_en_reg =3D _tuner_en_reg, \ - .tuner_en_bit =3D _tuner_en_bit, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .div_table =3D _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \ - _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ - _pcw_shift, NULL) - -static const struct mtk_pll_div_table armca35pll_div_table[] =3D { - { .div =3D 0, .freq =3D MT2712_PLL_FMAX }, - { .div =3D 1, .freq =3D 1202500000 }, - { .div =3D 2, .freq =3D 500500000 }, - { .div =3D 3, .freq =3D 315250000 }, - { .div =3D 4, .freq =3D 157625000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table armca72pll_div_table[] =3D { - { .div =3D 0, .freq =3D MT2712_PLL_FMAX }, - { .div =3D 1, .freq =3D 994500000 }, - { .div =3D 2, .freq =3D 520000000 }, - { .div =3D 3, .freq =3D 315250000 }, - { .div =3D 4, .freq =3D 157625000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table mmpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT2712_PLL_FMAX }, - { .div =3D 1, .freq =3D 1001000000 }, - { .div =3D 2, .freq =3D 601250000 }, - { .div =3D 3, .freq =3D 250250000 }, - { .div =3D 4, .freq =3D 125125000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100, - HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100, - HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), - PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100, - 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), - PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100, - 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100, - 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100, - 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100, - 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), - PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100, - 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100, - 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), - PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100, - 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100, - 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100, - 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table), - PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100, - HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_tab= le), - PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100, - 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table), - PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100, - 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), -}; - static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; =20 @@ -1084,35 +988,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = =3D { }, }; =20 -static int clk_mt2712_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - if (r) - goto free_clk_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r); - goto unregister_plls; - } - - return 0; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - static const struct mtk_clk_desc topck_desc =3D { .clks =3D top_clks, .num_clks =3D ARRAY_SIZE(top_clks), @@ -1133,33 +1008,6 @@ static const struct mtk_clk_desc mcu_desc =3D { .clk_lock =3D &mt2712_clk_lock, }; =20 -static const struct of_device_id of_match_clk_mt2712[] =3D { - { - .compatible =3D "mediatek,mt2712-apmixedsys", - .data =3D clk_mt2712_apmixed_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt2712_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *); - int r; - - clk_probe =3D of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r =3D clk_probe(pdev); - if (r !=3D 0) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static const struct mtk_clk_desc infra_desc =3D { .clks =3D infra_clks, .num_clks =3D ARRAY_SIZE(infra_clks), @@ -1189,20 +1037,8 @@ static struct platform_driver clk_mt2712_simple_drv = =3D { }, }; =20 -static struct platform_driver clk_mt2712_drv =3D { - .probe =3D clk_mt2712_probe, - .driver =3D { - .name =3D "clk-mt2712", - .of_match_table =3D of_match_clk_mt2712, - }, -}; - static int __init clk_mt2712_init(void) { - int ret =3D platform_driver_register(&clk_mt2712_drv); - - if (ret) - return ret; return platform_driver_register(&clk_mt2712_simple_drv); } =20 --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3494C05027 for ; Mon, 20 Feb 2023 15:02:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232070AbjBTPCO (ORCPT ); Mon, 20 Feb 2023 10:02:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231781AbjBTPCE (ORCPT ); Mon, 20 Feb 2023 10:02:04 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DE021DBB4; Mon, 20 Feb 2023 07:01:30 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B3B946602176; Mon, 20 Feb 2023 15:01:27 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905288; bh=1HjfxwBN9RMNJRVz4a+nf3R3egMM6Q1nEwSqqRs4zLo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X8jz3DF7JRSNqwlW0P6Qkg172fLy3cQRNCIhmLdsgg5oRi4wXUsxUZK97lBLE2ZMQ +FUsZuFVRoRl3aHgFYbl1j48qYx4FgBViu08oYHjzh6U+f5TAKUEdwGnn8xmpbLhgz otYwtMb/nnVy50Z+fWgTApME6HxWeUkff4XZ+Yi19MtStO4yHcy/ItU1KVj3njiaag /fSt3DXsv7jMUT047dC+vpRyn94Vrn2ryD92vn+xhQyBTjRmGJgoNgx5TQ7ZqUYdqQ ZOW35mSeJj5VzRhSoK2Lg2sE4mGyLNLzifA7KBkg1HwYoUnvoUw9B5P1D7KZ0S7gmh nD2CEe+qQZCkw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 09/55] clk: mediatek: mt2712-apmixedsys: Add .remove() callback for module build Date: Mon, 20 Feb 2023 16:00:25 +0100 Message-Id: <20230220150111.77897-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a .remove() callback to the apmixedsys driver to allow full module build; while at it, also change the usage of builtin_platform_driver() to module_platform_driver() to actually make use of the new callback. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c index 1e1a8272a4ac..2f4061c9a59e 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -138,6 +138,18 @@ static int clk_mt2712_apmixed_probe(struct platform_de= vice *pdev) return r; } =20 +static int clk_mt2712_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + static const struct of_device_id of_match_clk_mt2712_apmixed[] =3D { { .compatible =3D "mediatek,mt2712-apmixedsys" }, { /* sentinel */ } @@ -145,9 +157,10 @@ static const struct of_device_id of_match_clk_mt2712_a= pmixed[] =3D { =20 static struct platform_driver clk_mt2712_apmixed_drv =3D { .probe =3D clk_mt2712_apmixed_probe, + .remove =3D clk_mt2712_apmixed_remove, .driver =3D { .name =3D "clk-mt2712-apmixed", .of_match_table =3D of_match_clk_mt2712_apmixed, }, }; -builtin_platform_driver(clk_mt2712_apmixed_drv) +module_platform_driver(clk_mt2712_apmixed_drv) --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A53D4C64EC4 for ; Mon, 20 Feb 2023 15:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231313AbjBTPCS (ORCPT ); Mon, 20 Feb 2023 10:02:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232199AbjBTPCF (ORCPT ); Mon, 20 Feb 2023 10:02:05 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78EB51F90A; Mon, 20 Feb 2023 07:01:31 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 215EB6602179; Mon, 20 Feb 2023 15:01:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905290; bh=Jd0WSEgoMoiyLJ/JPwWzI6i2w8ARgz466SU1nHCnAdI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fF77HQ/0wexUKQO+Um9twd15V+8MkmbBJYlqBgT2eA21g72cgtze+YLA7i7+7hbMv fKRgjKF3MeYOO0IUClCLuqYLf4/sBpwJ5jltaJUC2qkQbM25BzIdLyWwiLn6K03bwy imlEpx+Hh48IPsoXLmXlfSdZyg86WocMcwCP1wrfQj8j4pjZUHl0PEWqToVsu6DZHi ROflXO8TTNpQGZekRJIn1x64mc9UiQ6Hal4ipYAgbWQKLKoKPqnO8Ch+Cc/mBle3lQ ymZPrI8xtjJSOX+wz9hpK7owTuCHxLoj/uPKpsDE35xwNTHz5sYgX9LWrTWxNRQ1fm HuwpSFioQ1vZQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 10/55] clk: mediatek: mt2712: Change to use module_platform_driver macro Date: Mon, 20 Feb 2023 16:00:26 +0100 Message-Id: <20230220150111.77897-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that all of the clocks in clk-mt2712.c are using the common mtk_clk_simple_{probe,remove}() callbacks we can safely migrate to module_platform_driver. While at it, also drop all references to `simple` in the specific context of mt2712 as that was used in the past only to allow us to have two platform_driver(s) in one file. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2712.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index c5fd76d1b9df..937c370d6765 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1020,7 +1020,7 @@ static const struct mtk_clk_desc peri_desc =3D { .rst_desc =3D &clk_rst_desc[1], }; =20 -static const struct of_device_id of_match_clk_mt2712_simple[] =3D { +static const struct of_device_id of_match_clk_mt2712[] =3D { { .compatible =3D "mediatek,mt2712-infracfg", .data =3D &infra_desc }, { .compatible =3D "mediatek,mt2712-mcucfg", .data =3D &mcu_desc }, { .compatible =3D "mediatek,mt2712-pericfg", .data =3D &peri_desc, }, @@ -1028,18 +1028,12 @@ static const struct of_device_id of_match_clk_mt271= 2_simple[] =3D { { /* sentinel */ } }; =20 -static struct platform_driver clk_mt2712_simple_drv =3D { +static struct platform_driver clk_mt2712_drv =3D { .probe =3D mtk_clk_simple_probe, .remove =3D mtk_clk_simple_remove, .driver =3D { - .name =3D "clk-mt2712-simple", - .of_match_table =3D of_match_clk_mt2712_simple, + .name =3D "clk-mt2712", + .of_match_table =3D of_match_clk_mt2712, }, }; - -static int __init clk_mt2712_init(void) -{ - return platform_driver_register(&clk_mt2712_simple_drv); -} - -arch_initcall(clk_mt2712_init); +module_platform_driver(clk_mt2712_drv); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3B9EC636CC for ; Mon, 20 Feb 2023 15:02:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232621AbjBTPCU (ORCPT ); Mon, 20 Feb 2023 10:02:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232311AbjBTPCF (ORCPT ); Mon, 20 Feb 2023 10:02:05 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAEC21EFD3; Mon, 20 Feb 2023 07:01:32 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 820B76602166; Mon, 20 Feb 2023 15:01:30 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905291; bh=DEMsB2eEoSt9vHXPUVn6NRj+B1E7zyKiJqK46envC14=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PNOKlRcMxMy0STqarl40xDMtEO00ZnvIhzAMIp+a4wIfz1T6x6N0y0vtVFGvX1rsm 1tZyxg9Z+IinKqX1Xyc52q2URJPF73Vyh+uG7Z4QQ/ARVdNwjbuSB/BViycY2B41Rb +CfoUaqpWE144AGmIrgtPWCVbsenA5wQzf381GR2rU7jWG/rJLQOGIbIIb2YLQHlcD 6n2kOGsFXKXm9GOMKAv+KMHbGUqYo4fQRPHoEDzwaYtPkqn8GrfJwpicf83pfiY0aD 0lTiCnD4cxmFC1aPFqqFaDDv3kGQjSeIOeMpVaKXH3m3HcIBGMDWVvBOHqKcoiL3FB zjDJwmjZG4n1Q== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 11/55] clk: mediatek: mt8365: Move apmixedsys clock driver to its own file Date: Mon, 20 Feb 2023 16:00:27 +0100 Message-Id: <20230220150111.77897-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating all other mt8365 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 164 +++++++++++++++++++ drivers/clk/mediatek/clk-mt8365.c | 143 ---------------- 3 files changed, 165 insertions(+), 144 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8365-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 3c7dd19cdddf..b004a47026d4 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -112,7 +112,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195) +=3D clk-mt8195-apmixed= sys.o clk-mt8195-topckgen.o clk-mt8195-venc.o clk-mt8195-vpp0.o clk-mt8195-vpp1.o \ clk-mt8195-wpe.o clk-mt8195-imp_iic_wrap.o \ clk-mt8195-apusys_pll.o -obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365.o +obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365.o clk-mt8365-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) +=3D clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) +=3D clk-mt8365-cam.o obj-$(CONFIG_COMMON_CLK_MT8365_MFG) +=3D clk-mt8365-mfg.o diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8365-apmixedsys.c new file mode 100644 index 000000000000..6f0fdf92bbd2 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2023 Collabora Ltd. + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-mtk.h" + +#define MT8365_PLL_FMAX (3800UL * MHZ) +#define MT8365_PLL_FMIN (1500UL * MHZ) +#define CON0_MT8365_RST_BAR BIT(23) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ + _rst_bar_mask, _pcw_chg_reg) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D _rst_bar_mask, \ + .fmax =3D MT8365_PLL_FMAX, \ + .fmin =3D MT8365_PLL_FMIN, \ + .pcwbits =3D _pcwbits, \ + .pcwibits =3D 8, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .tuner_en_reg =3D _tuner_en_reg, \ + .tuner_en_bit =3D _tuner_en_bit, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .pcw_chg_reg =3D _pcw_chg_reg, \ + .div_table =3D _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, \ + _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ + _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ + _pcw_chg_reg) \ + +static const struct mtk_pll_div_table armpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, + { .div =3D 1, .freq =3D 1500 * MHZ }, + { .div =3D 2, .freq =3D 750 * MHZ }, + { .div =3D 3, .freq =3D 375 * MHZ }, + { .div =3D 4, .freq =3D 182500000 }, + { } /* sentinel */ +}; + +static const struct mtk_pll_div_table mfgpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, + { .div =3D 1, .freq =3D 1600 * MHZ }, + { .div =3D 2, .freq =3D 800 * MHZ }, + { .div =3D 3, .freq =3D 400 * MHZ }, + { .div =3D 4, .freq =3D 200 * MHZ }, + { } /* sentinel */ +}; + +static const struct mtk_pll_div_table dsppll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, + { .div =3D 1, .freq =3D 1600 * MHZ }, + { .div =3D 2, .freq =3D 600 * MHZ }, + { .div =3D 3, .freq =3D 400 * MHZ }, + { .div =3D 4, .freq =3D 200 * MHZ }, + { } /* sentinel */ +}; + +static const struct mtk_pll_data plls[] =3D { + PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, + 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, + HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, CON0_MT8365_RST_BAR= , 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, + HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, CON0_MT8365_RST_BAR= , 0), + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, + 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, + 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, + 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, + 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, + 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, + 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), + PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, + 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), + PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, + 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), +}; + +static int clk_mt8365_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct clk_hw *hw; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + hw =3D devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, + base + 0x204, 0, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[CLK_APMIXED_UNIV_EN] =3D hw; + + hw =3D devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, + base + 0x204, 1, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[CLK_APMIXED_USB20_EN] =3D hw; + + ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_plls; + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8365_apmixed[] =3D { + { .compatible =3D "mediatek,mt8365-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8365_apmixed_drv =3D { + .probe =3D clk_mt8365_apmixed_probe, + .driver =3D { + .name =3D "clk-mt8365-apmixed", + .of_match_table =3D of_match_clk_mt8365_apmixed, + }, +}; +builtin_platform_driver(clk_mt8365_apmixed_drv) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index c9faa07ec0a6..91449a7cf608 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -17,7 +17,6 @@ #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-pll.h" =20 static DEFINE_SPINLOCK(mt8365_clk_lock); =20 @@ -757,145 +756,6 @@ static const struct mtk_simple_gate peri_clks[] =3D { { CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 }, }; =20 -#define MT8365_PLL_FMAX (3800UL * MHZ) -#define MT8365_PLL_FMIN (1500UL * MHZ) -#define CON0_MT8365_RST_BAR BIT(23) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ - _rst_bar_mask, _pcw_chg_reg) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D _rst_bar_mask, \ - .fmax =3D MT8365_PLL_FMAX, \ - .fmin =3D MT8365_PLL_FMIN, \ - .pcwbits =3D _pcwbits, \ - .pcwibits =3D 8, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .tuner_en_reg =3D _tuner_en_reg, \ - .tuner_en_bit =3D _tuner_en_bit, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .pcw_chg_reg =3D _pcw_chg_reg, \ - .div_table =3D _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, \ - _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ - _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ - _pcw_chg_reg) \ - -static const struct mtk_pll_div_table armpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, - { .div =3D 1, .freq =3D 1500 * MHZ }, - { .div =3D 2, .freq =3D 750 * MHZ }, - { .div =3D 3, .freq =3D 375 * MHZ }, - { .div =3D 4, .freq =3D 182500000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table mfgpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, - { .div =3D 1, .freq =3D 1600 * MHZ }, - { .div =3D 2, .freq =3D 800 * MHZ }, - { .div =3D 3, .freq =3D 400 * MHZ }, - { .div =3D 4, .freq =3D 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table dsppll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8365_PLL_FMAX }, - { .div =3D 1, .freq =3D 1600 * MHZ }, - { .div =3D 2, .freq =3D 600 * MHZ }, - { .div =3D 3, .freq =3D 400 * MHZ }, - { .div =3D 4, .freq =3D 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] =3D { - PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, - 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, - HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, - CON0_MT8365_RST_BAR, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, - HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, - CON0_MT8365_RST_BAR, 0), - PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, - 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, - 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, - 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, - 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, - 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, - 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), - PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, - 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), - PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, - 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), -}; - -static int clk_mt8365_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - struct clk_hw *hw; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - hw =3D devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, - base + 0x204, 0, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - clk_data->hws[CLK_APMIXED_UNIV_EN] =3D hw; - - hw =3D devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, - base + 0x204, 1, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - clk_data->hws[CLK_APMIXED_USB20_EN] =3D hw; - - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_plls; - - return 0; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - - return ret; -} - static int clk_mt8365_register_mtk_simple_gates(struct device *dev, void __iomem *bas= e, struct clk_hw_onecell_data *clk_data, @@ -1104,9 +964,6 @@ static int clk_mt8365_mcu_probe(struct platform_device= *pdev) =20 static const struct of_device_id of_match_clk_mt8365[] =3D { { - .compatible =3D "mediatek,mt8365-apmixedsys", - .data =3D clk_mt8365_apmixed_probe, - }, { .compatible =3D "mediatek,mt8365-topckgen", .data =3D clk_mt8365_top_probe, }, { --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA703C05027 for ; Mon, 20 Feb 2023 15:02:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbjBTPCY (ORCPT ); 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b=KHuIS/xWtKIKgBwwCBNTInzSx1KICo1agZSAi6zXMq2gYOXt0fkRuYy9RbpYVsZC1 ILnYlBhI0aS+SKE3WNixwyOFXlRP55cHspygJH/cGr82j0AEHEtHacv8JJ4ah/n0a3 Hpf5830duaLsGgu0tyWhlC/6lbXBZe7vnr148Zjpd0GOA4qySTnj9QewhCAnPOiUQI 1brxW/0bK5tpBe/Ym3l7cwkunm77FPq7JXsmJUnMsA381P5HgdXBjERxi/GjTomxFC l0RwvYLX4AlJVpXKQ6LCXhmHl3QNuIedPEV8bViYSRyUknW4GWJyrAoQMOFxmLN+mr hw5zlv2Au/JTQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 12/55] clk: mediatek: mt8365: Convert simple_gate to mtk_gate clocks Date: Mon, 20 Feb 2023 16:00:28 +0100 Message-Id: <20230220150111.77897-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On this SoC some clocks apparently don't have different offsets for set/clr/sta registers hence they can be set, cleared and status-read on one register: this means that it was possible to use simpler gate clocks instead of custom mtk_gate ones. In preparation for converting this clock driver to the common probe mechanism for MediaTek clocks, perform a conversion from simple_gate to mtk_gate clocks since the latter does provide implicit support for simple gate clocks as well. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8365.c | 189 +++++++++++++----------------- 1 file changed, 82 insertions(+), 107 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index 91449a7cf608..85fe7586a69b 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2022 MediaTek Inc. + * Copyright (C) 2023 Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #include @@ -393,12 +395,6 @@ static struct mtk_composite top_misc_mux_gates[] =3D { 0x0ec, 0, 2, 7), }; =20 -struct mt8365_clk_audio_mux { - int id; - const char *name; - u8 shift; -}; - static struct mt8365_clk_audio_mux top_misc_muxes[] =3D { { CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", 11}, { CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", 12}, @@ -569,35 +565,56 @@ static const struct mtk_clk_divider top_adj_divs[] = =3D { 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), }; =20 -struct mtk_simple_gate { - int id; - const char *name; - const char *parent; - u32 reg; - u8 shift; - unsigned long gate_flags; -}; - -static const struct mtk_simple_gate top_clk_gates[] =3D { - { CLK_TOP_CONN_32K, "conn_32k", "clk32k", 0x0, 10, CLK_GATE_SET_TO_DISABL= E }, - { CLK_TOP_CONN_26M, "conn_26m", "clk26m", 0x0, 11, CLK_GATE_SET_TO_DISABL= E }, - { CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 0x0, 16, CLK_GATE_SET_TO_DISABLE = }, - { CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 0x0, 17, CLK_GATE_SET_TO_DISABLE = }, - { CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 0x104, 8, 0 }, - { CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 0x104, 9, 0 = }, - { CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 0x104, 20,= 0 }, - { CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 0x104, 21, 0 }, - { CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 0x104, 22, 0 }, - { CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 0x104, 23, 0 }, - { CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0x320, 0, 0 }, - { CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 0x320, 1, 0 }, - { CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 0x320, 2, 0 }, - { CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 0x320, 3, 0 }, - { CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 0x320, 4, 0 = }, - { CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 0x320, 5, 0= }, - { CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 0x320, 6, 0 }, - { CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 0x320, 7, 0 }, - { CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 0x320, 8, 0 }, +static const struct mtk_gate_regs top0_cg_regs =3D { + .set_ofs =3D 0, + .clr_ofs =3D 0, + .sta_ofs =3D 0, +}; + +static const struct mtk_gate_regs top1_cg_regs =3D { + .set_ofs =3D 0x104, + .clr_ofs =3D 0x104, + .sta_ofs =3D 0x104, +}; + +static const struct mtk_gate_regs top2_cg_regs =3D { + .set_ofs =3D 0x320, + .clr_ofs =3D 0x320, + .sta_ofs =3D 0x320, +}; + +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr_inv) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr) + +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate top_clk_gates[] =3D { + GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10), + GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11), + GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16), + GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17), + GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9), + GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20= ), + GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21), + GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22), + GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23), + GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0), + GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1), + GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2), + GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3), + GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4), + GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5), + GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6), + GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7), + GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8), }; =20 static const struct mtk_gate_regs ifr2_cg_regs =3D { @@ -630,50 +647,24 @@ static const struct mtk_gate_regs ifr6_cg_regs =3D { .sta_ofs =3D 0xd8, }; =20 -#define GATE_IFR2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFRX(_id, _name, _parent, _shift, _regs) \ + GATE_MTK(_id, _name, _parent, _regs, _shift, \ + &mtk_clk_gate_ops_setclr) =20 -#define GATE_IFR3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR2(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs) =20 -#define GATE_IFR4(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr4_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR3(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs) =20 -#define GATE_IFR5(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr5_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR4(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs) =20 -#define GATE_IFR6(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr6_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR5(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs) + +#define GATE_IFR6(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs) =20 static const struct mtk_gate ifr_clks[] =3D { /* IFR2 */ @@ -752,33 +743,16 @@ static const struct mtk_gate ifr_clks[] =3D { GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11), }; =20 -static const struct mtk_simple_gate peri_clks[] =3D { - { CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 }, +static const struct mtk_gate_regs peri_cg_regs =3D { + .set_ofs =3D 0x20c, + .clr_ofs =3D 0x20c, + .sta_ofs =3D 0x20c, }; =20 -static int -clk_mt8365_register_mtk_simple_gates(struct device *dev, void __iomem *bas= e, - struct clk_hw_onecell_data *clk_data, - const struct mtk_simple_gate *gates, - unsigned int num_gates) -{ - unsigned int i; - - for (i =3D 0; i !=3D num_gates; ++i) { - const struct mtk_simple_gate *gate =3D &gates[i]; - struct clk_hw *hw; - - hw =3D devm_clk_hw_register_gate(dev, gate->name, gate->parent, 0, - base + gate->reg, gate->shift, - gate->gate_flags, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - clk_data->hws[gate->id] =3D hw; - } - - return 0; -} +static const struct mtk_gate peri_clks[] =3D { + GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31, + &mtk_clk_gate_ops_no_setclr), +}; =20 static int clk_mt8365_top_probe(struct platform_device *pdev) { @@ -840,17 +814,18 @@ static int clk_mt8365_top_probe(struct platform_devic= e *pdev) if (ret) goto unregister_composites; =20 - ret =3D clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, - top_clk_gates, - ARRAY_SIZE(top_clk_gates)); + ret =3D mtk_clk_register_gates(&pdev->dev, node, top_clk_gates, + ARRAY_SIZE(top_clk_gates), clk_data); if (ret) goto unregister_dividers; =20 ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (ret) - goto unregister_dividers; + goto unregister_gates; =20 return 0; +unregister_gates: + mtk_clk_unregister_gates(top_clk_gates, ARRAY_SIZE(top_clk_gates), clk_da= ta); unregister_dividers: mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data); @@ -915,9 +890,9 @@ static int clk_mt8365_peri_probe(struct platform_device= *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, - peri_clks, - ARRAY_SIZE(peri_clks)); + + ret =3D mtk_clk_register_gates(&pdev->dev, node, peri_clks, + ARRAY_SIZE(peri_clks), clk_data); if (ret) return ret; =20 --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 145CCC64EC7 for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1676905294; bh=wSnbyMfzTT5K6YQ9dYPu4W/7E3SDjJAMqKz1KNLxFIE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DB1RFeZFeQEjR5dEwqpSb/ZCovcsAqUD/oVzScFIGJ1zJ0cu74zw7qMsKhPDYvKdd 3zi2BeWB8fiTR+ldeV4h1KFnjiqd7gcle0md0jtFYJ/xV9IAilfF2LNfcJEOw/i9re XFH/GIUXATFvDm7B70NQTRtpzwYfWqkw1+DgXU1tOn5VI0OFIp0oCgaX+MbMQ7G46Q CN/YFnIba/0hMEzz9tkKI2cvgDgZRgJ3bBSzOqjLaTcM/tF+2vqMRTmX5aRzNjqO/N GukLgBTJtPkItWhtzBIYZ8lDJMIkNQ91JLM606zSBefZ4sOyRaFGNutkWU1sDOq7w5 KJfskYjjD6mPA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 13/55] clk: mediatek: mt8365: Join top_misc_mux_gates and top_misc_muxes arrays Date: Mon, 20 Feb 2023 16:00:29 +0100 Message-Id: <20230220150111.77897-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating this driver to the simple probe mechanism, join the audio gates to the top_misc_mux_gates array of mtk_composite clocks in one top_misc_muxes array. While at it, since the `apll_i2s0_parents` array is for all i2s clocks, rename that to `apll_i2s_parents`. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8365.c | 46 ++++++++++--------------------- 1 file changed, 14 insertions(+), 32 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index 85fe7586a69b..fef6c653c9ce 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -384,25 +384,23 @@ static const char * const mbist_diag_parents[] =3D { "univpll2_d8" }; =20 -static const char * const apll_i2s0_parents[] =3D { +static const char * const apll_i2s_parents[] =3D { "aud_1_sel", "aud_2_sel" }; =20 -static struct mtk_composite top_misc_mux_gates[] =3D { +static struct mtk_composite top_misc_muxes[] =3D { /* CLK_CFG_11 */ MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents, 0x0ec, 0, 2, 7), -}; - -static struct mt8365_clk_audio_mux top_misc_muxes[] =3D { - { CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", 11}, - { CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", 12}, - { CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", 13}, - { CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", 14}, - { CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", 15}, - { CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", 16}, - { CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", 17}, + /* Audio MUX */ + MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11,= 1), + MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12,= 1), + MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13,= 1), + MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14,= 1), + MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320,= 15, 1), + MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 1= 6, 1), + MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 1= 7, 1), }; =20 #define CLK_CFG_UPDATE 0x004 @@ -787,28 +785,12 @@ static int clk_mt8365_top_probe(struct platform_devic= e *pdev) if (ret) goto unregister_factors; =20 - ret =3D mtk_clk_register_composites(&pdev->dev, top_misc_mux_gates, - ARRAY_SIZE(top_misc_mux_gates), base, + ret =3D mtk_clk_register_composites(&pdev->dev, top_misc_muxes, + ARRAY_SIZE(top_misc_muxes), base, &mt8365_clk_lock, clk_data); if (ret) goto unregister_muxes; =20 - for (i =3D 0; i !=3D ARRAY_SIZE(top_misc_muxes); ++i) { - struct mt8365_clk_audio_mux *mux =3D &top_misc_muxes[i]; - struct clk_hw *hw; - - hw =3D devm_clk_hw_register_mux(dev, mux->name, apll_i2s0_parents, - ARRAY_SIZE(apll_i2s0_parents), - CLK_SET_RATE_PARENT, base + 0x320, - mux->shift, 1, 0, NULL); - if (IS_ERR(hw)) { - ret =3D PTR_ERR(hw); - goto unregister_composites; - } - - clk_data->hws[mux->id] =3D hw; - } - ret =3D mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8365_clk_lock, clk_data); if (ret) @@ -830,8 +812,8 @@ static int clk_mt8365_top_probe(struct platform_device = *pdev) mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data); unregister_composites: - mtk_clk_unregister_composites(top_misc_mux_gates, - ARRAY_SIZE(top_misc_mux_gates), clk_data); + mtk_clk_unregister_composites(top_misc_muxes, + ARRAY_SIZE(top_misc_muxes), clk_data); unregister_muxes: mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); unregister_factors: --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 876A8C64EC4 for ; Mon, 20 Feb 2023 15:02:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232853AbjBTPCg (ORCPT ); Mon, 20 Feb 2023 10:02:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231925AbjBTPCH (ORCPT ); Mon, 20 Feb 2023 10:02:07 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CF8120049; Mon, 20 Feb 2023 07:01:37 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B02AA6602168; Mon, 20 Feb 2023 15:01:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905295; bh=vIDbGzqkfmXmHDtcPk514occm+SjmUa+rP1OcAWimTk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GqCY7QVjfLtl/X8E7KJ6+LyCn+rO2D+RBWCDO10FB82tB6plPynE9XjZC8DsbTftt l4lRW15Wru87dD0VyBgk/49SP0XIAIWQhPjEk4kZsQIuy7gFV5GSK8QEuHC7cFXKld uORta9eGJiX2WpxRYi7fyMNqlNJMH3ahXDagMyGrVieG8Iyv3vFfLS0cdCvIZBVu/+ 4OeFZNAsJOGD8Cd2yjBbwtot0PnjZ64V0OEpi/EYZs+8p6cat6V54jlIVvZ6VcAIwP uiNe+yFu8Fe0bDB0EkrP9ng3BYrCzHr8FXXiocNAKEP/QwDEKr7H3IGBSMdNC0a7Bf WSkyVy7FY2fhg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 14/55] clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}() Date: Mon, 20 Feb 2023 16:00:30 +0100 Message-Id: <20230220150111.77897-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All clocks in this driver are supported by the common simple probe mechanism and it's now possible to migrate to it. While at it, also switch to using the module_platform_driver() macro. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8365.c | 241 +++++------------------------- 1 file changed, 37 insertions(+), 204 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index fef6c653c9ce..208cdc157918 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -752,220 +752,53 @@ static const struct mtk_gate peri_clks[] =3D { &mtk_clk_gate_ops_no_setclr), }; =20 -static int clk_mt8365_top_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - int ret; - int i; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_fixed_clks(top_fixed_clks, - ARRAY_SIZE(top_fixed_clks), clk_data); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - if (ret) - goto unregister_fixed_clks; - - ret =3D mtk_clk_register_muxes(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), node, - &mt8365_clk_lock, clk_data); - if (ret) - goto unregister_factors; - - ret =3D mtk_clk_register_composites(&pdev->dev, top_misc_muxes, - ARRAY_SIZE(top_misc_muxes), base, - &mt8365_clk_lock, clk_data); - if (ret) - goto unregister_muxes; - - ret =3D mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt8365_clk_lock, clk_data); - if (ret) - goto unregister_composites; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, top_clk_gates, - ARRAY_SIZE(top_clk_gates), clk_data); - if (ret) - goto unregister_dividers; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_gates; - - return 0; -unregister_gates: - mtk_clk_unregister_gates(top_clk_gates, ARRAY_SIZE(top_clk_gates), clk_da= ta); -unregister_dividers: - mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - clk_data); -unregister_composites: - mtk_clk_unregister_composites(top_misc_muxes, - ARRAY_SIZE(top_misc_muxes), clk_data); -unregister_muxes: - mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(top_fixed_clks, - ARRAY_SIZE(top_fixed_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - - return ret; -} - -static int clk_mt8365_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int ret; - - clk_data =3D mtk_alloc_clk_data(CLK_IFR_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_gates(&pdev->dev, node, ifr_clks, - ARRAY_SIZE(ifr_clks), clk_data); - if (ret) - goto free_clk_data; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_gates; - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(ifr_clks, ARRAY_SIZE(ifr_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - - return ret; -} - -static int clk_mt8365_peri_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device *dev =3D &pdev->dev; - struct device_node *node =3D dev->of_node; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_PERI_NR_CLK); - if (!clk_data) - return -ENOMEM; - - - ret =3D mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - return ret; -} - -static int clk_mt8365_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt8365_clk_lock, clk_data); - if (ret) - goto free_clk_data; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_composites; +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clk_gates, + .num_clks =3D ARRAY_SIZE(top_clk_gates), + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_muxes), + .composite_clks =3D top_misc_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_misc_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt8365_clk_lock, +}; =20 - return 0; +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D ifr_clks, + .num_clks =3D ARRAY_SIZE(ifr_clks), +}; =20 -unregister_composites: - mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), - clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc peri_desc =3D { + .clks =3D peri_clks, + .num_clks =3D ARRAY_SIZE(peri_clks), +}; =20 - return ret; -} +static const struct mtk_clk_desc mcu_desc =3D { + .composite_clks =3D mcu_muxes, + .num_composite_clks =3D ARRAY_SIZE(mcu_muxes), + .clk_lock =3D &mt8365_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt8365[] =3D { - { - .compatible =3D "mediatek,mt8365-topckgen", - .data =3D clk_mt8365_top_probe, - }, { - .compatible =3D "mediatek,mt8365-infracfg", - .data =3D clk_mt8365_infra_probe, - }, { - .compatible =3D "mediatek,mt8365-pericfg", - .data =3D clk_mt8365_peri_probe, - }, { - .compatible =3D "mediatek,mt8365-mcucfg", - .data =3D clk_mt8365_mcu_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt8365_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int ret; - - clk_probe =3D of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - ret =3D clk_probe(pdev); - if (ret) - dev_err(&pdev->dev, - "%s: could not register clock provider: %d\n", - pdev->name, ret); - - return ret; -} + { .compatible =3D "mediatek,mt8365-topckgen", .data =3D &topck_desc }, + { .compatible =3D "mediatek,mt8365-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt8365-pericfg", .data =3D &peri_desc }, + { .compatible =3D "mediatek,mt8365-mcucfg", .data =3D &mcu_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt8365_drv =3D { - .probe =3D clk_mt8365_probe, .driver =3D { .name =3D "clk-mt8365", .of_match_table =3D of_match_clk_mt8365, }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; - -static int __init clk_mt8365_init(void) -{ - return platform_driver_register(&clk_mt8365_drv); -} -arch_initcall(clk_mt8365_init); +module_platform_driver(clk_mt8365_drv); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63796C05027 for ; Mon, 20 Feb 2023 15:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232048AbjBTPCj (ORCPT ); Mon, 20 Feb 2023 10:02:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232535AbjBTPCM (ORCPT ); Mon, 20 Feb 2023 10:02:12 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A22881F906; Mon, 20 Feb 2023 07:01:38 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1B1096602169; Mon, 20 Feb 2023 15:01:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905297; bh=WzEqGHU4wPUr1FqrefeofMY/SCcyC9H6YipRxwjIHNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BZ5OYTuE+06IEwgRFotwJignqeZ3saIJQIthprb74Jelecz4jbQAGQYg9T6GKqlt2 vK1fRtHU5tyFEIpOQNcWVwC7A+CB5bWKfawSAemo7qwmZ0xalC46EwwOz9Yoal9Qec dFQOnwpyRNy4CwpWy6ooQZM36AshbcEQjVfqEKpi0868oiDfeCO2HyDxH1XAYcF5fQ I8YGyH7W58/J86Qbue7XQ0O9amcMbERo/HFvNNfSEL9R2yxciglQx6+MnPVQzK63Av k86AjS7R65iIecAzWTADOt4oJj3hhgXzUpB7EVDD2OWPNideKqAKblqSuMsKL5Jcu4 /BABTw3wITvJA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 15/55] clk: mediatek: mt8167: Compress GATE_TOPx macros Date: Mon, 20 Feb 2023 16:00:31 +0100 Message-Id: <20230220150111.77897-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros. No functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8167.c | 80 +++++++------------------------ 1 file changed, 16 insertions(+), 64 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index 91669ebafaf9..12384da4002d 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -736,77 +736,29 @@ static const struct mtk_gate_regs top5_cg_regs =3D { .sta_ofs =3D 0x44, }; =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP0_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP0_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP2_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP4_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top4_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP4_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP5(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top5_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 static const struct mtk_gate top_clks[] __initconst =3D { /* TOP0 */ --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1897C64EC7 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905298; bh=7C3i+oOEZJ/IUAE8+KpF0czCWtxEusasNCvRPK6iFeI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i1GXvrIZi84sZNNylsSW+6QEsdmzBUOh34ifS8n0UvrguPI/ylN2zRiSgsxjUkrsw bIY7gpZoS77OQTP73jNB9dMw2Oq4PhB5U4UUyNfe7p4inxlAnpninZ/GUzct0F+QIc y/MS23HrmZoHz0nJ9QadZy8TvvAiUY8ms/Rrsa2Y82/DqYhHGnMqAbOG+hYMpcDtdG 05jo//BTI9jog173RWMa+APtgTjLaBktaIqDEhBFfJYSEOc2Ptczmc5J2D/i0bnquh +H7y2l7q1rpIzSS8Mhjzn1rY4pqhPJ6Uma8OHlZe9d5fX8RfG1U2ctfxOvo0zOuFLr Oc1kaNkbRHRxQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 16/55] clk: mediatek: mt8167: Move apmixedsys as platform_driver in new file Date: Mon, 20 Feb 2023 16:00:32 +0100 Message-Id: <20230220150111.77897-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating all other MT8167 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, also migrate away from the legacy CLK_OF_DECLARE and convert this clock driver to be a platform_driver instead. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 143 +++++++++++++++++++ drivers/clk/mediatek/clk-mt8167.c | 102 ------------- 3 files changed, 144 insertions(+), 103 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8167-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index b004a47026d4..7fda42b76533 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -62,7 +62,7 @@ obj-$(CONFIG_COMMON_CLK_MT7986) +=3D clk-mt7986-topckgen.o obj-$(CONFIG_COMMON_CLK_MT7986) +=3D clk-mt7986-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) +=3D clk-mt7986-eth.o obj-$(CONFIG_COMMON_CLK_MT8135) +=3D clk-mt8135.o -obj-$(CONFIG_COMMON_CLK_MT8167) +=3D clk-mt8167.o +obj-$(CONFIG_COMMON_CLK_MT8167) +=3D clk-mt8167.o clk-mt8167-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) +=3D clk-mt8167-aud.o obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) +=3D clk-mt8167-img.o obj-$(CONFIG_COMMON_CLK_MT8167_MFGCFG) +=3D clk-mt8167-mfgcfg.o diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8167-apmixedsys.c new file mode 100644 index 000000000000..ebd90365be5f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS + * Copyright (c) 2023 Collabora, Ltd. + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-mtk.h" + +static DEFINE_SPINLOCK(mt8167_apmixed_clk_lock); + +#define MT8167_PLL_FMAX (2500UL * MHZ) + +#define CON0_MT8167_RST_BAR BIT(27) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D CON0_MT8167_RST_BAR, \ + .fmax =3D MT8167_PLL_FMAX, \ + .pcwbits =3D _pcwbits, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .div_table =3D _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + NULL) + +static const struct mtk_pll_div_table mmpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8167_PLL_FMAX }, + { .div =3D 1, .freq =3D 1000000000 }, + { .div =3D 2, .freq =3D 604500000 }, + { .div =3D 3, .freq =3D 253500000 }, + { .div =3D 4, .freq =3D 126750000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data plls[] =3D { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, + 21, 0x0104, 24, 0, 0x0104, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, + HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, + HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, + 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), + PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, + 31, 0x0180, 1, 0x0194, 0x0184, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, + 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0, + 21, 0x01C4, 24, 0, 0x01C4, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0, + 21, 0x01E4, 24, 0, 0x01E4, 0), +}; + +#define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .div_reg =3D _reg, \ + .div_shift =3D _shift, \ + .div_width =3D _width, \ + .clk_divider_flags =3D _flag, \ +} + +static const struct mtk_clk_divider adj_divs[] =3D { + DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", + 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), +}; + +static int clk_mt8167_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_devm_alloc_clk_data(dev, MT8167_CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret =3D mtk_clk_register_dividers(adj_divs, ARRAY_SIZE(adj_divs), base, + &mt8167_apmixed_clk_lock, clk_data); + if (ret) + goto unregister_plls; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_dividers; + + return 0; + +unregister_dividers: + mtk_clk_unregister_dividers(adj_divs, ARRAY_SIZE(adj_divs), clk_data); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8167_apmixed[] =3D { + { .compatible =3D "mediatek,mt8167-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8167_apmixed_drv =3D { + .probe =3D clk_mt8167_apmixed_probe, + .driver =3D { + .name =3D "clk-mt8167-apmixed", + .of_match_table =3D of_match_clk_mt8167_apmixed, + }, +}; +builtin_platform_driver(clk_mt8167_apmixed_drv) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index 12384da4002d..a4ffdac6d94d 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -14,7 +14,6 @@ =20 #include "clk-gate.h" #include "clk-mtk.h" -#include "clk-pll.h" =20 #include =20 @@ -685,21 +684,6 @@ static const struct mtk_clk_divider top_adj_divs[] =3D= { 0x0078, 0, 8), }; =20 -#define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .div_reg =3D _reg, \ - .div_shift =3D _shift, \ - .div_width =3D _width, \ - .clk_divider_flags =3D _flag, \ -} - -static const struct mtk_clk_divider apmixed_adj_divs[] =3D { - DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", - 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), -}; - static const struct mtk_gate_regs top0_cg_regs =3D { .set_ofs =3D 0x50, .clr_ofs =3D 0x80, @@ -929,89 +913,3 @@ static void __init mtk_infracfg_init(struct device_nod= e *node) __func__, r); } CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init= ); - -#define MT8167_PLL_FMAX (2500UL * MHZ) - -#define CON0_MT8167_RST_BAR BIT(27) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift, _div_table) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D CON0_MT8167_RST_BAR, \ - .fmax =3D MT8167_PLL_FMAX, \ - .pcwbits =3D _pcwbits, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .div_table =3D _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - NULL) - -static const struct mtk_pll_div_table mmpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8167_PLL_FMAX }, - { .div =3D 1, .freq =3D 1000000000 }, - { .div =3D 2, .freq =3D 604500000 }, - { .div =3D 3, .freq =3D 253500000 }, - { .div =3D 4, .freq =3D 126750000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, - 21, 0x0104, 24, 0, 0x0104, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, - HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, - HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, - 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), - PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, - 31, 0x0180, 1, 0x0194, 0x0184, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, - 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0, - 21, 0x01C4, 24, 0, 0x01C4, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0, - 21, 0x01E4, 24, 0, 0x01E4, 0), -}; - -static void __init mtk_apmixedsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data =3D mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK); - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs), - base, &mt8167_clk_lock, clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - -} -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys", - mtk_apmixedsys_init); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C522C636CC for ; Mon, 20 Feb 2023 15:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231666AbjBTPCq (ORCPT ); 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b=W98NDvXY1WP8lI3VzOSUr06/wzu2UB3yTj3Mqlas+oaOoW2YK8/FhHfIgUrdtM2QF phR1AwPo1bylIFaW8wxO2oMSBH7Ld5fttede7Pn5fU7M22vcFAKj3yKHGHldpmmQqg qEkkpd22xQPTwtGfGijkaYoYF9cqzhJY2rr2Hm9KaEK2o3cfMwLlKLVXi41aF3VQD7 1ED8asyBRkZO2NjCE4c3huLq1PnOEXvo8jZqgbL1DifbWX+uFUI1nI51N1GY0crehD yHyYPmhXSfOtW53eex2pxX6IoiXAGqPDJW9zAJTno7hbS+22nUNMS2XjYh6cswFIUZ 7p2NCP8LjFBCg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 17/55] clk: mediatek: mt8167: Remove __initconst annotation from arrays Date: Mon, 20 Feb 2023 16:00:33 +0100 Message-Id: <20230220150111.77897-18-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for converting the MT8167 clock drivers to be proper platform_driver(s), drop the __initconst annotation from all of the clock arrays since they will be used not only during init but also during runtime. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8167-aud.c | 2 +- drivers/clk/mediatek/clk-mt8167-img.c | 2 +- drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 2 +- drivers/clk/mediatek/clk-mt8167-vdec.c | 2 +- drivers/clk/mediatek/clk-mt8167.c | 100 +++++++++++------------ 5 files changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index f6bea6e9e6a4..2d890a440863 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -32,7 +32,7 @@ static const struct mtk_gate_regs aud_cg_regs =3D { .ops =3D &mtk_clk_gate_ops_no_setclr, \ } =20 -static const struct mtk_gate aud_clks[] __initconst =3D { +static const struct mtk_gate aud_clks[] =3D { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6), GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8), diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index 77db13b177fc..23950186ee02 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -32,7 +32,7 @@ static const struct mtk_gate_regs img_cg_regs =3D { .ops =3D &mtk_clk_gate_ops_setclr, \ } =20 -static const struct mtk_gate img_clks[] __initconst =3D { +static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0), GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "smi_mm", 5), GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "smi_mm", 6), diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 3c23591b02f7..40b2d45f3fe3 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -32,7 +32,7 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .ops =3D &mtk_clk_gate_ops_setclr, \ } =20 -static const struct mtk_gate mfg_clks[] __initconst =3D { +static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0), GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1), GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2), diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index 759e5791599f..905529789a7c 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -47,7 +47,7 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .ops =3D &mtk_clk_gate_ops_setclr_inv, \ } =20 -static const struct mtk_gate vdec_clks[] __initconst =3D { +static const struct mtk_gate vdec_clks[] =3D { /* VDEC0 */ GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0), /* VDEC1 */ diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index a4ffdac6d94d..f604add9b546 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -19,7 +19,7 @@ =20 static DEFINE_SPINLOCK(mt8167_clk_lock); =20 -static const struct mtk_fixed_clk fixed_clks[] __initconst =3D { +static const struct mtk_fixed_clk fixed_clks[] =3D { FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000), FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000), @@ -28,7 +28,7 @@ static const struct mtk_fixed_clk fixed_clks[] __initcons= t =3D { FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000= ), }; =20 -static const struct mtk_fixed_factor top_divs[] __initconst =3D { +static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2), FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), @@ -84,22 +84,22 @@ static const struct mtk_fixed_factor top_divs[] __initc= onst =3D { FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2), }; =20 -static const char * const uart0_parents[] __initconst =3D { +static const char * const uart0_parents[] =3D { "clk26m_ck", "univpll_d24" }; =20 -static const char * const gfmux_emi1x_parents[] __initconst =3D { +static const char * const gfmux_emi1x_parents[] =3D { "clk26m_ck", "dmpll_ck" }; =20 -static const char * const emi_ddrphy_parents[] __initconst =3D { +static const char * const emi_ddrphy_parents[] =3D { "gfmux_emi1x_sel", "gfmux_emi1x_sel" }; =20 -static const char * const ahb_infra_parents[] __initconst =3D { +static const char * const ahb_infra_parents[] =3D { "clk_null", "clk26m_ck", "mainpll_d11", @@ -115,7 +115,7 @@ static const char * const ahb_infra_parents[] __initcon= st =3D { "mainpll_d10" }; =20 -static const char * const csw_mux_mfg_parents[] __initconst =3D { +static const char * const csw_mux_mfg_parents[] =3D { "clk_null", "clk_null", "univpll_d3", @@ -126,7 +126,7 @@ static const char * const csw_mux_mfg_parents[] __initc= onst =3D { "mmpll380m" }; =20 -static const char * const msdc0_parents[] __initconst =3D { +static const char * const msdc0_parents[] =3D { "clk26m_ck", "univpll_d6", "mainpll_d8", @@ -137,7 +137,7 @@ static const char * const msdc0_parents[] __initconst = =3D { "mmpll_d2" }; =20 -static const char * const camtg_mm_parents[] __initconst =3D { +static const char * const camtg_mm_parents[] =3D { "clk_null", "clk26m_ck", "usb_phy48m_ck", @@ -145,17 +145,17 @@ static const char * const camtg_mm_parents[] __initco= nst =3D { "univpll_d6" }; =20 -static const char * const pwm_mm_parents[] __initconst =3D { +static const char * const pwm_mm_parents[] =3D { "clk26m_ck", "univpll_d12" }; =20 -static const char * const uart1_parents[] __initconst =3D { +static const char * const uart1_parents[] =3D { "clk26m_ck", "univpll_d24" }; =20 -static const char * const msdc1_parents[] __initconst =3D { +static const char * const msdc1_parents[] =3D { "clk26m_ck", "univpll_d6", "mainpll_d8", @@ -166,24 +166,24 @@ static const char * const msdc1_parents[] __initconst= =3D { "mmpll_d2" }; =20 -static const char * const spm_52m_parents[] __initconst =3D { +static const char * const spm_52m_parents[] =3D { "clk26m_ck", "univpll_d24" }; =20 -static const char * const pmicspi_parents[] __initconst =3D { +static const char * const pmicspi_parents[] =3D { "univpll_d20", "usb_phy48m_ck", "univpll_d16", "clk26m_ck" }; =20 -static const char * const qaxi_aud26m_parents[] __initconst =3D { +static const char * const qaxi_aud26m_parents[] =3D { "clk26m_ck", "ahb_infra_sel" }; =20 -static const char * const aud_intbus_parents[] __initconst =3D { +static const char * const aud_intbus_parents[] =3D { "clk_null", "clk26m_ck", "mainpll_d22", @@ -191,7 +191,7 @@ static const char * const aud_intbus_parents[] __initco= nst =3D { "mainpll_d11" }; =20 -static const char * const nfi2x_pad_parents[] __initconst =3D { +static const char * const nfi2x_pad_parents[] =3D { "clk_null", "clk_null", "clk_null", @@ -279,12 +279,12 @@ static const char * const nfi2x_pad_parents[] __initc= onst =3D { "mainpll_d5" }; =20 -static const char * const nfi1x_pad_parents[] __initconst =3D { +static const char * const nfi1x_pad_parents[] =3D { "ahb_infra_sel", "nfi1x_ck" }; =20 -static const char * const mfg_mm_parents[] __initconst =3D { +static const char * const mfg_mm_parents[] =3D { "clk_null", "clk_null", "clk_null", @@ -324,12 +324,12 @@ static const char * const mfg_mm_parents[] __initcons= t =3D { "mainpll_d14" }; =20 -static const char * const ddrphycfg_parents[] __initconst =3D { +static const char * const ddrphycfg_parents[] =3D { "clk26m_ck", "mainpll_d16" }; =20 -static const char * const smi_mm_parents[] __initconst =3D { +static const char * const smi_mm_parents[] =3D { "clk26m_ck", "clk_null", "clk_null", @@ -345,7 +345,7 @@ static const char * const smi_mm_parents[] __initconst = =3D { "mainpll_d14" }; =20 -static const char * const usb_78m_parents[] __initconst =3D { +static const char * const usb_78m_parents[] =3D { "clk_null", "clk26m_ck", "univpll_d16", @@ -353,7 +353,7 @@ static const char * const usb_78m_parents[] __initconst= =3D { "mainpll_d20" }; =20 -static const char * const scam_mm_parents[] __initconst =3D { +static const char * const scam_mm_parents[] =3D { "clk_null", "clk26m_ck", "mainpll_d14", @@ -361,7 +361,7 @@ static const char * const scam_mm_parents[] __initconst= =3D { "mainpll_d12" }; =20 -static const char * const spinor_parents[] __initconst =3D { +static const char * const spinor_parents[] =3D { "clk26m_d2", "clk26m_ck", "mainpll_d40", @@ -372,7 +372,7 @@ static const char * const spinor_parents[] __initconst = =3D { "univpll_d12" }; =20 -static const char * const msdc2_parents[] __initconst =3D { +static const char * const msdc2_parents[] =3D { "clk26m_ck", "univpll_d6", "mainpll_d8", @@ -383,7 +383,7 @@ static const char * const msdc2_parents[] __initconst = =3D { "mmpll_d2" }; =20 -static const char * const eth_parents[] __initconst =3D { +static const char * const eth_parents[] =3D { "clk26m_ck", "mainpll_d40", "univpll_d24", @@ -391,7 +391,7 @@ static const char * const eth_parents[] __initconst =3D= { "mainpll_d20" }; =20 -static const char * const vdec_mm_parents[] __initconst =3D { +static const char * const vdec_mm_parents[] =3D { "clk26m_ck", "univpll_d4", "mainpll_d4", @@ -400,7 +400,7 @@ static const char * const vdec_mm_parents[] __initconst= =3D { "mainpll_d6" }; =20 -static const char * const dpi0_mm_parents[] __initconst =3D { +static const char * const dpi0_mm_parents[] =3D { "clk26m_ck", "lvdspll_ck", "lvdspll_d2", @@ -408,7 +408,7 @@ static const char * const dpi0_mm_parents[] __initconst= =3D { "lvdspll_d8" }; =20 -static const char * const dpi1_mm_parents[] __initconst =3D { +static const char * const dpi1_mm_parents[] =3D { "clk26m_ck", "tvdpll_d2", "tvdpll_d4", @@ -416,85 +416,85 @@ static const char * const dpi1_mm_parents[] __initcon= st =3D { "tvdpll_d16" }; =20 -static const char * const axi_mfg_in_parents[] __initconst =3D { +static const char * const axi_mfg_in_parents[] =3D { "clk26m_ck", "mainpll_d11", "univpll_d24", "mmpll380m" }; =20 -static const char * const slow_mfg_parents[] __initconst =3D { +static const char * const slow_mfg_parents[] =3D { "clk26m_ck", "univpll_d12", "univpll_d24" }; =20 -static const char * const aud1_parents[] __initconst =3D { +static const char * const aud1_parents[] =3D { "clk26m_ck", "apll1_ck" }; =20 -static const char * const aud2_parents[] __initconst =3D { +static const char * const aud2_parents[] =3D { "clk26m_ck", "apll2_ck" }; =20 -static const char * const aud_engen1_parents[] __initconst =3D { +static const char * const aud_engen1_parents[] =3D { "clk26m_ck", "rg_apll1_d2_en", "rg_apll1_d4_en", "rg_apll1_d8_en" }; =20 -static const char * const aud_engen2_parents[] __initconst =3D { +static const char * const aud_engen2_parents[] =3D { "clk26m_ck", "rg_apll2_d2_en", "rg_apll2_d4_en", "rg_apll2_d8_en" }; =20 -static const char * const i2c_parents[] __initconst =3D { +static const char * const i2c_parents[] =3D { "clk26m_ck", "univpll_d20", "univpll_d16", "univpll_d12" }; =20 -static const char * const aud_i2s0_m_parents[] __initconst =3D { +static const char * const aud_i2s0_m_parents[] =3D { "rg_aud1", "rg_aud2" }; =20 -static const char * const pwm_parents[] __initconst =3D { +static const char * const pwm_parents[] =3D { "clk26m_ck", "univpll_d12" }; =20 -static const char * const spi_parents[] __initconst =3D { +static const char * const spi_parents[] =3D { "clk26m_ck", "univpll_d12", "univpll_d8", "univpll_d6" }; =20 -static const char * const aud_spdifin_parents[] __initconst =3D { +static const char * const aud_spdifin_parents[] =3D { "clk26m_ck", "univpll_d2" }; =20 -static const char * const uart2_parents[] __initconst =3D { +static const char * const uart2_parents[] =3D { "clk26m_ck", "univpll_d24" }; =20 -static const char * const bsi_parents[] __initconst =3D { +static const char * const bsi_parents[] =3D { "clk26m_ck", "mainpll_d10", "mainpll_d12", "mainpll_d20" }; =20 -static const char * const dbg_atclk_parents[] __initconst =3D { +static const char * const dbg_atclk_parents[] =3D { "clk_null", "clk26m_ck", "mainpll_d5", @@ -502,7 +502,7 @@ static const char * const dbg_atclk_parents[] __initcon= st =3D { "univpll_d5" }; =20 -static const char * const csw_nfiecc_parents[] __initconst =3D { +static const char * const csw_nfiecc_parents[] =3D { "clk_null", "mainpll_d7", "mainpll_d6", @@ -510,7 +510,7 @@ static const char * const csw_nfiecc_parents[] __initco= nst =3D { "mainpll_d5" }; =20 -static const char * const nfiecc_parents[] __initconst =3D { +static const char * const nfiecc_parents[] =3D { "clk_null", "nfi2x_pad_sel", "mainpll_d4", @@ -624,24 +624,24 @@ static struct mtk_composite top_muxes[] __initdata = =3D { 0x07c, 13, 3), }; =20 -static const char * const ifr_mux1_parents[] __initconst =3D { +static const char * const ifr_mux1_parents[] =3D { "clk26m_ck", "armpll", "univpll", "mainpll_d2" }; =20 -static const char * const ifr_eth_25m_parents[] __initconst =3D { +static const char * const ifr_eth_25m_parents[] =3D { "eth_d2_ck", "rg_eth" }; =20 -static const char * const ifr_i2c0_parents[] __initconst =3D { +static const char * const ifr_i2c0_parents[] =3D { "ahb_infra_d2", "rg_i2c" }; =20 -static const struct mtk_composite ifr_muxes[] __initconst =3D { +static const struct mtk_composite ifr_muxes[] =3D { MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000, 2, 2), MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080, @@ -744,7 +744,7 @@ static const struct mtk_gate_regs top5_cg_regs =3D { #define GATE_TOP5(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 -static const struct mtk_gate top_clks[] __initconst =3D { +static const struct mtk_gate top_clks[] =3D { /* TOP0 */ GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0), GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1), --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B005C636CC for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1676905301; bh=EfVsMWfXlW7Nej60ln7osuE3Ve3dZUUh6F8ZrFmhc+I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l4DsH9DLq87thUDkRa6HQNLjN5LuiCqEBLsDcR+bS6hTRybaXotNZ0E6RmKmZAWM2 S5+JB6h30kFjUiESUylUP15U6K6+joXK/+kMVplH4p9ZSPa0Vbv3AR9GWh8VxGgdlF nlCJptmC/SfpNWdzcxPK0B7siZJJZdOyqO/FwDzsqCbAcp6FWJZhY7pfyo++KNHC6f pJce+69tUMuyj+htqlN7qzKlSfwhVvZykpWXCyxy+7SvcZIOCOvUy4HKUAkSWykLdy zcJDlTaeQaEu+j2XgXQM5LH0IzOD3LCKjE1p+9AMH1KxIurNp8a3XsFtOXEakmvFyq XO9m6YGjAnyWQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 18/55] clk: mediatek: mt8167: Convert to mtk_clk_simple_{probe,remove}() Date: Mon, 20 Feb 2023 16:00:34 +0100 Message-Id: <20230220150111.77897-19-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert topckgen and infracfg clock drivers to use the common mtk_clk_simple_probe() mechanism and change this from the old "static" CLK_OF_DECLARE to be a platform driver, allowing it to eventually be built as a module. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8167-aud.c | 31 +++++---- drivers/clk/mediatek/clk-mt8167-img.c | 32 ++++----- drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 32 ++++----- drivers/clk/mediatek/clk-mt8167-vdec.c | 33 ++++----- drivers/clk/mediatek/clk-mt8167.c | 86 +++++++++--------------- 5 files changed, 101 insertions(+), 113 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index 2d890a440863..eec9de190cb6 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -48,19 +48,22 @@ static const struct mtk_gate aud_clks[] =3D { GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), }; =20 -static void __init mtk_audsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR_CLK); - - mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_da= ta); +static const struct mtk_clk_desc aud_desc =3D { + .clks =3D aud_clks, + .num_clks =3D ARRAY_SIZE(aud_clks), +}; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_audsys[] =3D { + { .compatible =3D "mediatek,mt8167-audsys", .data =3D &aud_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init); +static struct platform_driver clk_mt8167_audsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-audsys", + .of_match_table =3D of_match_clk_mt8167_audsys, + }, +}; +module_platform_driver(clk_mt8167_audsys_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index 23950186ee02..5cd51d894d32 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -41,20 +41,22 @@ static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9), }; =20 -static void __init mtk_imgsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_IMG_NR_CLK); - - mtk_clk_register_gates(NULL, node, img_clks, ARRAY_SIZE(img_clks), clk_da= ta); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc img_desc =3D { + .clks =3D img_clks, + .num_clks =3D ARRAY_SIZE(img_clks), +}; =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_imgsys[] =3D { + { .compatible =3D "mediatek,mt8167-imgsys", .data =3D &img_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8167-imgsys", mtk_imgsys_init); +static struct platform_driver clk_mt8167_imgsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-imgsys", + .of_match_table =3D of_match_clk_mt8167_imgsys, + }, +}; +module_platform_driver(clk_mt8167_imgsys_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 40b2d45f3fe3..2cf88d5d245d 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -39,20 +39,22 @@ static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3), }; =20 -static void __init mtk_mfgcfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_MFG_NR_CLK); - - mtk_clk_register_gates(NULL, node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_da= ta); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc mfg_desc =3D { + .clks =3D mfg_clks, + .num_clks =3D ARRAY_SIZE(mfg_clks), +}; =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_mfgcfg[] =3D { + { .compatible =3D "mediatek,mt8167-mfgcfg", .data =3D &mfg_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init); +static struct platform_driver clk_mt8167_mfgcfg_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-mfgcfg", + .of_match_table =3D of_match_clk_mt8167_mfgcfg, + }, +}; +module_platform_driver(clk_mt8167_mfgcfg_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index 905529789a7c..c3e2253a57d7 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -54,21 +54,22 @@ static const struct mtk_gate vdec_clks[] =3D { GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0), }; =20 -static void __init mtk_vdecsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_VDEC_NR_CLK); - - mtk_clk_register_gates(NULL, node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc vdec_desc =3D { + .clks =3D vdec_clks, + .num_clks =3D ARRAY_SIZE(vdec_clks), +}; =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_vdec[] =3D { + { .compatible =3D "mediatek,mt8167-vdecsys", .data =3D &vdec_desc }, + { /* sentinel */ } +}; =20 -} -CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init); +static struct platform_driver clk_mt8167_vdec_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167-vdecsys", + .of_match_table =3D of_match_clk_mt8167_vdec, + }, +}; +module_platform_driver(clk_mt8167_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index f604add9b546..507e1ebe3ba8 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "clk-gate.h" #include "clk-mtk.h" @@ -857,59 +858,38 @@ static const struct mtk_gate top_clks[] =3D { GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), }; =20 -static void __init mtk_topckgen_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data =3D mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK); +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .fixed_clks =3D fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt8167_clk_lock, +}; =20 - mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), - clk_data); - mtk_clk_register_gates(NULL, node, top_clks, ARRAY_SIZE(top_clks), clk_da= ta); +static const struct mtk_clk_desc infra_desc =3D { + .composite_clks =3D ifr_muxes, + .num_composite_clks =3D ARRAY_SIZE(ifr_muxes), + .clk_lock =3D &mt8167_clk_lock, +}; =20 - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(NULL, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8167_clk_lock, clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt8167_clk_lock, clk_data); +static const struct of_device_id of_match_clk_mt8167[] =3D { + { .compatible =3D "mediatek,mt8167-topckgen", .data =3D &topck_desc }, + { .compatible =3D "mediatek,mt8167-infracfg", .data =3D &infra_desc }, + { /* sentinel */ } +}; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init= ); - -static void __init mtk_infracfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data =3D mtk_alloc_clk_data(CLK_IFR_NR_CLK); - - mtk_clk_register_composites(NULL, ifr_muxes, - ARRAY_SIZE(ifr_muxes), base, - &mt8167_clk_lock, clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init= ); +static struct platform_driver clk_mt8167_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8167", + .of_match_table =3D of_match_clk_mt8167, + }, +}; +module_platform_driver(clk_mt8167_drv); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13A26C05027 for ; Mon, 20 Feb 2023 15:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbjBTPDC (ORCPT ); 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b=CqW6AQX5AnESJP3kLV94hk+8ndW+DP8zmtzuac2eEWZEVPt4E8/Nj0rT+pMvFaL+m JPZUZVbEfDhpRFC3pgQQkSxUJfQpE8EpPavpmhQv1aF6X7pTyLBjZLtsDph5daMaUw 6WSm6gbUMnToPdy2xrUW1H7eChja0/Zq4Y6JhQsVKU1k9tRxe8U8X2RRNi6cBTfj/h zQD06suYHPp6G9qjpDBzu2X2LQbu6RdEmJFIXNBS1bbXnucJxAPfKb9Nr17z1h5xJz Y8h8ORIR3Fc4ZTmVbPlEXzkxrcIzjmGeE+7zVxBM6PLYRdIvJQqZvIuiE2LOUZCQSq 2FYoNLZRSyxCQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 19/55] clk: mediatek: mt8183: Move apmixedsys clock driver to its own file Date: Mon, 20 Feb 2023 16:00:35 +0100 Message-Id: <20230220150111.77897-20-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating all other mt8183 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it and fix some indentation issues in the PLLs table. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 193 +++++++++++++++++++ drivers/clk/mediatek/clk-mt8183.c | 153 --------------- 3 files changed, 194 insertions(+), 154 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8183-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 7fda42b76533..10038a0f25e0 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -74,7 +74,7 @@ obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) +=3D clk-mt8173-im= g.o obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) +=3D clk-mt8173-mm.o obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) +=3D clk-mt8173-vdecsys.o obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) +=3D clk-mt8173-vencsys.o -obj-$(CONFIG_COMMON_CLK_MT8183) +=3D clk-mt8183.o +obj-$(CONFIG_COMMON_CLK_MT8183) +=3D clk-mt8183.o clk-mt8183-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) +=3D clk-mt8183-audio.o obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) +=3D clk-mt8183-cam.o obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) +=3D clk-mt8183-img.o diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8183-apmixedsys.c new file mode 100644 index 000000000000..e66e90163bb4 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Weiyi Lu + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +static const struct mtk_gate_regs apmixed_cg_regs =3D { + .set_ofs =3D 0x20, + .clr_ofs =3D 0x20, + .sta_ofs =3D 0x20, +}; + +#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) + +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) + +/* + * CRITICAL CLOCK: + * apmixed_appll26m is the toppest clock gate of all PLLs. + */ +static const struct mtk_gate apmixed_clks[] =3D { + /* AUDIO0 */ + GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", "f_f26m_ck", 4), + GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", + "f_f26m_ck", 5, CLK_IS_CRITICAL), + GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck", 6), + GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", "f_f26m_ck", 7), + GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", "f_f26m_ck", 8), + GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", "f_f26m_ck", 9), + GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck", 11= ), + GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", "f_f26m_ck", 13= ), + GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", "f_f26m_ck"= , 14), + GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck", 16= ), + GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", "f_f26m_ck", 17= ), +}; + +#define MT8183_PLL_FMAX (3800UL * MHZ) +#define MT8183_PLL_FMIN (1500UL * MHZ) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcw_chg_reg, _div_table) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D _rst_bar_mask, \ + .fmax =3D MT8183_PLL_FMAX, \ + .fmin =3D MT8183_PLL_FMIN, \ + .pcwbits =3D _pcwbits, \ + .pcwibits =3D _pcwibits, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .tuner_en_reg =3D _tuner_en_reg, \ + .tuner_en_bit =3D _tuner_en_bit, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .pcw_chg_reg =3D _pcw_chg_reg, \ + .div_table =3D _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcw_chg_reg) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcw_chg_reg, NULL) + +static const struct mtk_pll_div_table armpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8183_PLL_FMAX }, + { .div =3D 1, .freq =3D 1500 * MHZ }, + { .div =3D 2, .freq =3D 750 * MHZ }, + { .div =3D 3, .freq =3D 375 * MHZ }, + { .div =3D 4, .freq =3D 187500000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_div_table mfgpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8183_PLL_FMAX }, + { .div =3D 1, .freq =3D 1600 * MHZ }, + { .div =3D 2, .freq =3D 800 * MHZ }, + { .div =3D 3, .freq =3D 400 * MHZ }, + { .div =3D 4, .freq =3D 200 * MHZ }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data plls[] =3D { + PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0, + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, + 0x0204, 0, 0, armpll_div_table), + PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0, + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, + 0x0214, 0, 0, armpll_div_table), + PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0, + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, + 0x0294, 0, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, + 0x0224, 0, 0), + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, + 0x0234, 0, 0), + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0, + 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, + mfgpll_div_table), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0, + 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0, + 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0, + HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, + 0x0274, 0, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0, + 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0, + 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), +}; + +static int clk_mt8183_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (ret) + goto unregister_plls; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_gates; + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8183_apmixed[] =3D { + { .compatible =3D "mediatek,mt8183-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8183_apmixed_drv =3D { + .probe =3D clk_mt8183_apmixed_probe, + .driver =3D { + .name =3D "clk-mt8183-apmixed", + .of_match_table =3D of_match_clk_mt8183_apmixed, + }, +}; +builtin_platform_driver(clk_mt8183_apmixed_drv) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 722d913f0b4d..84b970f33316 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -14,7 +14,6 @@ #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-pll.h" =20 #include =20 @@ -941,140 +940,6 @@ static const struct mtk_gate peri_clks[] =3D { GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), }; =20 -static const struct mtk_gate_regs apmixed_cg_regs =3D { - .set_ofs =3D 0x20, - .clr_ofs =3D 0x20, - .sta_ofs =3D 0x20, -}; - -#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ - GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ - _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) - -#define GATE_APMIXED(_id, _name, _parent, _shift) \ - GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) - -/* - * CRITICAL CLOCK: - * apmixed_appll26m is the toppest clock gate of all PLLs. - */ -static const struct mtk_gate apmixed_clks[] =3D { - /* AUDIO0 */ - GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", - "f_f26m_ck", 4), - GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", - "f_f26m_ck", 5, CLK_IS_CRITICAL), - GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", - "f_f26m_ck", 6), - GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", - "f_f26m_ck", 7), - GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", - "f_f26m_ck", 8), - GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", - "f_f26m_ck", 9), - GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", - "f_f26m_ck", 11), - GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", - "f_f26m_ck", 13), - GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", - "f_f26m_ck", 14), - GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", - "f_f26m_ck", 16), - GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", - "f_f26m_ck", 17), -}; - -#define MT8183_PLL_FMAX (3800UL * MHZ) -#define MT8183_PLL_FMIN (1500UL * MHZ) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ - _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _pcw_chg_reg, _div_table) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D _rst_bar_mask, \ - .fmax =3D MT8183_PLL_FMAX, \ - .fmin =3D MT8183_PLL_FMIN, \ - .pcwbits =3D _pcwbits, \ - .pcwibits =3D _pcwibits, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .tuner_en_reg =3D _tuner_en_reg, \ - .tuner_en_bit =3D _tuner_en_bit, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .pcw_chg_reg =3D _pcw_chg_reg, \ - .div_table =3D _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ - _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _pcw_chg_reg) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ - _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _pcw_chg_reg, NULL) - -static const struct mtk_pll_div_table armpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8183_PLL_FMAX }, - { .div =3D 1, .freq =3D 1500 * MHZ }, - { .div =3D 2, .freq =3D 750 * MHZ }, - { .div =3D 3, .freq =3D 375 * MHZ }, - { .div =3D 4, .freq =3D 187500000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table mfgpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8183_PLL_FMAX }, - { .div =3D 1, .freq =3D 1600 * MHZ }, - { .div =3D 2, .freq =3D 800 * MHZ }, - { .div =3D 3, .freq =3D 400 * MHZ }, - { .div =3D 4, .freq =3D 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] =3D { - PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0, - HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, - 0x0204, 0, 0, armpll_div_table), - PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0, - HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, - 0x0214, 0, 0, armpll_div_table), - PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0, - HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, - 0x0294, 0, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, - 0x0224, 0, 0), - PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, - 0x0234, 0, 0), - PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0, - 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, - mfgpll_div_table), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0, - 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0, - 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0, - HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, - 0x0274, 0, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0, - 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0, - 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), -}; - static u16 infra_rst_ofs[] =3D { INFRA_RST0_SET_OFFSET, INFRA_RST1_SET_OFFSET, @@ -1088,21 +953,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D= { .rst_bank_nr =3D ARRAY_SIZE(infra_rst_ofs), }; =20 -static int clk_mt8183_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static struct clk_hw_onecell_data *top_clk_data; =20 static void clk_mt8183_top_init_early(struct device_node *node) @@ -1204,9 +1054,6 @@ static int clk_mt8183_mcu_probe(struct platform_devic= e *pdev) =20 static const struct of_device_id of_match_clk_mt8183[] =3D { { - .compatible =3D "mediatek,mt8183-apmixedsys", - .data =3D clk_mt8183_apmixed_probe, - }, { .compatible =3D "mediatek,mt8183-topckgen", .data =3D clk_mt8183_top_probe, }, { --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6561C64EC7 for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1676905304; bh=Hau1Wx+OHy+fMZU1Q9fDwGbEbJv+icuSKhMTvm0iYCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gAYJC0eMw6qhoBfu7G/jMcrdNzWWR7MQF/vdKDyimZUtogQd3ZaoGBqwNL3ffNSUw +6zaVAGECSodRzvAol8Ne4qvtH1/hkd5ziUyy5vju67ESKDG5UzdaY1ezKKDpGCCpk AnAAwLdQ4DvKKCXM4uaSG15IoHZqSO/w0AWotaAK7EbEjGY7R8haw60D0M2O7F054/ S/uaKXrt4c5n9O7PjYfYSKKFdb82pRZIkjV+iuwDpa72q2HsqI8e86Yo56K/f/AePM L8LroC6xCmaco8k+kNep+i9U1kJ3iB2u9cKkITuuCrXVlAqVxdd7VM/CKfTM4ZOolz vxaDM+pw4OmNg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 20/55] clk: mediatek: mt8183: Compress clocks arrays entries where possible Date: Mon, 20 Feb 2023 16:00:36 +0100 Message-Id: <20230220150111.77897-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Increase human readability and decrease number of lines by compressing the clock array entries where possible, to a maximum of ~95 columns. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8183.c | 450 ++++++++++-------------------- 1 file changed, 150 insertions(+), 300 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 84b970f33316..9da193d7782d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -448,138 +448,97 @@ static const char * const aud_2_parents[] =3D { static const struct mtk_mux top_muxes[] =3D { /* CLK_CFG_0 */ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", - axi_parents, 0x40, - 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), + axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", - mm_parents, 0x40, - 0x44, 0x48, 8, 3, 15, 0x004, 1), + mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", - img_parents, 0x40, - 0x44, 0x48, 16, 3, 23, 0x004, 2), + img_parents, 0x40, 0x44, 0x48, 16, 3, 23, 0x004, 2), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", - cam_parents, 0x40, - 0x44, 0x48, 24, 4, 31, 0x004, 3), + cam_parents, 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 3), /* CLK_CFG_1 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", - dsp_parents, 0x50, - 0x54, 0x58, 0, 4, 7, 0x004, 4), + dsp_parents, 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 4), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", - dsp1_parents, 0x50, - 0x54, 0x58, 8, 4, 15, 0x004, 5), + dsp1_parents, 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 5), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", - dsp2_parents, 0x50, - 0x54, 0x58, 16, 4, 23, 0x004, 6), + dsp2_parents, 0x50, 0x54, 0x58, 16, 4, 23, 0x004, 6), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", - ipu_if_parents, 0x50, - 0x54, 0x58, 24, 4, 31, 0x004, 7), + ipu_if_parents, 0x50, 0x54, 0x58, 24, 4, 31, 0x004, 7), /* CLK_CFG_2 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", - mfg_parents, 0x60, - 0x64, 0x68, 0, 2, 7, 0x004, 8), + mfg_parents, 0x60, 0x64, 0x68, 0, 2, 7, 0x004, 8), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", - f52m_mfg_parents, 0x60, - 0x64, 0x68, 8, 2, 15, 0x004, 9), + f52m_mfg_parents, 0x60, 0x64, 0x68, 8, 2, 15, 0x004, 9), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", - camtg_parents, 0x60, - 0x64, 0x68, 16, 3, 23, 0x004, 10), + camtg_parents, 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 10), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", - camtg2_parents, 0x60, - 0x64, 0x68, 24, 3, 31, 0x004, 11), + camtg2_parents, 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 11), /* CLK_CFG_3 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", - camtg3_parents, 0x70, - 0x74, 0x78, 0, 3, 7, 0x004, 12), + camtg3_parents, 0x70, 0x74, 0x78, 0, 3, 7, 0x004, 12), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", - camtg4_parents, 0x70, - 0x74, 0x78, 8, 3, 15, 0x004, 13), + camtg4_parents, 0x70, 0x74, 0x78, 8, 3, 15, 0x004, 13), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", - uart_parents, 0x70, - 0x74, 0x78, 16, 1, 23, 0x004, 14), + uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", - spi_parents, 0x70, - 0x74, 0x78, 24, 2, 31, 0x004, 15), + spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15), /* CLK_CFG_4 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", - msdc50_hclk_parents, 0x80, - 0x84, 0x88, 0, 2, 7, 0x004, 16), + msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", - msdc50_0_parents, 0x80, - 0x84, 0x88, 8, 3, 15, 0x004, 17), + msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", - msdc30_1_parents, 0x80, - 0x84, 0x88, 16, 3, 23, 0x004, 18), + msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", - msdc30_2_parents, 0x80, - 0x84, 0x88, 24, 3, 31, 0x004, 19), + msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19), /* CLK_CFG_5 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", - audio_parents, 0x90, - 0x94, 0x98, 0, 2, 7, 0x004, 20), + audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", - aud_intbus_parents, 0x90, - 0x94, 0x98, 8, 2, 15, 0x004, 21), + aud_intbus_parents, 0x90, 0x94, 0x98, 8, 2, 15, 0x004, 21), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", - pmicspi_parents, 0x90, - 0x94, 0x98, 16, 2, 23, 0x004, 22), + pmicspi_parents, 0x90, 0x94, 0x98, 16, 2, 23, 0x004, 22), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", - fpwrap_ulposc_parents, 0x90, - 0x94, 0x98, 24, 2, 31, 0x004, 23), + fpwrap_ulposc_parents, 0x90, 0x94, 0x98, 24, 2, 31, 0x004, 23), /* CLK_CFG_6 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", - atb_parents, 0xa0, - 0xa4, 0xa8, 0, 2, 7, 0x004, 24), + atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", - dpi0_parents, 0xa0, - 0xa4, 0xa8, 16, 4, 23, 0x004, 26), + dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", - scam_parents, 0xa0, - 0xa4, 0xa8, 24, 1, 31, 0x004, 27), + scam_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x004, 27), /* CLK_CFG_7 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", - disppwm_parents, 0xb0, - 0xb4, 0xb8, 0, 3, 7, 0x004, 28), + disppwm_parents, 0xb0, 0xb4, 0xb8, 0, 3, 7, 0x004, 28), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", - usb_top_parents, 0xb0, - 0xb4, 0xb8, 8, 2, 15, 0x004, 29), + usb_top_parents, 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x004, 29), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", - ssusb_top_xhci_parents, 0xb0, - 0xb4, 0xb8, 16, 2, 23, 0x004, 30), + ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", - spm_parents, 0xb0, - 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), + spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), /* CLK_CFG_8 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", - i2c_parents, 0xc0, - 0xc4, 0xc8, 0, 2, 7, 0x008, 1), + i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", - scp_parents, 0xc0, - 0xc4, 0xc8, 8, 3, 15, 0x008, 2), + scp_parents, 0xc0, 0xc4, 0xc8, 8, 3, 15, 0x008, 2), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", - seninf_parents, 0xc0, - 0xc4, 0xc8, 16, 2, 23, 0x008, 3), + seninf_parents, 0xc0, 0xc4, 0xc8, 16, 2, 23, 0x008, 3), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", - dxcc_parents, 0xc0, - 0xc4, 0xc8, 24, 2, 31, 0x008, 4), + dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4), /* CLK_CFG_9 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", - aud_engen1_parents, 0xd0, - 0xd4, 0xd8, 0, 2, 7, 0x008, 5), + aud_engen1_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 5), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", - aud_engen2_parents, 0xd0, - 0xd4, 0xd8, 8, 2, 15, 0x008, 6), + aud_engen2_parents, 0xd0, 0xd4, 0xd8, 8, 2, 15, 0x008, 6), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", - faes_ufsfde_parents, 0xd0, - 0xd4, 0xd8, 16, 3, 23, 0x008, 7), + faes_ufsfde_parents, 0xd0, 0xd4, 0xd8, 16, 3, 23, 0x008, 7), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", - fufs_parents, 0xd0, - 0xd4, 0xd8, 24, 2, 31, 0x008, 8), + fufs_parents, 0xd0, 0xd4, 0xd8, 24, 2, 31, 0x008, 8), /* CLK_CFG_10 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", - aud_1_parents, 0xe0, - 0xe4, 0xe8, 0, 1, 7, 0x008, 9), + aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", - aud_2_parents, 0xe0, - 0xe4, 0xe8, 8, 1, 15, 0x008, 10), + aud_2_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x008, 10), }; =20 static const char * const apll_i2s0_parents[] =3D { @@ -643,30 +602,18 @@ static struct mtk_composite mcu_muxes[] =3D { }; =20 static struct mtk_composite top_aud_comp[] =3D { - MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, - 0x320, 8, 1), - MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, - 0x320, 9, 1), - MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, - 0x320, 10, 1), - MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, - 0x320, 11, 1), - MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, - 0x320, 12, 1), - MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, - 0x328, 20, 1), - DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", - 0x320, 2, 0x324, 8, 0), - DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", - 0x320, 3, 0x324, 8, 8), - DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", - 0x320, 4, 0x324, 8, 16), - DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", - 0x320, 5, 0x324, 8, 24), - DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", - 0x320, 6, 0x328, 8, 0), - DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", - 0x320, 7, 0x328, 8, 8), + MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 0x320, 8, = 1), + MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 0x320, 9, = 1), + MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 0x320, 10,= 1), + MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 0x320, 11,= 1), + MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 0x320, 12,= 1), + MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 0x328, 20,= 1), + DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0= x324, 8, 0), + DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0= x324, 8, 8), + DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 0x320, 4, 0= x324, 8, 16), + DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 0x320, 5, 0= x324, 8, 24), + DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0= x328, 8, 0), + DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 7, 0x3= 28, 8, 8), }; =20 static const struct mtk_gate_regs top_cg_regs =3D { @@ -727,203 +674,106 @@ static const struct mtk_gate_regs infra3_cg_regs = =3D { =20 static const struct mtk_gate infra_clks[] =3D { /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", - "axi_sel", 0), - GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", - "axi_sel", 1), - GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", - "axi_sel", 2), - GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", - "axi_sel", 3), - GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", - "scp_sel", 4), - GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", - "f_f26m_ck", 5), - GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", - "axi_sel", 6), - GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", - "axi_sel", 8), - GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", - "axi_sel", 9), - GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", - "axi_sel", 10), - GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", - "i2c_sel", 11), - GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", - "i2c_sel", 12), - GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", - "i2c_sel", 13), - GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", - "i2c_sel", 14), - GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", - "axi_sel", 15), - GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", - "i2c_sel", 16), - GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", - "i2c_sel", 17), - GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", - "i2c_sel", 18), - GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", - "i2c_sel", 19), - GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", - "i2c_sel", 21), - GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", - "uart_sel", 22), - GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", - "uart_sel", 23), - GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", - "uart_sel", 24), - GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", - "uart_sel", 25), - GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", - "axi_sel", 27), - GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", - "axi_sel", 28), - GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", - "axi_sel", 31), + GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), + GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "axi_sel", 1), + GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "axi_sel", 2), + GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "axi_sel", 3), + GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", "scp_sel", 4), + GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "f_f26m_ck", 5), + GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), + GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8), + GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), + GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), + GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), + GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", "i2c_sel", 12), + GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), + GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), + GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), + GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "i2c_sel", 16), + GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "i2c_sel", 17), + GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "i2c_sel", 18), + GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "i2c_sel", 19), + GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "i2c_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), + GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), + GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), + GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), + GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), + GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", "axi_sel", 28), + GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", - "spi_sel", 1), - GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", - "msdc50_hclk_sel", 2), - GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", - "axi_sel", 4), - GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", - "axi_sel", 5), - GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", - "msdc50_0_sel", 6), - GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", - "f_f26m_ck", 7), - GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", - "axi_sel", 8), - GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", - "axi_sel", 9), - GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", - "f_f26m_ck", 10), - GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", - "axi_sel", 11), - GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", - "axi_sel", 12), - GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", - "axi_sel", 13), - GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", - "f_f26m_ck", 14), - GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", - "msdc30_1_sel", 16), - GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", - "msdc30_2_sel", 17), - GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", - "axi_sel", 18), - GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", - "axi_sel", 19), - GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", - "axi_sel", 20), - GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", - "axi_sel", 23), - GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", - "axi_sel", 24), - GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", - "axi_sel", 25), - GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", - "axi_sel", 26), - GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", - "dxcc_sel", 27), - GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", - "dxcc_sel", 28), - GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", - "axi_sel", 30), - GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", - "f_f26m_ck", 31), + GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), + GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_hclk_sel", 2), + GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "axi_sel", 4), + GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "axi_sel", 5), + GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", "msdc50_0_sel", 6), + GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", "f_f26m_ck", 7), + GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), + GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), + GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "f_f26m_ck", 10), + GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), + GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), + GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), + GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "f_f26m_ck", 14), + GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", "msdc30_1_sel", 16), + GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", "msdc30_2_sel", 17), + GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", "axi_sel", 18), + GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19), + GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), + GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), + GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), + GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), + GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), + GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 2= 7), + GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), + GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", "axi_sel", 30), + GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "f_f26m_ck", 31), /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", - "f_f26m_ck", 0), - GATE_INFRA2(CLK_INFRA_USB, "infra_usb", - "usb_top_sel", 1), - GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", - "axi_sel", 2), - GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", - "axi_sel", 3), - GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", - "f_f26m_ck", 4), - GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", - "spi_sel", 6), - GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", - "i2c_sel", 7), - GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", - "f_f26m_ck", 8), - GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", - "spi_sel", 9), - GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", - "spi_sel", 10), - GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", - "ssusb_top_xhci_sel", 11), - GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", - "fufs_sel", 12), - GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", - "fufs_sel", 13), - GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", - "axi_sel", 14), - GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", - "axi_sel", 16), - GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", - "i2c_sel", 18), - GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", - "i2c_sel", 19), - GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", - "i2c_sel", 20), - GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", - "i2c_sel", 21), - GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", - "i2c_sel", 22), - GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", - "i2c_sel", 23), - GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", - "i2c_sel", 24), - GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", - "spi_sel", 25), - GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", - "spi_sel", 26), - GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", - "axi_sel", 27), - GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", - "fufs_sel", 28), - GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", - "faes_ufsfde_sel", 29), - GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", - "fufs_sel", 30), + GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "f_f26m_ck", 0), + GATE_INFRA2(CLK_INFRA_USB, "infra_usb", "usb_top_sel", 1), + GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", "axi_sel", 2), + GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", "axi_sel", 3), + GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", "f_f26m_ck"= , 4), + GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), + GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), + GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", "f_f26m_ck"= , 8), + GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), + GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), + GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", "ssusb_top_xhci_sel= ", 11), + GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12), + GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel"= , 13), + GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14), + GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), + GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), + GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), + GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), + GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), + GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), + GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), + GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), + GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), + GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), + GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", "axi_sel", 27), + GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "fufs_sel", 28), + GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "faes_ufsfde_sel", = 29), + GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "fufs_sel", 30), /* INFRA3 */ - GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", - "msdc50_0_sel", 0), - GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", - "msdc50_0_sel", 1), - GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", - "msdc50_0_sel", 2), - GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", - "axi_sel", 5), - GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", - "i2c_sel", 6), - GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", - "msdc50_hclk_sel", 7), - GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", - "msdc50_hclk_sel", 8), - GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", - "axi_sel", 16), - GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", - "axi_sel", 17), - GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", - "axi_sel", 18), - GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", - "axi_sel", 19), - GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", - "f_f26m_ck", 20), - GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", - "axi_sel", 21), - GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", - "i2c_sel", 22), - GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", - "i2c_sel", 23), - GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", - "msdc50_0_sel", 24), + GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), + GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), + GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), + GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), + GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), + GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7), + GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_hclk_sel", 8), + GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), + GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), + GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), + GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), + GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "f_f26m_ck", 20), + GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", "axi_sel", 21), + GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), + GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), + GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), }; =20 static const struct mtk_gate_regs peri_cg_regs =3D { --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 274C6C05027 for ; Mon, 20 Feb 2023 15:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232365AbjBTPDQ (ORCPT ); Mon, 20 Feb 2023 10:03:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232850AbjBTPCg (ORCPT ); Mon, 20 Feb 2023 10:02:36 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 170E620555; Mon, 20 Feb 2023 07:01:46 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 75B106602180; Mon, 20 Feb 2023 15:01:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905305; bh=Ods8oGr6IDmSNHDIC/Lgn1UYdRZOCHtvm+3+FE6PlSE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KJf4mjkZ/YdAjbn7hOZAb5hmFeO5RGWr6PQwDv75G+Gu+9ny86NU+MwweIX79YEQv XYYh525aapaXnnaeqwHDhVNbqygmjCq1vv/BVzEQ4imqfjbg3QNLZhMYYmkksr09kk NPjL5KMMPmYAJ86eyyipHT5yQdUhp5F44Up7NNAyrHFjmWL6nX47sWbHd8xt0/eXtj ozNqlYmBRr3PVJ9u5HtbT7f7/JtICUpDTKWosel8NsoN+tmLY6VM1EkDcW1CDgH7MX +OI0S69O44QsqQgGOorYc3k4rfv9TCxpvNPANwtCZheR4q71Af2YwnwKGuOyZe4BW3 2uKtBOTbTzSuQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 21/55] clk: mediatek: mt8183: Convert all remaining clocks to common probe Date: Mon, 20 Feb 2023 16:00:37 +0100 Message-Id: <20230220150111.77897-22-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch to mtk_clk_simple_{probe,remove}() for infracfg and topckgen clocks on MT8183 to allow full module build for clock drivers. Differently from other MediaTek clock drivers, it was necessary to change the name of the `clk13m` clock, as that is already declared in the SoC's devicetree as a "fixed-factor-clock" (with the same name) and redeclaring it here would obviously fail to register the entire clock controller; this clock wasn't dropped only to retain compatibility with older devicetrees As a note, the `clk13m` clock is not mentioned in any parent names array(s) as the correct one (csw_f26m_d2) is already used in place of that. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8183.c | 166 ++++++------------------------ 1 file changed, 34 insertions(+), 132 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 9da193d7782d..02176ee97cd2 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -25,11 +25,14 @@ static const struct mtk_fixed_clk top_fixed_clks[] =3D { FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), }; =20 -static const struct mtk_fixed_factor top_early_divs[] =3D { - FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), -}; - +/* + * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M + * valid, but renamed from "clk13m" (defined as fixed clock in the new + * devicetrees) to "clk26m_d2", satisfying the older clock assignments. + * This means that on new devicetrees "clk26m_d2" is unused. + */ static const struct mtk_fixed_factor top_divs[] =3D { + FACTOR(CLK_TOP_CLK13M, "clk26m_d2", "clk26m", 1, 2), FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0), FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0), @@ -803,26 +806,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(infra_rst_ofs), }; =20 -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt8183_top_init_early(struct device_node *node) -{ - int i; - - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - for (i =3D 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); -} - -CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", - clk_mt8183_top_init_early); - /* Register mux notifier for MFG mux */ static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) { @@ -845,134 +828,53 @@ static int clk_mt8183_reg_mfg_mux_notifier(struct de= vice *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } =20 -static int clk_mt8183_top_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct device_node *node =3D pdev->dev.of_node; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - - mtk_clk_register_muxes(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), node, - &mt8183_clk_lock, top_clk_data); - - mtk_clk_register_composites(&pdev->dev, top_aud_comp, - ARRAY_SIZE(top_aud_comp), base, - &mt8183_clk_lock, top_clk_data); - - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), top_clk_data); - - ret =3D clk_mt8183_reg_mfg_mux_notifier(&pdev->dev, - top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); - if (ret) - return ret; - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - top_clk_data); -} - -static int clk_mt8183_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); - - mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt8183_clk_lock, clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static const struct of_device_id of_match_clk_mt8183[] =3D { - { - .compatible =3D "mediatek,mt8183-topckgen", - .data =3D clk_mt8183_top_probe, - }, { - .compatible =3D "mediatek,mt8183-mcucfg", - .data =3D clk_mt8183_mcu_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt8183_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe =3D of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r =3D clk_probe(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static const struct mtk_clk_desc infra_desc =3D { .clks =3D infra_clks, .num_clks =3D ARRAY_SIZE(infra_clks), .rst_desc =3D &clk_rst_desc, }; =20 +static const struct mtk_clk_desc mcu_desc =3D { + .composite_clks =3D mcu_muxes, + .num_composite_clks =3D ARRAY_SIZE(mcu_muxes), + .clk_lock =3D &mt8183_clk_lock, +}; + static const struct mtk_clk_desc peri_desc =3D { .clks =3D peri_clks, .num_clks =3D ARRAY_SIZE(peri_clks), }; =20 -static const struct of_device_id of_match_clk_mt8183_simple[] =3D { +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_muxes), + .composite_clks =3D top_aud_comp, + .num_composite_clks =3D ARRAY_SIZE(top_aud_comp), + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .clk_lock =3D &mt8183_clk_lock, + .clk_notifier_func =3D clk_mt8183_reg_mfg_mux_notifier, + .mfg_clk_idx =3D CLK_TOP_MUX_MFG, +}; + +static const struct of_device_id of_match_clk_mt8183[] =3D { { .compatible =3D "mediatek,mt8183-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt8183-mcucfg", .data =3D &mcu_desc }, { .compatible =3D "mediatek,mt8183-pericfg", .data =3D &peri_desc, }, + { .compatible =3D "mediatek,mt8183-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 -static struct platform_driver clk_mt8183_simple_drv =3D { +static struct platform_driver clk_mt8183_drv =3D { .probe =3D mtk_clk_simple_probe, .remove =3D mtk_clk_simple_remove, - .driver =3D { - .name =3D "clk-mt8183-simple", - .of_match_table =3D of_match_clk_mt8183_simple, - }, -}; - -static struct platform_driver clk_mt8183_drv =3D { - .probe =3D clk_mt8183_probe, .driver =3D { .name =3D "clk-mt8183", .of_match_table =3D of_match_clk_mt8183, }, }; - -static int __init clk_mt8183_init(void) -{ - int ret =3D platform_driver_register(&clk_mt8183_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt8183_simple_drv); -} - -arch_initcall(clk_mt8183_init); +module_platform_driver(clk_mt8183_drv) --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 380DAC636CC for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905307; bh=OrbmHKPT4S5tKnKiFgQbhyo4lMcbxfeglgNt8q9Xn5U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hIdk53KBj4h2Lt6fJJzvDS/5dOvSxcTAGB97pFoqHH0vwMk/pOLsgpk8jn6NMTez+ 2Xtt5YTqKHbOtNsoNuies+uKtrIZCry3Oq4OD6Ca3hwSx/4+w+fxnA90KRlin49n63 F4kizVn1LEODtkcB9pt3lq0ZAu6nW0v4HQj349fGIkq+z/bNMoxWO9s18Y3ExkYEE/ 7F6QyFG+WPSHX7gZxXcM1mD64G5EFv8eYCsG4oXIvZoO7vmZeKqge4fieApORMIjha xfPB78ie3RD4BW2r9fzeHO/H389bqiNVQq9g9yVHI7H3XenKNTkNNci5Q5BE/VofLI f5rdRE9e5xZyg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 22/55] clk: mediatek: Consistently use GATE_MTK() macro Date: Mon, 20 Feb 2023 16:00:38 +0100 Message-Id: <20230220150111.77897-23-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All the various MediaTek clock drivers are, in a way or another, redefining the GATE_MTK() macro with different names: while some are doing that by actually using GATE_MTK(), others are copying it entirely (hence, entirely redefining it). Change all clock drivers to always and consistently use this macro. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2701-aud.c | 40 +++-------- drivers/clk/mediatek/clk-mt2701-bdp.c | 20 ++---- drivers/clk/mediatek/clk-mt2701-eth.c | 10 +-- drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +-- drivers/clk/mediatek/clk-mt2701-hif.c | 10 +-- drivers/clk/mediatek/clk-mt2701-img.c | 10 +-- drivers/clk/mediatek/clk-mt2701-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt2701-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt2701.c | 40 +++-------- drivers/clk/mediatek/clk-mt2712-bdp.c | 10 +-- drivers/clk/mediatek/clk-mt2712-img.c | 10 +-- drivers/clk/mediatek/clk-mt2712-jpgdec.c | 10 +-- drivers/clk/mediatek/clk-mt2712-mfg.c | 10 +-- drivers/clk/mediatek/clk-mt2712-mm.c | 30 ++------ drivers/clk/mediatek/clk-mt2712-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt2712-venc.c | 10 +-- drivers/clk/mediatek/clk-mt2712.c | 66 ++++-------------- drivers/clk/mediatek/clk-mt6765-audio.c | 20 ++---- drivers/clk/mediatek/clk-mt6765-cam.c | 10 +-- drivers/clk/mediatek/clk-mt6765-img.c | 10 +-- drivers/clk/mediatek/clk-mt6765-mipi0a.c | 10 +-- drivers/clk/mediatek/clk-mt6765-mm.c | 10 +-- drivers/clk/mediatek/clk-mt6765-vcodec.c | 10 +-- drivers/clk/mediatek/clk-mt6765.c | 80 +++++----------------- drivers/clk/mediatek/clk-mt6797-img.c | 10 +-- drivers/clk/mediatek/clk-mt6797-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt6797-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt6797-venc.c | 10 +-- drivers/clk/mediatek/clk-mt6797.c | 42 ++++-------- drivers/clk/mediatek/clk-mt7622-aud.c | 40 +++-------- drivers/clk/mediatek/clk-mt7622-eth.c | 20 ++---- drivers/clk/mediatek/clk-mt7622-hif.c | 22 ++---- drivers/clk/mediatek/clk-mt7622.c | 61 ++++------------- drivers/clk/mediatek/clk-mt7629-eth.c | 20 ++---- drivers/clk/mediatek/clk-mt7629-hif.c | 22 ++---- drivers/clk/mediatek/clk-mt7629.c | 40 +++-------- drivers/clk/mediatek/clk-mt7986-eth.c | 24 ++----- drivers/clk/mediatek/clk-mt7986-infracfg.c | 24 ++----- drivers/clk/mediatek/clk-mt8135.c | 30 ++------ drivers/clk/mediatek/clk-mt8167-aud.c | 11 +-- drivers/clk/mediatek/clk-mt8167-img.c | 10 +-- drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 10 +-- drivers/clk/mediatek/clk-mt8167-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt8167-vdec.c | 20 ++---- drivers/clk/mediatek/clk-mt8173-mm.c | 20 ++---- drivers/clk/mediatek/clk-mt8516-aud.c | 10 +-- drivers/clk/mediatek/clk-mt8516.c | 60 ++++------------ 47 files changed, 223 insertions(+), 839 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index 1a32d8b7db84..21f7cc106bbe 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -15,41 +15,17 @@ =20 #include =20 -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 static const struct mtk_gate_regs audio0_cg_regs =3D { .set_ofs =3D 0x0, diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/c= lk-mt2701-bdp.c index 435ed4819d56..b0f057207945 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs bdp1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_BDP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &bdp0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_BDP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_BDP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &bdp1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_BDP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate bdp_clks[] =3D { GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index f3cb78e7f6e9..4c830ebdd761 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs eth_cg_regs =3D { .sta_ofs =3D 0x0030, }; =20 -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate eth_clks[] =3D { GATE_DUMMY(CLK_DUMMY, "eth_dummy"), diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 499a170ba5f9..ae094046890a 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -16,14 +16,8 @@ =20 #include =20 -#define GATE_G3D(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &g3d_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_G3D(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &g3d_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate_regs g3d_cg_regs =3D { .sta_ofs =3D 0x0, diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index d5465d782993..3583bd1240d5 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs hif_cg_regs =3D { .sta_ofs =3D 0x0030, }; =20 -#define GATE_HIF(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &hif_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_HIF(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate hif_clks[] =3D { GATE_DUMMY(CLK_DUMMY, "hif_dummy"), diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/c= lk-mt2701-img.c index 7e53deb7f990..eb172473f075 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0000, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/cl= k-mt2701-mm.c index a8d94ca0eefd..993d904d619f 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs disp1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_DISP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &disp0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_DISP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_DISP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &disp1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_DISP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate mm_clks[] =3D { GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/= clk-mt2701-vdec.c index d3089da0ab62..0f07c5d731df 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x0008, }; =20 -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 06ca81359d35..dfe328f7a44b 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -636,14 +636,8 @@ static const struct mtk_gate_regs top_aud_cg_regs =3D { .sta_ofs =3D 0x012C, }; =20 -#define GATE_TOP_AUD(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top_aud_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr) =20 static const struct mtk_gate top_clks[] =3D { GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", @@ -702,14 +696,8 @@ static const struct mtk_gate_regs infra_cg_regs =3D { .sta_ofs =3D 0x0048, }; =20 -#define GATE_ICG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_ICG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate infra_clks[] =3D { GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0), @@ -823,23 +811,11 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { .sta_ofs =3D 0x001c, }; =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate peri_clks[] =3D { GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31), diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/c= lk-mt2712-bdp.c index 684d03e9f6de..5e668651dd90 100644 --- a/drivers/clk/mediatek/clk-mt2712-bdp.c +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs bdp_cg_regs =3D { .sta_ofs =3D 0x100, }; =20 -#define GATE_BDP(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &bdp_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_BDP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) =20 static const struct mtk_gate bdp_clks[] =3D { GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/c= lk-mt2712-img.c index 335049cdc856..3ffa51384e6b 100644 --- a/drivers/clk/mediatek/clk-mt2712-img.c +++ b/drivers/clk/mediatek/clk-mt2712-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediate= k/clk-mt2712-jpgdec.c index 07ba7c5e80af..8c768d5ce24d 100644 --- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs jpgdec_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_JPGDEC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &jpgdec_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_JPGDEC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &jpgdec_cg_regs, _shift, &mtk_clk_gate_ops_= setclr_inv) =20 static const struct mtk_gate jpgdec_clks[] =3D { GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/c= lk-mt2712-mfg.c index 42f8cf3ecf4c..8949315c2dd2 100644 --- a/drivers/clk/mediatek/clk-mt2712-mfg.c +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_MFG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mfg_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/cl= k-mt2712-mm.c index 615f6b0fe96e..850cef9f2009 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -30,32 +30,14 @@ static const struct mtk_gate_regs mm2_cg_regs =3D { .sta_ofs =3D 0x220, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mm_clks[] =3D { /* MM0 */ diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/= clk-mt2712-vdec.c index 6296ed5c5b55..572290dd43c8 100644 --- a/drivers/clk/mediatek/clk-mt2712-vdec.c +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x8, }; =20 -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { /* VDEC0 */ diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/= clk-mt2712-venc.c index b9bfc35de629..9588eb03016e 100644 --- a/drivers/clk/mediatek/clk-mt2712-venc.c +++ b/drivers/clk/mediatek/clk-mt2712-venc.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &venc_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 937c370d6765..d0e6a4fbfa99 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -814,23 +814,11 @@ static const struct mtk_gate_regs top1_cg_regs =3D { .sta_ofs =3D 0x424, }; =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } - -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) =20 static const struct mtk_gate top_clks[] =3D { /* TOP0 */ @@ -854,14 +842,8 @@ static const struct mtk_gate_regs infra_cg_regs =3D { .sta_ofs =3D 0x48, }; =20 -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate infra_clks[] =3D { GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), @@ -891,32 +873,14 @@ static const struct mtk_gate_regs peri2_cg_regs =3D { .sta_ofs =3D 0x42c, }; =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) + +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) + +#define GATE_PERI2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri2_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate peri_clks[] =3D { /* PERI0 */ diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek= /clk-mt6765-audio.c index 0aa6c0d352ca..5682e0302eee 100644 --- a/drivers/clk/mediatek/clk-mt6765-audio.c +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs audio1_cg_regs =3D { .sta_ofs =3D 0x4, }; =20 -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 static const struct mtk_gate audio_clks[] =3D { /* AUDIO0 */ diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/c= lk-mt6765-cam.c index 25f2bef38126..6e7d192c19cb 100644 --- a/drivers/clk/mediatek/clk-mt6765-cam.c +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs cam_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_CAM(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &cam_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_CAM(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate cam_clks[] =3D { GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0), diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/c= lk-mt6765-img.c index a62303ef4f41..cfbc907988af 100644 --- a/drivers/clk/mediatek/clk-mt6765-img.c +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0), diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediate= k/clk-mt6765-mipi0a.c index 25c829fc3866..f2b9dc808480 100644 --- a/drivers/clk/mediatek/clk-mt6765-mipi0a.c +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mipi0a_cg_regs =3D { .sta_ofs =3D 0x80, }; =20 -#define GATE_MIPI0A(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mipi0a_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_MIPI0A(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mipi0a_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 static const struct mtk_gate mipi0a_clks[] =3D { GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A, diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/cl= k-mt6765-mm.c index bda774668a36..a4570c9dbefa 100644 --- a/drivers/clk/mediatek/clk-mt6765-mm.c +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mm_cg_regs =3D { .sta_ofs =3D 0x100, }; =20 -#define GATE_MM(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm_cg_regs, _shift, &mtk_clk_gate_ops_setc= lr) =20 static const struct mtk_gate mm_clks[] =3D { /* MM */ diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediate= k/clk-mt6765-vcodec.c index 2bc1fbde87da..75d72b9b4032 100644 --- a/drivers/clk/mediatek/clk-mt6765-vcodec.c +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &venc_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0), diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index 6f5c92a7f620..0c20ce678350 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -483,32 +483,14 @@ static const struct mtk_gate_regs top2_cg_regs =3D { .sta_ofs =3D 0x320, }; =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) =20 -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 static const struct mtk_gate top_clks[] =3D { /* TOP0 */ @@ -559,41 +541,17 @@ static const struct mtk_gate_regs ifr5_cg_regs =3D { .sta_ofs =3D 0xc8, }; =20 -#define GATE_IFR2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_IFR3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr3_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_IFR4(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr4_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR4(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr4_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_IFR5(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ifr5_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr5_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 static const struct mtk_gate ifr_clks[] =3D { /* INFRA_TOPAXI */ @@ -674,14 +632,8 @@ static const struct mtk_gate_regs apmixed_cg_regs =3D { .sta_ofs =3D 0x14, }; =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &apmixed_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr_inv) =20 static const struct mtk_gate apmixed_clks[] =3D { /* AUDIO0 */ diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/c= lk-mt6797-img.c index 7c6a53fbb8be..06441393478f 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0000, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11), diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index 706c9775646d..e7a5a43f91f1 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -23,23 +23,11 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ -} +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ -} +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mm_clks[] =3D { GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/= clk-mt6797-vdec.c index 6120fccc859f..8622ddd87a5b 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x0008, }; =20 -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ -} +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ -} +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8), diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/= clk-mt6797-venc.c index 834d3834d2bb..928d611a476e 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs =3D { .sta_ofs =3D 0x0000, }; =20 -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &venc_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 static const struct mtk_gate venc_clks[] =3D { GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index 105a512857b3..17b23ee4faee 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -421,40 +421,22 @@ static const struct mtk_gate_regs infra2_cg_regs =3D { .sta_ofs =3D 0x00b0, }; =20 -#define GATE_ICG0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ -} +#define GATE_ICG0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_ICG1(_id, _name, _parent, _shift) \ - GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_ICG1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - .flags =3D _flags, \ -} +#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) =20 -#define GATE_ICG2(_id, _name, _parent, _shift) \ - GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_ICG2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - .flags =3D _flags, \ -} +#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) =20 /* * Clock gates dramc and dramc_b are needed by the DRAM controller. diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index b8aabfeb1cba..27c543759f2a 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -16,41 +16,17 @@ =20 #include =20 -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 -#define GATE_AUDIO3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &audio3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr) =20 static const struct mtk_gate_regs audio0_cg_regs =3D { .set_ofs =3D 0x0, diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index aee583fa77d0..66b163cc1633 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -16,14 +16,8 @@ =20 #include =20 -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate_regs eth_cg_regs =3D { .set_ofs =3D 0x30, @@ -45,14 +39,8 @@ static const struct mtk_gate_regs sgmii_cg_regs =3D { .sta_ofs =3D 0xE4, }; =20 -#define GATE_SGMII(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &sgmii_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate sgmii_clks[] =3D { GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index ab5cad0c2b1c..bcd1dfc6e8e0 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -16,23 +16,11 @@ =20 #include =20 -#define GATE_PCIE(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &pcie_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } - -#define GATE_SSUSB(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ssusb_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PCIE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_SSUSB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate_regs pcie_cg_regs =3D { .set_ofs =3D 0x30, diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 5a82c2270bfb..41af8d420bbf 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -50,59 +50,24 @@ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ NULL, "clkxtal") =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &apmixed_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv) =20 -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static DEFINE_SPINLOCK(mt7622_clk_lock); =20 diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index a4ae7d6c7a71..719a47fef798 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -16,14 +16,8 @@ =20 #include =20 -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate_regs eth_cg_regs =3D { .set_ofs =3D 0x30, @@ -45,14 +39,8 @@ static const struct mtk_gate_regs sgmii_cg_regs =3D { .sta_ofs =3D 0xE4, }; =20 -#define GATE_SGMII(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &sgmii_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate sgmii_clks[2][4] =3D { { diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index c3eb09ea6036..78d85542e4f1 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -16,23 +16,11 @@ =20 #include =20 -#define GATE_PCIE(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &pcie_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } - -#define GATE_SSUSB(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &ssusb_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PCIE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_SSUSB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) =20 static const struct mtk_gate_regs pcie_cg_regs =3D { .set_ofs =3D 0x30, diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index cf062d4a7ecc..09c85fda43d8 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -50,41 +50,17 @@ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ NULL, "clk20m") =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &apmixed_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr_inv) =20 -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static DEFINE_SPINLOCK(mt7629_clk_lock); =20 diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/c= lk-mt7986-eth.c index 703872239ecc..e04bc6845ea6 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -22,12 +22,8 @@ static const struct mtk_gate_regs sgmii0_cg_regs =3D { .sta_ofs =3D 0xe4, }; =20 -#define GATE_SGMII0(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &sgmii0_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 static const struct mtk_gate sgmii0_clks[] __initconst =3D { GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), @@ -42,12 +38,8 @@ static const struct mtk_gate_regs sgmii1_cg_regs =3D { .sta_ofs =3D 0xe4, }; =20 -#define GATE_SGMII1(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &sgmii1_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 static const struct mtk_gate sgmii1_clks[] __initconst =3D { GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), @@ -62,12 +54,8 @@ static const struct mtk_gate_regs eth_cg_regs =3D { .sta_ofs =3D 0x30, }; =20 -#define GATE_ETH(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D ð_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 static const struct mtk_gate eth_clks[] __initconst =3D { GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/media= tek/clk-mt7986-infracfg.c index e80c92167c8f..0a4bf87ee160 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -87,26 +87,14 @@ static const struct mtk_gate_regs infra2_cg_regs =3D { .sta_ofs =3D 0x68, }; =20 -#define GATE_INFRA0(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &infra0_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_INFRA1(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &infra1_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 -#define GATE_INFRA2(_id, _name, _parent, _shift) = \ - { \ - .id =3D _id, .name =3D _name, .parent_name =3D _parent, \ - .regs =3D &infra2_cg_regs, .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_= setclr) =20 static const struct mtk_gate infra_clks[] =3D { /* INFRA0 */ diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 2b9c925c2a2b..97a115d2c3da 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -401,14 +401,8 @@ static const struct mtk_gate_regs infra_cg_regs =3D { .sta_ofs =3D 0x0048, }; =20 -#define GATE_ICG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_ICG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate infra_clks[] __initconst =3D { GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), @@ -438,23 +432,11 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { .sta_ofs =3D 0x001c, }; =20 -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate peri_gates[] __initconst =3D { /* PERI0 */ diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index eec9de190cb6..8869c53da79c 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -23,14 +23,9 @@ static const struct mtk_gate_regs aud_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_AUD(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &aud_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) + =20 static const struct mtk_gate aud_clks[] =3D { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index 5cd51d894d32..6a068f2a9dce 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -23,14 +23,8 @@ static const struct mtk_gate_regs img_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &img_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate img_clks[] =3D { GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0), diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 2cf88d5d245d..7fcb944134b6 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -23,14 +23,8 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_MFG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mfg_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0), diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/cl= k-mt8167-mm.c index 78c023b0565a..5a5192d0dc45 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -29,23 +29,11 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { .sta_ofs =3D 0x110, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mm_clks[] =3D { /* MM0 */ diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index c3e2253a57d7..b3eccc2eca58 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -29,23 +29,11 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { .sta_ofs =3D 0x8, }; =20 -#define GATE_VDEC0_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 -#define GATE_VDEC1_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr_inv) =20 static const struct mtk_gate vdec_clks[] =3D { /* VDEC0 */ diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/cl= k-mt8173-mm.c index ffec2d917661..435cfae25492 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -25,23 +25,11 @@ static const struct mtk_gate_regs mm1_cg_regs =3D { .sta_ofs =3D 0x0110, }; =20 -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &mm1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) =20 static const struct mtk_gate mt8173_mm_clks[] =3D { GATE_DUMMY(CLK_DUMMY, "mm_dummy"), diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/c= lk-mt8516-aud.c index 00f356fe7c7a..a6ae8003b9ff 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -22,14 +22,8 @@ static const struct mtk_gate_regs aud_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_AUD(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &aud_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) =20 static const struct mtk_gate aud_clks[] __initconst =3D { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index 2c0cae7b3bcf..6983d3a48dc9 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -525,59 +525,23 @@ static const struct mtk_gate_regs top5_cg_regs =3D { .sta_ofs =3D 0x44, }; =20 -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP2_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top2_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP2_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP3(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top3_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 -#define GATE_TOP4_I(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top4_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_TOP4_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) =20 -#define GATE_TOP5(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &top5_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr) =20 static const struct mtk_gate top_clks[] __initconst =3D { /* TOP1 */ --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 189A0C636CC for ; Mon, 20 Feb 2023 15:03:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232832AbjBTPD1 (ORCPT ); Mon, 20 Feb 2023 10:03:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232135AbjBTPCm (ORCPT ); Mon, 20 Feb 2023 10:02:42 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B4B320573; Mon, 20 Feb 2023 07:01:50 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 57BB86602176; Mon, 20 Feb 2023 15:01:47 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905308; bh=qEBrgGdbulqzhtfUdPsw3k5Qo9gj6LPHE51E64is1Uk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KwNQ1xNUAHedRvQ6pHiAwZozsE0CSvSiwW/I0xu5+NCwsoHBELFO24wBiLNjPdmhu gSbHuakv9amEtsK9U+UQ2A8O9hLEcLffALhwVmVLRuwg+gnZqsouYOzpiUIG2wG9zz bT+FnXZZT/PC1yPWL8SJLJFqbbUjzfvOmO8isGZOJvWeZZR14HVFR39ZHRxqan2PcH vV8ZLoLLg/LveH4SWANY0cEXlkCP54OAJhYX72oiFtupcdAYtVZ8APC3cSbxfH8c82 mPXm7V4yYSjoKojTgWbPmUk1h7BidyfgLjo5XpzyFp6HzE3jNxSGL1gdCp1x8MqVuN O5pwJ89kebr4w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 23/55] clk: mediatek: mt7622: Properly use CLK_IS_CRITICAL flag Date: Mon, 20 Feb 2023 16:00:39 +0100 Message-Id: <20230220150111.77897-24-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: 2fc0a509e4ee ("clk: mediatek: add clock support for MT7622 SoC") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt7622.c | 35 +++++++++++++------------------ 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 41af8d420bbf..1c0049fbeb69 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -50,9 +50,9 @@ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ NULL, "clkxtal") =20 -#define GATE_APMIXED(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, \ - &mtk_clk_gate_ops_no_setclr_inv) +#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL) =20 #define GATE_INFRA(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) @@ -66,6 +66,10 @@ #define GATE_PERI0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 +#define GATE_PERI0_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) + #define GATE_PERI1(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 @@ -315,7 +319,7 @@ static const struct mtk_pll_data plls[] =3D { }; =20 static const struct mtk_gate apmixed_clks[] =3D { - GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), + GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), }; =20 static const struct mtk_gate infra_clks[] =3D { @@ -450,7 +454,7 @@ static const struct mtk_gate peri_clks[] =3D { GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), - GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), + GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), @@ -478,12 +482,12 @@ static struct mtk_composite infra_muxes[] =3D { =20 static struct mtk_composite top_muxes[] =3D { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, - 0x040, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, - 0x040, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, - 0x040, 16, 1, 23), + MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, + 0x040, 0, 3, 7, CLK_IS_CRITICAL), + MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, + 0x040, 8, 1, 15, CLK_IS_CRITICAL), + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, + 0x040, 16, 1, 23, CLK_IS_CRITICAL), MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x040, 24, 3, 31), =20 @@ -621,10 +625,6 @@ static int mtk_topckgen_init(struct platform_device *p= dev) mtk_clk_register_gates(&pdev->dev, node, top_clks, ARRAY_SIZE(top_clks), clk_data); =20 - clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } =20 @@ -667,9 +667,6 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); =20 - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); - clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } =20 @@ -697,8 +694,6 @@ static int mtk_pericfg_init(struct platform_device *pde= v) if (r) return r; =20 - clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk); - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); =20 return 0; --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4679BC05027 for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1676905309; bh=ZSpxb+kxw1MAPqOUj1dDriQpkA+rVpzbjlUvwvsXJLQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CykQdfoW95y5fw6tTE8EpueLFWGElccNfiStXyXRbmboNLRzpE/WlqZZEbQIKP0Fj DWFMkla8SgDjNitcO33P0rarJl+gSuSpAUe2HR7Lcdur7ET/RFGOnsGbwC8XMpJha7 zkkRF4xdQsflmkv73AlnqqyE4F8jFayuF3wawZjmq1UpFH3uf1pNCAbdSIQAu0l6nE FPZRnrx70gTFnQd91fG2xTA5910z5DqseoYipbIidfARSUZNERHAf8D3Rjp62xJQb8 hTt0UdfKprCNSELLCk1tpuDglhb/EXmzylEH/so4jRmbyCN4dRF1ccA58T5D50jAdR MjBzM6eeZueyQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 24/55] clk: mediatek: mt7622: Move apmixedsys clock driver to its own file Date: Mon, 20 Feb 2023 16:00:40 +0100 Message-Id: <20230220150111.77897-25-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating mt7622 clocks to the common simple probe mechanism, move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 137 +++++++++++++++++++ drivers/clk/mediatek/clk-mt7622.c | 87 ------------ 3 files changed, 138 insertions(+), 88 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt7622-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 10038a0f25e0..c1bee331eebf 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) +=3D clk-mt2712-mf= g.o obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) +=3D clk-mt2712-mm.o obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) +=3D clk-mt2712-vdec.o obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) +=3D clk-mt2712-venc.o -obj-$(CONFIG_COMMON_CLK_MT7622) +=3D clk-mt7622.o +obj-$(CONFIG_COMMON_CLK_MT7622) +=3D clk-mt7622.o clk-mt7622-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) +=3D clk-mt7622-eth.o obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) +=3D clk-mt7622-hif.o obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +=3D clk-mt7622-aud.o diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/med= iatek/clk-mt7622-apmixedsys.c new file mode 100644 index 000000000000..497fada797b9 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017 MediaTek Inc. + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +#define MT7622_PLL_FMAX (2500UL * MHZ) +#define CON0_MT7622_RST_BAR BIT(27) + +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table, _parent_name) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D CON0_MT7622_RST_BAR, \ + .fmax =3D MT7622_PLL_FMAX, \ + .pcwbits =3D _pcwbits, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .div_table =3D _div_table, \ + .parent_name =3D _parent_name, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + NULL, "clkxtal") + +static const struct mtk_gate_regs apmixed_cg_regs =3D { + .set_ofs =3D 0x8, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x8, +}; + +#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL) + +static const struct mtk_pll_data plls[] =3D { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, + PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, + HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, + HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), + PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0, + 0, 21, 0x0300, 1, 0, 0x0304, 0), + PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0, + 0, 21, 0x0314, 1, 0, 0x0318, 0), + PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0, + 0, 31, 0x0324, 1, 0, 0x0328, 0), + PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0, + 0, 31, 0x0334, 1, 0, 0x0338, 0), + PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0, + 0, 21, 0x0344, 1, 0, 0x0348, 0), + PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0, + 0, 21, 0x0358, 1, 0, 0x035C, 0), +}; + +static const struct mtk_gate apmixed_clks[] =3D { + GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), +}; + +static int clk_mt7622_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (ret) + goto unregister_plls; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_gates; + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt7622_apmixed[] =3D { + { .compatible =3D "mediatek,mt7622-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt7622_apmixed_drv =3D { + .probe =3D clk_mt7622_apmixed_probe, + .driver =3D { + .name =3D "clk-mt7622-apmixed", + .of_match_table =3D of_match_clk_mt7622_apmixed, + }, +}; +builtin_platform_driver(clk_mt7622_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT7622 apmixedsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 1c0049fbeb69..6cf74c948ac7 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -14,46 +14,10 @@ #include "clk-cpumux.h" #include "clk-gate.h" #include "clk-mtk.h" -#include "clk-pll.h" =20 #include #include /* for consumer */ =20 -#define MT7622_PLL_FMAX (2500UL * MHZ) -#define CON0_MT7622_RST_BAR BIT(27) - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift, _div_table, _parent_name) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D CON0_MT7622_RST_BAR, \ - .fmax =3D MT7622_PLL_FMAX, \ - .pcwbits =3D _pcwbits, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .div_table =3D _div_table, \ - .parent_name =3D _parent_name, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - NULL, "clkxtal") - -#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \ - GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \ - &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL) - #define GATE_INFRA(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 @@ -261,12 +225,6 @@ static const char * const peribus_ck_parents[] =3D { "syspll1_d4" }; =20 -static const struct mtk_gate_regs apmixed_cg_regs =3D { - .set_ofs =3D 0x8, - .clr_ofs =3D 0x8, - .sta_ofs =3D 0x8, -}; - static const struct mtk_gate_regs infra_cg_regs =3D { .set_ofs =3D 0x40, .clr_ofs =3D 0x44, @@ -297,31 +255,6 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { .sta_ofs =3D 0x1C, }; =20 -static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, - PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, - HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), - PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, - HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), - PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0, - 0, 21, 0x0300, 1, 0, 0x0304, 0), - PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0, - 0, 21, 0x0314, 1, 0, 0x0318, 0), - PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0, - 0, 31, 0x0324, 1, 0, 0x0328, 0), - PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0, - 0, 31, 0x0334, 1, 0, 0x0338, 0), - PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0, - 0, 21, 0x0344, 1, 0, 0x0348, 0), - PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0, - 0, 21, 0x0358, 1, 0, 0x035C, 0), -}; - -static const struct mtk_gate apmixed_clks[] =3D { - GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), -}; - static const struct mtk_gate infra_clks[] =3D { GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), @@ -652,23 +585,6 @@ static int mtk_infrasys_init(struct platform_device *p= dev) return 0; } =20 -static int mtk_apmixedsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), - clk_data); - - mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} =20 static int mtk_pericfg_init(struct platform_device *pdev) { @@ -701,9 +617,6 @@ static int mtk_pericfg_init(struct platform_device *pde= v) =20 static const struct of_device_id of_match_clk_mt7622[] =3D { { - .compatible =3D "mediatek,mt7622-apmixedsys", - .data =3D mtk_apmixedsys_init, - }, { .compatible =3D "mediatek,mt7622-infracfg", .data =3D mtk_infrasys_init, }, { --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABC98C64EC4 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905311; bh=T91Ba3/qDGf8sWWJXdHxINm7g/vf3TN99/lK3EA+d84=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S+QKTzOPirQoL+nnyWmkVbLGda6NSB+cQyii7xHxVvIo5iGwvB3N8GQNMNDWPjeL9 GETLl2tb+noVzjdkkQNo4MNztgG/nwvkgTuMgWKWRbcMEenUxXrEDh03WZF82qugZ+ p5xMO2YVAlJsbanrTGuKiMdV4ILqz97e3UUoLiQ052HktWGH/0gAspKOJAEdLIa+PQ 9LgU7WdRHYBQScCgg1VVuvz25xljvtW9S3eYSvkmfDodxIevgWQJ9yYlQbo6TqB615 rwoja89AqMZpm/ejnknOAS/JuS5FXzJQXPUhXCZ27+/3NuPL1njzgfTJ/F+gNTA//e Q+Ow2hVuoZUXA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 25/55] clk: mediatek: mt7622-apmixedsys: Add .remove() callback for module build Date: Mon, 20 Feb 2023 16:00:41 +0100 Message-Id: <20230220150111.77897-26-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a .remove() callback to the apmixedsys driver to allow full module build; while at it, also change the usage of builtin_platform_driver() to module_platform_driver() to actually make use of the new callback. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/med= iatek/clk-mt7622-apmixedsys.c index 497fada797b9..a9f3057d7080 100644 --- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -119,6 +119,19 @@ static int clk_mt7622_apmixed_probe(struct platform_de= vice *pdev) return ret; } =20 +static int clk_mt7622_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + static const struct of_device_id of_match_clk_mt7622_apmixed[] =3D { { .compatible =3D "mediatek,mt7622-apmixedsys" }, { /* sentinel */ } @@ -126,12 +139,13 @@ static const struct of_device_id of_match_clk_mt7622_= apmixed[] =3D { =20 static struct platform_driver clk_mt7622_apmixed_drv =3D { .probe =3D clk_mt7622_apmixed_probe, + .remove =3D clk_mt7622_apmixed_remove, .driver =3D { .name =3D "clk-mt7622-apmixed", .of_match_table =3D of_match_clk_mt7622_apmixed, }, }; -builtin_platform_driver(clk_mt7622_apmixed_drv) +module_platform_driver(clk_mt7622_apmixed_drv) =20 MODULE_DESCRIPTION("MediaTek MT7622 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DB1CC636CC for ; Mon, 20 Feb 2023 15:03:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232617AbjBTPD4 (ORCPT ); Mon, 20 Feb 2023 10:03:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232530AbjBTPDN (ORCPT ); Mon, 20 Feb 2023 10:03:13 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9578F1DBA6; Mon, 20 Feb 2023 07:02:08 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 866C06602136; Mon, 20 Feb 2023 15:01:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905312; bh=eh5GXyeSIL7bMN9yHS8TdHQpEiVl+DCQQSgnD2Vktug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DTr98LlF0N5p3sKFeGi6/E5QrWwoS1WA9tZQF8hL5ctBxZV/1/aUpw7FLqL5Sgkmd FPxNsTZvqzn9JyWUlH/cb4pHie2AHw3Y62z/fbtyhwIuRLS5ryXVnkDZyoU18wU5TS 77yAvPHBmgG+GGx1vKta/ovcOiC9RYP+swHSkun0IGWlputkn2hipyZ6/yghBBHcz2 eP6XqYckpYqP7kc4e/9BuHWoZiC8u5tFSksCiiLTTlVlGDmNfD8lOymUOSf2+aeATQ QkHawheroOabRsUgX9kRSyTTd6UJqzojcbk2Q2IhsJ/MXEAXTjyON8jRvuXtIoXynF pZwOFUE7Qaa4Q== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 26/55] clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.c Date: Mon, 20 Feb 2023 16:00:42 +0100 Message-Id: <20230220150111.77897-27-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The infracfg driver cannot be converted to clk_mtk_simple_probe() as it registers cpumuxes, which is not supported on the common probing mechanism: for this reason, move it to its own file. While at it, also convert it to be a platform driver instead; to do so, also add a .remove() callback for this driver. During the conversion, error handling was added to the infracfg probe function. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 3 +- drivers/clk/mediatek/clk-mt7622-infracfg.c | 127 +++++++++++++++++++++ drivers/clk/mediatek/clk-mt7622.c | 78 +------------ 3 files changed, 134 insertions(+), 74 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt7622-infracfg.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index c1bee331eebf..0f2cd735d9fd 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -46,7 +46,8 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) +=3D clk-mt2712-mf= g.o obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) +=3D clk-mt2712-mm.o obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) +=3D clk-mt2712-vdec.o obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) +=3D clk-mt2712-venc.o -obj-$(CONFIG_COMMON_CLK_MT7622) +=3D clk-mt7622.o clk-mt7622-apmixedsys.o +obj-$(CONFIG_COMMON_CLK_MT7622) +=3D clk-mt7622.o clk-mt7622-apmixedsys.o \ + clk-mt7622-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) +=3D clk-mt7622-eth.o obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) +=3D clk-mt7622-hif.o obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +=3D clk-mt7622-aud.o diff --git a/drivers/clk/mediatek/clk-mt7622-infracfg.c b/drivers/clk/media= tek/clk-mt7622-infracfg.c new file mode 100644 index 000000000000..09d8ac4d483a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7622-infracfg.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017 MediaTek Inc. + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include + +#include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "reset.h" + +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) + +static const struct mtk_gate_regs infra_cg_regs =3D { + .set_ofs =3D 0x40, + .clr_ofs =3D 0x44, + .sta_ofs =3D 0x48, +}; + +static const char * const infra_mux1_parents[] =3D { + "clkxtal", + "armpll", + "main_core_en", + "armpll" +}; + +static const struct mtk_composite cpu_muxes[] =3D { + MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2= ), +}; + +static const struct mtk_gate infra_clks[] =3D { + GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), + GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), + GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), + GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), + GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), + GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), +}; + +static u16 infrasys_rst_ofs[] =3D { 0x30 }; + +static const struct mtk_clk_rst_desc clk_rst_desc =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), +}; + +static const struct of_device_id of_match_clk_mt7622_infracfg[] =3D { + { .compatible =3D "mediatek,mt7622-infracfg" }, + { /* sentinel */ } +}; + +static int clk_mt7622_infracfg_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); + if (ret) + goto free_clk_data; + + ret =3D mtk_clk_register_gates(&pdev->dev, node, infra_clks, + ARRAY_SIZE(infra_clks), clk_data); + if (ret) + goto free_clk_data; + + ret =3D mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, + ARRAY_SIZE(cpu_muxes), clk_data); + if (ret) + goto unregister_gates; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_cpumuxes; + + return 0; + +unregister_cpumuxes: + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); +unregister_gates: + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return ret; +} + +static int clk_mt7622_infracfg_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt7622_infracfg_drv =3D { + .driver =3D { + .name =3D "clk-mt7622-infracfg", + .of_match_table =3D of_match_clk_mt7622_infracfg, + }, + .probe =3D clk_mt7622_infracfg_probe, + .remove =3D clk_mt7622_infracfg_remove, +}; +module_platform_driver(clk_mt7622_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 6cf74c948ac7..fb813f8d3a7d 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -18,9 +18,6 @@ #include #include /* for consumer */ =20 -#define GATE_INFRA(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) - #define GATE_TOP0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr) =20 @@ -39,13 +36,6 @@ =20 static DEFINE_SPINLOCK(mt7622_clk_lock); =20 -static const char * const infra_mux1_parents[] =3D { - "clkxtal", - "armpll", - "main_core_en", - "armpll" -}; - static const char * const axi_parents[] =3D { "clkxtal", "syspll1_d2", @@ -225,12 +215,6 @@ static const char * const peribus_ck_parents[] =3D { "syspll1_d4" }; =20 -static const struct mtk_gate_regs infra_cg_regs =3D { - .set_ofs =3D 0x40, - .clr_ofs =3D 0x44, - .sta_ofs =3D 0x48, -}; - static const struct mtk_gate_regs top0_cg_regs =3D { .set_ofs =3D 0x120, .clr_ofs =3D 0x120, @@ -255,15 +239,6 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { .sta_ofs =3D 0x1C, }; =20 -static const struct mtk_gate infra_clks[] =3D { - GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), - GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), - GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), - GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), - GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), - GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), -}; - static const struct mtk_fixed_clk top_fixed_clks[] =3D { FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 31250000), @@ -408,11 +383,6 @@ static const struct mtk_gate peri_clks[] =3D { GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), }; =20 -static struct mtk_composite infra_muxes[] =3D { - MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, - 0x000, 2, 2), -}; - static struct mtk_composite top_muxes[] =3D { /* CLK_CFG_0 */ MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, @@ -512,22 +482,12 @@ static struct mtk_composite peri_muxes[] =3D { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; =20 -static u16 infrasys_rst_ofs[] =3D { 0x30, }; static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; =20 -static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { - /* infrasys */ - { - .version =3D MTK_RST_SIMPLE, - .rst_bank_ofs =3D infrasys_rst_ofs, - .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), - }, - /* pericfg */ - { - .version =3D MTK_RST_SIMPLE, - .rst_bank_ofs =3D pericfg_rst_ofs, - .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), - }, +static const struct mtk_clk_rst_desc clk_rst_desc =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), }; =20 static int mtk_topckgen_init(struct platform_device *pdev) @@ -561,31 +521,6 @@ static int mtk_topckgen_init(struct platform_device *p= dev) return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } =20 -static int mtk_infrasys_init(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - - mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, - ARRAY_SIZE(infra_muxes), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); - if (r) - return r; - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); - - return 0; -} - - static int mtk_pericfg_init(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -610,16 +545,13 @@ static int mtk_pericfg_init(struct platform_device *p= dev) if (r) return r; =20 - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return 0; } =20 static const struct of_device_id of_match_clk_mt7622[] =3D { { - .compatible =3D "mediatek,mt7622-infracfg", - .data =3D mtk_infrasys_init, - }, { .compatible =3D "mediatek,mt7622-topckgen", .data =3D mtk_topckgen_init, }, { --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7C7EC05027 for ; Mon, 20 Feb 2023 15:03:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231703AbjBTPDn (ORCPT ); Mon, 20 Feb 2023 10:03:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232457AbjBTPC7 (ORCPT ); Mon, 20 Feb 2023 10:02:59 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4533F2068C; Mon, 20 Feb 2023 07:01:58 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id EA9A86602166; Mon, 20 Feb 2023 15:01:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905314; bh=hWZRDGal3GNmdFtLS5t4q03/QmGR1D89Es46OeyDZNc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F4Z1qGNARyyqYtHkxWcnf33RZWdglNz10upRApbN0JYXXE8Nsqq/BQMC+XteydqBq Q0K2i98tOP6HroxmrUdL0ZmWU3kDaz8qJ3KR2KrFeOmmsJPR/6iXHD9FwZXevWaEGF cCYY19r+rBs2/goMjHI+StAhA1hUdFUMs3X5DtHQqb5tJxfX0+Wr3xQE5f8tw8GFgt W8cWNrnPSzKy2PxOZ4zeFW0xIgAav60y8AhmPvp9gSxEQbgYQyvzwpIsARIA8UGKHM 1Ht9RO3XAzTqRyw1/t3gYPe0NnGL6YId/WN9yCdsJRHWTNpIwQGjfkOT2Yf7s5CewG q6a8XYdrrvWxQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 27/55] clk: mediatek: mt7622: Convert to platform driver and simple probe Date: Mon, 20 Feb 2023 16:00:43 +0100 Message-Id: <20230220150111.77897-28-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the MT7622 topckgen and pericfg clock drivers to platform drivers and use the simple probe mechanism. This also allows to build these clocks as modules. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt7622.c | 125 ++++++++---------------------- 1 file changed, 31 insertions(+), 94 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index fb813f8d3a7d..7a002b73fcaa 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -490,107 +490,44 @@ static const struct mtk_clk_rst_desc clk_rst_desc = =3D { .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), }; =20 -static int mtk_topckgen_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - struct device_node *node =3D pdev->dev.of_node; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt7622_clk_lock, clk_data); - - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt7622_clk_lock, clk_data); - - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static int mtk_pericfg_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - struct device_node *node =3D pdev->dev.of_node; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(&pdev->dev, peri_muxes, - ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - return r; - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return 0; -} +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt7622_clk_lock, +}; + +static const struct mtk_clk_desc peri_desc =3D { + .clks =3D peri_clks, + .num_clks =3D ARRAY_SIZE(peri_clks), + .composite_clks =3D peri_muxes, + .num_composite_clks =3D ARRAY_SIZE(peri_muxes), + .rst_desc =3D &clk_rst_desc, + .clk_lock =3D &mt7622_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt7622[] =3D { - { - .compatible =3D "mediatek,mt7622-topckgen", - .data =3D mtk_topckgen_init, - }, { - .compatible =3D "mediatek,mt7622-pericfg", - .data =3D mtk_pericfg_init, - }, { - /* sentinel */ - } -}; - -static int clk_mt7622_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} + { .compatible =3D "mediatek,mt7622-topckgen", .data =3D &topck_desc }, + { .compatible =3D "mediatek,mt7622-pericfg", .data =3D &peri_desc }, + { /* sentinel */ } +}; =20 static struct platform_driver clk_mt7622_drv =3D { - .probe =3D clk_mt7622_probe, .driver =3D { .name =3D "clk-mt7622", .of_match_table =3D of_match_clk_mt7622, }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; +module_platform_driver(clk_mt7622_drv) =20 -static int clk_mt7622_init(void) -{ - return platform_driver_register(&clk_mt7622_drv); -} - -arch_initcall(clk_mt7622_init); +MODULE_DESCRIPTION("MediaTek MT7622 clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCD10C05027 for ; Mon, 20 Feb 2023 15:04:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232907AbjBTPEP (ORCPT ); Mon, 20 Feb 2023 10:04:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232726AbjBTPDY (ORCPT ); Mon, 20 Feb 2023 10:03:24 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3E38206A0; Mon, 20 Feb 2023 07:02:14 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 549376602177; Mon, 20 Feb 2023 15:01:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905315; bh=lK+OUhgRAWsWXMNgwB1Jy/MlnHCd1PfzA4X17tTY7y8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JRsltzUKt3P//EjY4fd4+08ZjcKU/6thFAaXXTIZzmPNvF5rtcp1gadHQUVBVXqSI V4brvEdVFovNYVWuayVOpOCTqG1bMrnil8KMG5U0vw1Pi3SssV920q3MWOGcbOx3bR /D5PnqDJp0KiR6JkCAngt8Dg7U9QYs1I3mFETZY7cMOoCDFE4LMXGi2cCoqfoGrDJZ q5X8qXD7Au6mCwYfmXPKm2Ei7D/8/GtoOZF0SpNAZ6Yz6GaE3VhRGwmZzCoxcmreCC Xucydb3Evn0TOPK2W4DACpBhLWp3R+3aAITK5x9wIfiixW+yN5nQQqmkSOQGmiBk4p QxJeNFYCR4rKQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 28/55] clk: mediatek: mt8516: Move apmixedsys clock driver to its own file Date: Mon, 20 Feb 2023 16:00:44 +0100 Message-Id: <20230220150111.77897-29-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating mt8516 clocks to the common simple probe mechanism, convert the apmixedsys to be a separated platform driver and move it to clk-mt8516-apmixedsys.c. While at it, also fix some indentation issues. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 121 +++++++++++++++++++ drivers/clk/mediatek/clk-mt8516.c | 81 ------------- 3 files changed, 122 insertions(+), 82 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8516-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 0f2cd735d9fd..3133ad8c2028 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -120,5 +120,5 @@ obj-$(CONFIG_COMMON_CLK_MT8365_MFG) +=3D clk-mt8365-mfg= .o obj-$(CONFIG_COMMON_CLK_MT8365_MMSYS) +=3D clk-mt8365-mm.o obj-$(CONFIG_COMMON_CLK_MT8365_VDEC) +=3D clk-mt8365-vdec.o obj-$(CONFIG_COMMON_CLK_MT8365_VENC) +=3D clk-mt8365-venc.o -obj-$(CONFIG_COMMON_CLK_MT8516) +=3D clk-mt8516.o +obj-$(CONFIG_COMMON_CLK_MT8516) +=3D clk-mt8516.o clk-mt8516-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) +=3D clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8516-apmixedsys.c new file mode 100644 index 000000000000..5b87c9fb81f5 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019 MediaTek Inc. + * James Liao + * Fabien Parent + * + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-pll.h" + +#define MT8516_PLL_FMAX (1502UL * MHZ) + +#define CON0_MT8516_RST_BAR BIT(27) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D CON0_MT8516_RST_BAR, \ + .fmax =3D MT8516_PLL_FMAX, \ + .pcwbits =3D _pcwbits, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .div_table =3D _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + NULL) + +static const struct mtk_pll_div_table mmpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8516_PLL_FMAX }, + { .div =3D 1, .freq =3D 1000000000 }, + { .div =3D 2, .freq =3D 604500000 }, + { .div =3D 3, .freq =3D 253500000 }, + { .div =3D 4, .freq =3D 126750000 }, + { } /* sentinel */ +}; + +static const struct mtk_pll_data plls[] =3D { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, + 21, 0x0104, 24, 0, 0x0104, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, + HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, + HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, + 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), + PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, + 31, 0x0180, 1, 0x0194, 0x0184, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, + 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), +}; + +static int clk_mt8516_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_plls; + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8516_apmixed[] =3D { + { .compatible =3D "mediatek,mt8516-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8516_apmixed_drv =3D { + .probe =3D clk_mt8516_apmixed_probe, + .driver =3D { + .name =3D "clk-mt8516-apmixed", + .of_match_table =3D of_match_clk_mt8516_apmixed, + }, +}; +builtin_platform_driver(clk_mt8516_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index 6983d3a48dc9..51e6948cb54b 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -13,7 +13,6 @@ =20 #include "clk-gate.h" #include "clk-mtk.h" -#include "clk-pll.h" =20 #include =20 @@ -695,83 +694,3 @@ static void __init mtk_infracfg_init(struct device_nod= e *node) __func__, r); } CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init= ); - -#define MT8516_PLL_FMAX (1502UL * MHZ) - -#define CON0_MT8516_RST_BAR BIT(27) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift, _div_table) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D CON0_MT8516_RST_BAR, \ - .fmax =3D MT8516_PLL_FMAX, \ - .pcwbits =3D _pcwbits, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .div_table =3D _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - NULL) - -static const struct mtk_pll_div_table mmpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8516_PLL_FMAX }, - { .div =3D 1, .freq =3D 1000000000 }, - { .div =3D 2, .freq =3D 604500000 }, - { .div =3D 3, .freq =3D 253500000 }, - { .div =3D 4, .freq =3D 126750000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, - 21, 0x0104, 24, 0, 0x0104, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, - HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, - HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, - 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), - PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, - 31, 0x0180, 1, 0x0194, 0x0184, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, - 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), -}; - -static void __init mtk_apmixedsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - -} -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys", - mtk_apmixedsys_init); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B2CAC05027 for ; Mon, 20 Feb 2023 15:04:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231941AbjBTPE1 (ORCPT ); Mon, 20 Feb 2023 10:04:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232241AbjBTPD2 (ORCPT ); Mon, 20 Feb 2023 10:03:28 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 275E8206BB; Mon, 20 Feb 2023 07:02:23 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BB0AC6602192; Mon, 20 Feb 2023 15:01:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905316; bh=mBi2vu9zK6J7OK8kzMEo2QXJSnqtMODi1D3E+PXa/E0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SLWgdIOtEVlDGLlEPmLGiHhaUaYAYccLWVn5Bt08yFnCo9c7P4ySQwaJwzHa6AKgN doCQIWThnDzTemP/xFJPkNJtDY8/Y6eNw0/RjGpy19jCcrKcya1ZOpmYF330qIWQFv Af1dJCl2q9oHbG5J2s5gZYTPsQ9pUnXu7O4JoZpCwKFRi/nX7ThXpqZLoVvKnA7SGl DOGhKVvkTbcwEr/lBcvA5TXUstOa9p6etD4mC7XXtCZ6T5WpYISPStrE+lJyfVUWeI eb3IFmRZoettsgqSk/Mg5uCPwNcAnMchCKznbW35ntVWDLMubSGgq80uQpn4OKKZaK PfVBq6cPkEpEA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 29/55] clk: mediatek: mt8516: Convert to platform driver and simple probe Date: Mon, 20 Feb 2023 16:00:45 +0100 Message-Id: <20230220150111.77897-30-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the MT8516 clock drivers to be platform drivers and use the common probe mechanism. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8516-aud.c | 35 ++++++----- drivers/clk/mediatek/clk-mt8516.c | 88 +++++++++++---------------- 2 files changed, 57 insertions(+), 66 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/c= lk-mt8516-aud.c index a6ae8003b9ff..119dbbd0c3e0 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 MediaTek Inc. * Author: James Liao * Fabien Parent + * Copyright (c) 2023 Collabora Ltd. */ =20 #include @@ -25,7 +26,7 @@ static const struct mtk_gate_regs aud_cg_regs =3D { #define GATE_AUD(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr) =20 -static const struct mtk_gate aud_clks[] __initconst =3D { +static const struct mtk_gate aud_clks[] =3D { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6), GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8), @@ -41,19 +42,25 @@ static const struct mtk_gate aud_clks[] __initconst =3D= { GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), }; =20 -static void __init mtk_audsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR_CLK); +static const struct mtk_clk_desc aud_desc =3D { + .clks =3D aud_clks, + .num_clks =3D ARRAY_SIZE(aud_clks), +}; =20 - mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_da= ta); +static const struct of_device_id of_match_clk_mt8516_aud[] =3D { + { .compatible =3D "mediatek,mt8516-audsys", .data =3D &aud_desc }, + { /* sentinel */ } +}; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static struct platform_driver clk_mt8516_aud_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8516-aud", + .of_match_table =3D of_match_clk_mt8516_aud, + }, +}; +builtin_platform_driver(clk_mt8516_aud_drv); =20 -} -CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init); +MODULE_DESCRIPTION("MediaTek MT8516 audiosys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index 51e6948cb54b..ad59e932d4aa 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 MediaTek Inc. * Author: James Liao * Fabien Parent + * Copyright (c) 2023 Collabora Ltd. */ =20 #include @@ -10,6 +11,7 @@ #include #include #include +#include =20 #include "clk-gate.h" #include "clk-mtk.h" @@ -638,59 +640,41 @@ static const struct mtk_gate top_clks[] __initconst = =3D { GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), }; =20 -static void __init mtk_topckgen_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } +static const struct mtk_clk_desc topck_desc =3D { + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .fixed_clks =3D fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .divider_clks =3D top_adj_divs, + .num_divider_clks =3D ARRAY_SIZE(top_adj_divs), + .clk_lock =3D &mt8516_clk_lock, +}; =20 - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); +static const struct mtk_clk_desc infra_desc =3D { + .composite_clks =3D ifr_muxes, + .num_composite_clks =3D ARRAY_SIZE(ifr_muxes), + .clk_lock =3D &mt8516_clk_lock, +}; =20 - mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), - clk_data); - mtk_clk_register_gates(NULL, node, top_clks, ARRAY_SIZE(top_clks), clk_da= ta); +static const struct of_device_id of_match_clk_mt8516[] =3D { + { .compatible =3D "mediatek,mt8516-topckgen", .data =3D &topck_desc }, + { .compatible =3D "mediatek,mt8516-infracfg", .data =3D &infra_desc }, + { /* sentinel */ } +}; =20 - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(NULL, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8516_clk_lock, clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt8516_clk_lock, clk_data); +static struct platform_driver clk_mt8516_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8516", + .of_match_table =3D of_match_clk_mt8516, + }, +}; +module_platform_driver(clk_mt8516_drv); =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init= ); - -static void __init mtk_infracfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data =3D mtk_alloc_clk_data(CLK_IFR_NR_CLK); - - mtk_clk_register_composites(NULL, ifr_muxes, - ARRAY_SIZE(ifr_muxes), base, - &mt8516_clk_lock, clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init= ); +MODULE_DESCRIPTION("MediaTek MT8516 clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FC7EC05027 for ; Mon, 20 Feb 2023 15:03:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231989AbjBTPDq (ORCPT ); Mon, 20 Feb 2023 10:03:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231366AbjBTPDJ (ORCPT ); Mon, 20 Feb 2023 10:03:09 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B3FF2056F; Mon, 20 Feb 2023 07:02:00 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 247566602169; Mon, 20 Feb 2023 15:01:57 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905318; bh=xhH2n5XmogkvcmxqMIc1jv/49UOL0BNOcn3TahthPEQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SD2itfCWdRnDqBZ21k4ppPSVXMDmvQJvvQF2dlNYAN27aVsNgYAyrgv/e5Nwl328t uczMzQsb1aGogzvk6dVIzR3X4msY8DrS1XdbDpQVDBwUkpfq1b8d/f57bEnlP0tHxe 0h9IqMO8g5dC2O/Y7VcTtCYUONUAyenAXDa3ZrN0+OSixdaC9/rnsBNq0mgOyzbqNb q4/OY/wSa4AhTbyhadM/xLZ05qywfgFwM7mqhiiO0W1q/wl47hY40CTCL57FXQMno0 AV6A3VaTxr39Xy27vUFNXPAd3tfwfv0Zs0NDAobA9SOE77n2BW/NwgIlc2wzc2CHDO 29DUB7Fe61SPA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 30/55] clk: mediatek: mt8516: Allow building clock drivers as modules Date: Mon, 20 Feb 2023 16:00:46 +0100 Message-Id: <20230220150111.77897-31-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that all MT8516 drivers have been converted to platform driver, change the configuration options to tristate. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 2d14855dd37e..b9c0a9e21cf1 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -743,7 +743,7 @@ config COMMON_CLK_MT8365_VENC This driver supports MediaTek MT8365 venc clocks. =20 config COMMON_CLK_MT8516 - bool "Clock driver for MediaTek MT8516" + tristate "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -751,7 +751,7 @@ config COMMON_CLK_MT8516 This driver supports MediaTek MT8516 clocks. =20 config COMMON_CLK_MT8516_AUDSYS - bool "Clock driver for MediaTek MT8516 audsys" + tristate "Clock driver for MediaTek MT8516 audsys" depends on COMMON_CLK_MT8516 help This driver supports MediaTek MT8516 audsys clocks. --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA6CEC64EC4 for ; Mon, 20 Feb 2023 15:04:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbjBTPEk (ORCPT ); Mon, 20 Feb 2023 10:04:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232845AbjBTPDz (ORCPT ); Mon, 20 Feb 2023 10:03:55 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E9871F91D; Mon, 20 Feb 2023 07:02:31 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 848276602168; Mon, 20 Feb 2023 15:01:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905319; bh=ZplN2YRj3Q1FQDaVBRSPFITk+c8951vtcnNlTkqRLoc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gNja5X8I2Xa0vjCsknaEVkaWxsXlak9965fMGPxempAmDxaNRS6NW5+art/yCM4Gx LstgMSiIfJUReqFl4TeFXFdfgZg+TPBQgsi+XDr6J1P66A0w2XSl1+F0srPj/B/iA+ awn/0cZ4VEXdCZwRVtuXz7Ju0Zg477OcLxHhxkvV9sLZ31vZIcMmyXENpsLbAUtVtv n7Z4jNadSjXKM+VSHMqMHA4QsBtus4SGaRMVkBjAbPoc5kvKyiucMhKWxaiAVih1d1 TllgIVd+Ak8iavgXkq1YIJqq13RDV+a8itDi3bV7JmFbPkFXeDl5nyJdZdaRvzTo5u S3gxaTYfo7YAg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 31/55] clk: mediatek: Propagate struct device with mtk_clk_register_dividers() Date: Mon, 20 Feb 2023 16:00:47 +0100 Message-Id: <20230220150111.77897-32-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Propagate struct device for divider clocks registered through clk-mtk helpers to be able to get runtime PM support for MTK clocks. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2701.c | 2 +- drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mtk.c | 8 +++++--- drivers/clk/mediatek/clk-mtk.h | 3 ++- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index dfe328f7a44b..e9c27b1364b6 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -681,7 +681,7 @@ static int mtk_topckgen_init(struct platform_device *pd= ev) ARRAY_SIZE(top_muxes), base, &mt2701_clk_lock, clk_data); =20 - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), + mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_di= vs), base, &mt2701_clk_lock, clk_data); =20 mtk_clk_register_gates(&pdev->dev, node, top_clks, diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8167-apmixedsys.c index ebd90365be5f..27597fdeb6e9 100644 --- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -109,7 +109,7 @@ static int clk_mt8167_apmixed_probe(struct platform_dev= ice *pdev) if (ret) return ret; =20 - ret =3D mtk_clk_register_dividers(adj_divs, ARRAY_SIZE(adj_divs), base, + ret =3D mtk_clk_register_dividers(dev, adj_divs, ARRAY_SIZE(adj_divs), ba= se, &mt8167_apmixed_clk_lock, clk_data); if (ret) goto unregister_plls; diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 39bd360aa0c9..7013340e116e 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -393,7 +393,8 @@ void mtk_clk_unregister_composites(const struct mtk_com= posite *mcs, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_composites); =20 -int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, +int mtk_clk_register_dividers(struct device *dev, + const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_hw_onecell_data *clk_data) { @@ -412,7 +413,7 @@ int mtk_clk_register_dividers(const struct mtk_clk_divi= der *mcds, int num, continue; } =20 - hw =3D clk_hw_register_divider(NULL, mcd->name, mcd->parent_name, + hw =3D clk_hw_register_divider(dev, mcd->name, mcd->parent_name, mcd->flags, base + mcd->div_reg, mcd->div_shift, mcd->div_width, mcd->clk_divider_flags, lock); =20 @@ -535,7 +536,8 @@ static int __mtk_clk_simple_probe(struct platform_devic= e *pdev, } =20 if (mcd->divider_clks) { - r =3D mtk_clk_register_dividers(mcd->divider_clks, + r =3D mtk_clk_register_dividers(&pdev->dev, + mcd->divider_clks, mcd->num_divider_clks, base, mcd->clk_lock, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 554aecdc1015..b7a751861fce 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -202,7 +202,8 @@ struct mtk_clk_divider { .div_width =3D _width, \ } =20 -int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, +int mtk_clk_register_dividers(struct device *dev, + const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_hw_onecell_data *clk_data); void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int n= um, --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5ECEC05027 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905321; bh=TVcQKRssdAc9o2ZUajNdAkJkyh364bF8fOa6lB5Z2tE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P4BwsqZ98UmXU7C5jgu1fXk5B6wVJFJExMfeTa9u1C/Auv2vDycXxcHbCli8cjfNZ MV4efjnqCQclipqwM6Af+KWoaaDSSmaHqhrfESFHD19pFIpXAuJyI+qc3WY9qRFm4l zVGUzscQDpe8EMGqNGLGo9NVwdAxs+HMe6PXwZ7lmfyirtVreh4GWZL0IGbAVKVDA1 Wx0FCgL792SQin4x4/wfJXdl+pX5d9rN+48fQXZvC2kWHfEzL7Si7AjUT/xdb8hevH 5y+zQiitmOGXkQuZsReXnDuX56KFJM89TI9F4oFa33T2kHDMWsFWIJpnwXjBSAsuc6 nDSHFb6j2bqRA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 32/55] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set critical clock Date: Mon, 20 Feb 2023 16:00:48 +0100 Message-Id: <20230220150111.77897-33-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of calling clk_prepare_enable() at probe time, add the PLL_AO flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediat= ek/clk-mt7986-apmixed.c index 62080ee4dbe3..227ca572056e 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -42,7 +42,7 @@ "clkxtal") =20 static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32, + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, 0x0200, 4, 0, 0x0204, 0), PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, 0x0210, 4, 0, 0x0214, 0), @@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(struct platform_devic= e *pdev) =20 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); =20 - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { pr_err("%s(): could not register clock provider: %d\n", --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B034C05027 for ; Mon, 20 Feb 2023 15:03:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232878AbjBTPDw (ORCPT ); Mon, 20 Feb 2023 10:03:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232324AbjBTPDM (ORCPT ); Mon, 20 Feb 2023 10:03:12 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EABD320566; Mon, 20 Feb 2023 07:02:06 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4B471660217C; Mon, 20 Feb 2023 15:02:01 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905322; bh=nMAANSk/UU2xOIRce888SbMKzruYSYk/80xNpYz3QzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q8mlHYT8MoU2+0Q1UdFtn+JqCIcJxZOtnO/VzVdQWoJYpCWpgSAswePEeOmau9c2O wx/hD+1ByATJfL31LrzG5EUE/YC5R1HSrqHx63D82kDI6UHTDv9lUb8cDoJ9eLAGpP ++Q9dqgQynoGs1gcbSiiVRw5ilJI3qfKNU5/U1w0f6KCfftVMpZGxpNWxuZQSMFj9B J1tRdblkdU9JdDdh7d98fHFSvsGeOL5P2pGt3UocB3oLFGN25OF3wVZDnDYwsukICf XpAJYhxdVUN9UG+ni/GgGT3TbGIHhnVEo2NI3y5XKcGJz1CrmtjtNErF299cdB6VlB RU+NrjH/DmGiw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 33/55] clk: mediatek: mt7986-infracfg: Migrate to common probe mechanism Date: Mon, 20 Feb 2023 16:00:49 +0100 Message-Id: <20230220150111.77897-34-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert this driver to use the common mtk_clk_simple_probe() mechanism. While at it, also use module_platform_driver() instead, as this driver just gained a .remove() callback during the conversion. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt7986-infracfg.c | 61 ++++++---------------- 1 file changed, 17 insertions(+), 44 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/media= tek/clk-mt7986-infracfg.c index 0a4bf87ee160..0299faad0733 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -157,57 +157,30 @@ static const struct mtk_gate infra_clks[] =3D { GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15), }; =20 -static int clk_mt7986_infracfg_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - void __iomem *base; - int nr =3D ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + - ARRAY_SIZE(infra_clks); - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data =3D mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(&pdev->dev, infra_muxes, - ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; - -} +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .factor_clks =3D infra_divs, + .num_factor_clks =3D ARRAY_SIZE(infra_divs), + .mux_clks =3D infra_muxes, + .num_mux_clks =3D ARRAY_SIZE(infra_muxes), + .clk_lock =3D &mt7986_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt7986_infracfg[] =3D { - { .compatible =3D "mediatek,mt7986-infracfg", }, - {} + { .compatible =3D "mediatek,mt7986-infracfg", .data =3D &infra_desc }, + { /* sentinel */ } }; =20 static struct platform_driver clk_mt7986_infracfg_drv =3D { - .probe =3D clk_mt7986_infracfg_probe, .driver =3D { .name =3D "clk-mt7986-infracfg", .of_match_table =3D of_match_clk_mt7986_infracfg, }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; -builtin_platform_driver(clk_mt7986_infracfg_drv); +module_platform_driver(clk_mt7986_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT7986 infracfg clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15D55C636CC for ; Mon, 20 Feb 2023 15:15:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230366AbjBTPPu (ORCPT ); Mon, 20 Feb 2023 10:15:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232295AbjBTPPr (ORCPT ); Mon, 20 Feb 2023 10:15:47 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2997620D0B; Mon, 20 Feb 2023 07:15:18 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B33A1660216B; Mon, 20 Feb 2023 15:02:02 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905323; bh=wjEUtgV2dUeTl5IMzfSzsq0GbF+vXUsOW/+em9uek+4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e6N3VplNu288eHct3tIIpUnqutJ5Es2UPyb2fPd0Nn1QIUPEJ+zgD+lGu3jInZQcN zPmdLbc7WU2wd7ZZ7NSMnUCEwHznoSGlskxtVJ0MvDRVyr3aM4hc9se/K724hj9V2+ rbp88Khy5JLAUGJwfzU/jSTGaeD3mHR7jERUIEvX63Q0wwACJSC46N5e8fBUI5xvKx KW1/qbGlpp1CekZ4z8kXFvfkKFIS28Pj5uRVHgYngvQXqvEpScYdvSHGJCMno7tGLy QlFt61dVjudozGMkAYNxF+Ub1hQDoUAuhQda1VELb8C1/C0B9bxr6tPZe3wmr3/8P6 XmnDvW+Cxgqcg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 34/55] clk: mediatek: mt7986-eth: Migrate to common probe mechanism Date: Mon, 20 Feb 2023 16:00:50 +0100 Message-Id: <20230220150111.77897-35-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert this driver to use the common mtk_clk_simple_probe() mechanism. While at it, also remove __initconst annotations (as these structures are used also at runtime). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt7986-eth.c | 83 +++++++++++---------------- 1 file changed, 32 insertions(+), 51 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/c= lk-mt7986-eth.c index e04bc6845ea6..138ba0a47221 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -25,7 +25,7 @@ static const struct mtk_gate_regs sgmii0_cg_regs =3D { #define GATE_SGMII0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 -static const struct mtk_gate sgmii0_clks[] __initconst =3D { +static const struct mtk_gate sgmii0_clks[] =3D { GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3), GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4), @@ -41,7 +41,7 @@ static const struct mtk_gate_regs sgmii1_cg_regs =3D { #define GATE_SGMII1(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_= no_setclr_inv) =20 -static const struct mtk_gate sgmii1_clks[] __initconst =3D { +static const struct mtk_gate sgmii1_clks[] =3D { GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3), GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4), @@ -57,7 +57,7 @@ static const struct mtk_gate_regs eth_cg_regs =3D { #define GATE_ETH(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_= setclr_inv) =20 -static const struct mtk_gate eth_clks[] __initconst =3D { +static const struct mtk_gate eth_clks[] =3D { GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7), GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8), @@ -65,56 +65,37 @@ static const struct mtk_gate eth_clks[] __initconst =3D= { GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15), }; =20 -static void __init mtk_sgmiisys_0_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - mtk_clk_register_gates(NULL, node, sgmii0_clks, - ARRAY_SIZE(sgmii0_clks), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0", - mtk_sgmiisys_0_init); - -static void __init mtk_sgmiisys_1_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - mtk_clk_register_gates(NULL, node, sgmii1_clks, - ARRAY_SIZE(sgmii1_clks), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1", - mtk_sgmiisys_1_init); +static const struct mtk_clk_desc eth_desc =3D { + .clks =3D eth_clks, + .num_clks =3D ARRAY_SIZE(eth_clks), +}; =20 -static void __init mtk_ethsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; +static const struct mtk_clk_desc sgmii0_desc =3D { + .clks =3D sgmii0_clks, + .num_clks =3D ARRAY_SIZE(sgmii0_clks), +}; =20 - clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); +static const struct mtk_clk_desc sgmii1_desc =3D { + .clks =3D sgmii1_clks, + .num_clks =3D ARRAY_SIZE(sgmii1_clks), +}; =20 - mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_da= ta); +static const struct of_device_id of_match_clk_mt7986_eth[] =3D { + { .compatible =3D "mediatek,mt7986-ethsys", .data =3D ð_desc }, + { .compatible =3D "mediatek,mt7986-sgmiisys_0", .data =3D &sgmii0_desc }, + { .compatible =3D "mediatek,mt7986-sgmiisys_1", .data =3D &sgmii1_desc }, + { /* sentinel */ } +}; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static struct platform_driver clk_mt7986_eth_drv =3D { + .driver =3D { + .name =3D "clk-mt7986-eth", + .of_match_table =3D of_match_clk_mt7986_eth, + }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt7986_eth_drv); =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init); +MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D13A4C64EC4 for ; Mon, 20 Feb 2023 15:05:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232952AbjBTPFL (ORCPT ); Mon, 20 Feb 2023 10:05:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232940AbjBTPEj (ORCPT ); Mon, 20 Feb 2023 10:04:39 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98A5C1CF4B; Mon, 20 Feb 2023 07:02:52 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 20AEB6602172; Mon, 20 Feb 2023 15:02:04 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905325; bh=hL7jk0inioKV0EMEo8KXoi4jYj0DK6gbA/IvRiEA10E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BCCrZrtISbv78jN3xePmjApEtQjTH3bRbCN/TTdmVQ9JahE2207aR3Hy9KFnUI3gO jYf6rISc1OSOVEiKDncth7kJWBwCQOHWzNy2cEyOh7LF1YqIm5RHjL0OBGt4cnqxNd +cCmTixtDOnjA0ckdGVOSiBcQCbAUhz4pAIRqLGkXlMfbQq16RxftGXp0EOR3MvhxQ dBOSuoT7cb7VyojSuLSQwIb3i1PoWuTGphmpg344gcHcduGXgXa5wJfn48NYCVG/Vp l60aviNhqTsDbp7a9FXoTptYG8R/F37tMNA9cHYwaM228pbAJWl5kn0Eo3lryMWMtf MMaXzETH3sG5w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 35/55] clk: mediatek: mt8186-mcu: Migrate to common probe mechanism Date: Mon, 20 Feb 2023 16:00:51 +0100 Message-Id: <20230220150111.77897-36-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert MT8186 MCUSYS clocks to the common mtk_clk_simple_probe(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8186-mcu.c | 68 +++++---------------------- 1 file changed, 13 insertions(+), 55 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8186-mcu.c b/drivers/clk/mediatek/c= lk-mt8186-mcu.c index e52a2d986c99..895856df95df 100644 --- a/drivers/clk/mediatek/clk-mt8186-mcu.c +++ b/drivers/clk/mediatek/clk-mt8186-mcu.c @@ -43,67 +43,25 @@ static struct mtk_composite mcu_muxes[] =3D { MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents,= 0x2E0, 9, 2), }; =20 -static const struct of_device_id of_match_clk_mt8186_mcu[] =3D { - { .compatible =3D "mediatek,mt8186-mcusys", }, - {} +static const struct mtk_clk_desc mcu_desc =3D { + .composite_clks =3D mcu_muxes, + .num_composite_clks =3D ARRAY_SIZE(mcu_muxes), }; =20 -static int clk_mt8186_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - void __iomem *base; - - clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); - if (!clk_data) - return -ENOMEM; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - r =3D PTR_ERR(base); - goto free_mcu_data; - } - - r =3D mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - NULL, clk_data); - if (r) - goto free_mcu_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_composite_muxes; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_composite_muxes: - mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data); -free_mcu_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8186_mcu_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - struct device_node *node =3D pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} +static const struct of_device_id of_match_clk_mt8186_mcu[] =3D { + { .compatible =3D "mediatek,mt8186-mcusys", .data =3D &mcu_desc }, + { /* sentinel */} +}; =20 static struct platform_driver clk_mt8186_mcu_drv =3D { - .probe =3D clk_mt8186_mcu_probe, - .remove =3D clk_mt8186_mcu_remove, .driver =3D { .name =3D "clk-mt8186-mcu", .of_match_table =3D of_match_clk_mt8186_mcu, }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; -builtin_platform_driver(clk_mt8186_mcu_drv); +module_platform_driver(clk_mt8186_mcu_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 mcusys clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F8A6C64EC7 for ; Mon, 20 Feb 2023 15:04:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232294AbjBTPEB (ORCPT ); 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OGFLwKNRAwhU7mb+ocJp0Tc3BNQxaJ/WcCayJjttqOzW9LiOLvwWuBD3PpCpAknf/ gmGsOKMBAwjQ/PZOEkCwrFVcv62cmJWbip1AOWBJMnbI4N39iIkwJohScaC+2W9ntf xayL5l6MxI6KZPlP6yT2XhdBTpcWwoRWvDiyhHtN0uvfz6+h9fvdZjtjJYYyHtcuD8 tCl7J7kHKGSWpJvySDN1sUpFRGc5TH6fWzRKeOmV/9tE/9uP0ahMKO3arik+DRM/f/ wBRCHvQOGdPchm095qf2VzQJRnCMoo7EVetmBsWuOsOPKBDieBITRBrAbFawGOszhy +dicVTzbWAdXg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 36/55] clk: mediatek: Switch to module_platform_driver() where possible Date: Mon, 20 Feb 2023 16:00:52 +0100 Message-Id: <20230220150111.77897-37-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Lots of clock drivers have got both .probe() and a .remove() callbacks: switch from builtin_platform_driver() to module_platform_driver() so that we actually register the .remove() callback. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2701-aud.c | 3 +-- drivers/clk/mediatek/clk-mt2701-bdp.c | 3 +-- drivers/clk/mediatek/clk-mt2701-eth.c | 3 +-- drivers/clk/mediatek/clk-mt2701-g3d.c | 3 +-- drivers/clk/mediatek/clk-mt2701-hif.c | 3 +-- drivers/clk/mediatek/clk-mt2701-img.c | 3 +-- drivers/clk/mediatek/clk-mt2701-mm.c | 3 +-- drivers/clk/mediatek/clk-mt2701-vdec.c | 3 +-- drivers/clk/mediatek/clk-mt2712-bdp.c | 3 +-- drivers/clk/mediatek/clk-mt2712-img.c | 3 +-- drivers/clk/mediatek/clk-mt2712-jpgdec.c | 3 +-- drivers/clk/mediatek/clk-mt2712-mfg.c | 3 +-- drivers/clk/mediatek/clk-mt2712-mm.c | 3 +-- drivers/clk/mediatek/clk-mt2712-vdec.c | 3 +-- drivers/clk/mediatek/clk-mt2712-venc.c | 3 +-- drivers/clk/mediatek/clk-mt6765-audio.c | 3 +-- drivers/clk/mediatek/clk-mt6765-cam.c | 3 +-- drivers/clk/mediatek/clk-mt6765-img.c | 3 +-- drivers/clk/mediatek/clk-mt6765-mipi0a.c | 3 +-- drivers/clk/mediatek/clk-mt6765-mm.c | 3 +-- drivers/clk/mediatek/clk-mt6765-vcodec.c | 3 +-- drivers/clk/mediatek/clk-mt6797-img.c | 3 +-- drivers/clk/mediatek/clk-mt6797-mm.c | 3 +-- drivers/clk/mediatek/clk-mt6797-vdec.c | 3 +-- drivers/clk/mediatek/clk-mt6797-venc.c | 3 +-- drivers/clk/mediatek/clk-mt7622-aud.c | 3 +-- drivers/clk/mediatek/clk-mt7622-eth.c | 3 +-- drivers/clk/mediatek/clk-mt7622-hif.c | 3 +-- drivers/clk/mediatek/clk-mt7629-hif.c | 3 +-- drivers/clk/mediatek/clk-mt7981-infracfg.c | 2 +- drivers/clk/mediatek/clk-mt7981-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt7986-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8167-mm.c | 2 +- drivers/clk/mediatek/clk-mt8173-mm.c | 3 +-- drivers/clk/mediatek/clk-mt8183-audio.c | 3 +-- drivers/clk/mediatek/clk-mt8183-cam.c | 3 +-- drivers/clk/mediatek/clk-mt8183-img.c | 3 +-- drivers/clk/mediatek/clk-mt8183-ipu0.c | 3 +-- drivers/clk/mediatek/clk-mt8183-ipu1.c | 3 +-- drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 3 +-- drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 3 +-- drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 3 +-- drivers/clk/mediatek/clk-mt8183-mm.c | 3 +-- drivers/clk/mediatek/clk-mt8183-vdec.c | 3 +-- drivers/clk/mediatek/clk-mt8183-venc.c | 3 +-- drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8186-cam.c | 2 +- drivers/clk/mediatek/clk-mt8186-img.c | 2 +- drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c | 2 +- drivers/clk/mediatek/clk-mt8186-infra_ao.c | 2 +- drivers/clk/mediatek/clk-mt8186-ipe.c | 2 +- drivers/clk/mediatek/clk-mt8186-mdp.c | 2 +- drivers/clk/mediatek/clk-mt8186-mfg.c | 2 +- drivers/clk/mediatek/clk-mt8186-mm.c | 2 +- drivers/clk/mediatek/clk-mt8186-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8186-vdec.c | 2 +- drivers/clk/mediatek/clk-mt8186-venc.c | 2 +- drivers/clk/mediatek/clk-mt8186-wpe.c | 2 +- drivers/clk/mediatek/clk-mt8192-aud.c | 3 +-- drivers/clk/mediatek/clk-mt8192-cam.c | 3 +-- drivers/clk/mediatek/clk-mt8192-img.c | 3 +-- drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c | 3 +-- drivers/clk/mediatek/clk-mt8192-ipe.c | 3 +-- drivers/clk/mediatek/clk-mt8192-mdp.c | 3 +-- drivers/clk/mediatek/clk-mt8192-mfg.c | 3 +-- drivers/clk/mediatek/clk-mt8192-mm.c | 3 +-- drivers/clk/mediatek/clk-mt8192-msdc.c | 3 +-- drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 3 +-- drivers/clk/mediatek/clk-mt8192-vdec.c | 3 +-- drivers/clk/mediatek/clk-mt8192-venc.c | 3 +-- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 2 +- drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 2 +- drivers/clk/mediatek/clk-mt8195-cam.c | 2 +- drivers/clk/mediatek/clk-mt8195-ccu.c | 2 +- drivers/clk/mediatek/clk-mt8195-img.c | 2 +- drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c | 2 +- drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 +- drivers/clk/mediatek/clk-mt8195-ipe.c | 2 +- drivers/clk/mediatek/clk-mt8195-mfg.c | 2 +- drivers/clk/mediatek/clk-mt8195-peri_ao.c | 2 +- drivers/clk/mediatek/clk-mt8195-scp_adsp.c | 2 +- drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8195-vdec.c | 2 +- drivers/clk/mediatek/clk-mt8195-vdo0.c | 3 ++- drivers/clk/mediatek/clk-mt8195-vdo1.c | 3 ++- drivers/clk/mediatek/clk-mt8195-venc.c | 2 +- drivers/clk/mediatek/clk-mt8195-vpp0.c | 2 +- drivers/clk/mediatek/clk-mt8195-vpp1.c | 2 +- drivers/clk/mediatek/clk-mt8195-wpe.c | 2 +- drivers/clk/mediatek/clk-mt8365-apu.c | 2 +- drivers/clk/mediatek/clk-mt8365-cam.c | 2 +- drivers/clk/mediatek/clk-mt8365-mfg.c | 2 +- drivers/clk/mediatek/clk-mt8365-mm.c | 2 +- drivers/clk/mediatek/clk-mt8365-vdec.c | 2 +- drivers/clk/mediatek/clk-mt8365-venc.c | 2 +- drivers/clk/mediatek/clk-mt8516-aud.c | 2 +- 96 files changed, 98 insertions(+), 149 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index 21f7cc106bbe..cff6c3b8896f 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -163,5 +163,4 @@ static struct platform_driver clk_mt2701_aud_drv =3D { .of_match_table =3D of_match_clk_mt2701_aud, }, }; - -builtin_platform_driver(clk_mt2701_aud_drv); +module_platform_driver(clk_mt2701_aud_drv); diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/c= lk-mt2701-bdp.c index b0f057207945..dad9a35e9310 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -104,5 +104,4 @@ static struct platform_driver clk_mt2701_bdp_drv =3D { .of_match_table =3D of_match_clk_mt2701_bdp, }, }; - -builtin_platform_driver(clk_mt2701_bdp_drv); +module_platform_driver(clk_mt2701_bdp_drv); diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index 4c830ebdd761..2c4781f9141a 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,5 +58,4 @@ static struct platform_driver clk_mt2701_eth_drv =3D { .of_match_table =3D of_match_clk_mt2701_eth, }, }; - -builtin_platform_driver(clk_mt2701_eth_drv); +module_platform_driver(clk_mt2701_eth_drv); diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index ae094046890a..2fed9f96d1e5 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -57,5 +57,4 @@ static struct platform_driver clk_mt2701_g3d_drv =3D { .of_match_table =3D of_match_clk_mt2701_g3d, }, }; - -builtin_platform_driver(clk_mt2701_g3d_drv); +module_platform_driver(clk_mt2701_g3d_drv); diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index 3583bd1240d5..ac47a20047da 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -55,5 +55,4 @@ static struct platform_driver clk_mt2701_hif_drv =3D { .of_match_table =3D of_match_clk_mt2701_hif, }, }; - -builtin_platform_driver(clk_mt2701_hif_drv); +module_platform_driver(clk_mt2701_hif_drv); diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/c= lk-mt2701-img.c index eb172473f075..776f470623ca 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -52,5 +52,4 @@ static struct platform_driver clk_mt2701_img_drv =3D { .of_match_table =3D of_match_clk_mt2701_img, }, }; - -builtin_platform_driver(clk_mt2701_img_drv); +module_platform_driver(clk_mt2701_img_drv); diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/cl= k-mt2701-mm.c index 993d904d619f..f23208b8dcba 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -85,5 +85,4 @@ static struct platform_driver clk_mt2701_mm_drv =3D { }, .id_table =3D clk_mt2701_mm_id_table, }; - -builtin_platform_driver(clk_mt2701_mm_drv); +module_platform_driver(clk_mt2701_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/= clk-mt2701-vdec.c index 0f07c5d731df..57e7020aaab5 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -57,5 +57,4 @@ static struct platform_driver clk_mt2701_vdec_drv =3D { .of_match_table =3D of_match_clk_mt2701_vdec, }, }; - -builtin_platform_driver(clk_mt2701_vdec_drv); +module_platform_driver(clk_mt2701_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/c= lk-mt2712-bdp.c index 5e668651dd90..5324544039b3 100644 --- a/drivers/clk/mediatek/clk-mt2712-bdp.c +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c @@ -74,5 +74,4 @@ static struct platform_driver clk_mt2712_bdp_drv =3D { .of_match_table =3D of_match_clk_mt2712_bdp, }, }; - -builtin_platform_driver(clk_mt2712_bdp_drv); +module_platform_driver(clk_mt2712_bdp_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/c= lk-mt2712-img.c index 3ffa51384e6b..c16453c6b421 100644 --- a/drivers/clk/mediatek/clk-mt2712-img.c +++ b/drivers/clk/mediatek/clk-mt2712-img.c @@ -52,5 +52,4 @@ static struct platform_driver clk_mt2712_img_drv =3D { .of_match_table =3D of_match_clk_mt2712_img, }, }; - -builtin_platform_driver(clk_mt2712_img_drv); +module_platform_driver(clk_mt2712_img_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediate= k/clk-mt2712-jpgdec.c index 8c768d5ce24d..c1363eb5d893 100644 --- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c @@ -48,5 +48,4 @@ static struct platform_driver clk_mt2712_jpgdec_drv =3D { .of_match_table =3D of_match_clk_mt2712_jpgdec, }, }; - -builtin_platform_driver(clk_mt2712_jpgdec_drv); +module_platform_driver(clk_mt2712_jpgdec_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/c= lk-mt2712-mfg.c index 8949315c2dd2..d91d788babcf 100644 --- a/drivers/clk/mediatek/clk-mt2712-mfg.c +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c @@ -47,5 +47,4 @@ static struct platform_driver clk_mt2712_mfg_drv =3D { .of_match_table =3D of_match_clk_mt2712_mfg, }, }; - -builtin_platform_driver(clk_mt2712_mfg_drv); +module_platform_driver(clk_mt2712_mfg_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/cl= k-mt2712-mm.c index 850cef9f2009..6245b79bab90 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -126,5 +126,4 @@ static struct platform_driver clk_mt2712_mm_drv =3D { }, .id_table =3D clk_mt2712_mm_id_table, }; - -builtin_platform_driver(clk_mt2712_mm_drv); +module_platform_driver(clk_mt2712_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/= clk-mt2712-vdec.c index 572290dd43c8..1d3e65f60808 100644 --- a/drivers/clk/mediatek/clk-mt2712-vdec.c +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c @@ -60,5 +60,4 @@ static struct platform_driver clk_mt2712_vdec_drv =3D { .of_match_table =3D of_match_clk_mt2712_vdec, }, }; - -builtin_platform_driver(clk_mt2712_vdec_drv); +module_platform_driver(clk_mt2712_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/= clk-mt2712-venc.c index 9588eb03016e..09f2683f0f13 100644 --- a/drivers/clk/mediatek/clk-mt2712-venc.c +++ b/drivers/clk/mediatek/clk-mt2712-venc.c @@ -49,5 +49,4 @@ static struct platform_driver clk_mt2712_venc_drv =3D { .of_match_table =3D of_match_clk_mt2712_venc, }, }; - -builtin_platform_driver(clk_mt2712_venc_drv); +module_platform_driver(clk_mt2712_venc_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek= /clk-mt6765-audio.c index 5682e0302eee..712e0da78b4b 100644 --- a/drivers/clk/mediatek/clk-mt6765-audio.c +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -74,5 +74,4 @@ static struct platform_driver clk_mt6765_audio_drv =3D { .of_match_table =3D of_match_clk_mt6765_audio, }, }; - -builtin_platform_driver(clk_mt6765_audio_drv); +module_platform_driver(clk_mt6765_audio_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/c= lk-mt6765-cam.c index 6e7d192c19cb..0581a1f3971e 100644 --- a/drivers/clk/mediatek/clk-mt6765-cam.c +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -55,5 +55,4 @@ static struct platform_driver clk_mt6765_cam_drv =3D { .of_match_table =3D of_match_clk_mt6765_cam, }, }; - -builtin_platform_driver(clk_mt6765_cam_drv); +module_platform_driver(clk_mt6765_cam_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/c= lk-mt6765-img.c index cfbc907988af..7c605dc155eb 100644 --- a/drivers/clk/mediatek/clk-mt6765-img.c +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -51,5 +51,4 @@ static struct platform_driver clk_mt6765_img_drv =3D { .of_match_table =3D of_match_clk_mt6765_img, }, }; - -builtin_platform_driver(clk_mt6765_img_drv); +module_platform_driver(clk_mt6765_img_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediate= k/clk-mt6765-mipi0a.c index f2b9dc808480..b299db047138 100644 --- a/drivers/clk/mediatek/clk-mt6765-mipi0a.c +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -48,5 +48,4 @@ static struct platform_driver clk_mt6765_mipi0a_drv =3D { .of_match_table =3D of_match_clk_mt6765_mipi0a, }, }; - -builtin_platform_driver(clk_mt6765_mipi0a_drv); +module_platform_driver(clk_mt6765_mipi0a_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/cl= k-mt6765-mm.c index a4570c9dbefa..ec2b287cf1a3 100644 --- a/drivers/clk/mediatek/clk-mt6765-mm.c +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -77,5 +77,4 @@ static struct platform_driver clk_mt6765_mm_drv =3D { .of_match_table =3D of_match_clk_mt6765_mm, }, }; - -builtin_platform_driver(clk_mt6765_mm_drv); +module_platform_driver(clk_mt6765_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediate= k/clk-mt6765-vcodec.c index 75d72b9b4032..17355923325e 100644 --- a/drivers/clk/mediatek/clk-mt6765-vcodec.c +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -50,5 +50,4 @@ static struct platform_driver clk_mt6765_vcodec_drv =3D { .of_match_table =3D of_match_clk_mt6765_vcodec, }, }; - -builtin_platform_driver(clk_mt6765_vcodec_drv); +module_platform_driver(clk_mt6765_vcodec_drv); diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/c= lk-mt6797-img.c index 06441393478f..d46a3a3ac3ad 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -48,5 +48,4 @@ static struct platform_driver clk_mt6797_img_drv =3D { .of_match_table =3D of_match_clk_mt6797_img, }, }; - -builtin_platform_driver(clk_mt6797_img_drv); +module_platform_driver(clk_mt6797_img_drv); diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index e7a5a43f91f1..899a0e6fa988 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -98,5 +98,4 @@ static struct platform_driver clk_mt6797_mm_drv =3D { }, .id_table =3D clk_mt6797_mm_id_table, }; - -builtin_platform_driver(clk_mt6797_mm_drv); +module_platform_driver(clk_mt6797_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/= clk-mt6797-vdec.c index 8622ddd87a5b..f2b979b1ea19 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -59,5 +59,4 @@ static struct platform_driver clk_mt6797_vdec_drv =3D { .of_match_table =3D of_match_clk_mt6797_vdec, }, }; - -builtin_platform_driver(clk_mt6797_vdec_drv); +module_platform_driver(clk_mt6797_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/= clk-mt6797-venc.c index 928d611a476e..9fbf4cd5160e 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -50,5 +50,4 @@ static struct platform_driver clk_mt6797_venc_drv =3D { .of_match_table =3D of_match_clk_mt6797_venc, }, }; - -builtin_platform_driver(clk_mt6797_venc_drv); +module_platform_driver(clk_mt6797_venc_drv); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index 27c543759f2a..7cca52693a3f 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -154,5 +154,4 @@ static struct platform_driver clk_mt7622_aud_drv =3D { .of_match_table =3D of_match_clk_mt7622_aud, }, }; - -builtin_platform_driver(clk_mt7622_aud_drv); +module_platform_driver(clk_mt7622_aud_drv); diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 66b163cc1633..89e68c836d40 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -86,5 +86,4 @@ static struct platform_driver clk_mt7622_eth_drv =3D { .of_match_table =3D of_match_clk_mt7622_eth, }, }; - -builtin_platform_driver(clk_mt7622_eth_drv); +module_platform_driver(clk_mt7622_eth_drv); diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index bcd1dfc6e8e0..06ade985dfe2 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -98,5 +98,4 @@ static struct platform_driver clk_mt7622_hif_drv =3D { .of_match_table =3D of_match_clk_mt7622_hif, }, }; - -builtin_platform_driver(clk_mt7622_hif_drv); +module_platform_driver(clk_mt7622_hif_drv); diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 78d85542e4f1..79bcd91386fc 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -93,5 +93,4 @@ static struct platform_driver clk_mt7629_hif_drv =3D { .of_match_table =3D of_match_clk_mt7629_hif, }, }; - -builtin_platform_driver(clk_mt7629_hif_drv); +module_platform_driver(clk_mt7629_hif_drv); diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/media= tek/clk-mt7981-infracfg.c index 8cf5057419e8..35cd126408b6 100644 --- a/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c @@ -204,4 +204,4 @@ static struct platform_driver clk_mt7981_infracfg_drv = =3D { .of_match_table =3D of_match_clk_mt7981_infracfg, }, }; -builtin_platform_driver(clk_mt7981_infracfg_drv); +module_platform_driver(clk_mt7981_infracfg_drv); diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/media= tek/clk-mt7981-topckgen.c index 74634d65f5f6..f4c31cb1c74e 100644 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -419,4 +419,4 @@ static struct platform_driver clk_mt7981_topckgen_drv = =3D { .of_match_table =3D of_match_clk_mt7981_topckgen, }, }; -builtin_platform_driver(clk_mt7981_topckgen_drv); +module_platform_driver(clk_mt7981_topckgen_drv); diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/media= tek/clk-mt7986-topckgen.c index dff9976fa689..dacaf5492286 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -313,4 +313,4 @@ static struct platform_driver clk_mt7986_topckgen_drv = =3D { .of_match_table =3D of_match_clk_mt7986_topckgen, }, }; -builtin_platform_driver(clk_mt7986_topckgen_drv); +module_platform_driver(clk_mt7986_topckgen_drv); diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/cl= k-mt8167-mm.c index 5a5192d0dc45..de6c2283b695 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -92,4 +92,4 @@ static struct platform_driver clk_mt8167_mm_drv =3D { }, .id_table =3D clk_mt8167_mm_id_table, }; -builtin_platform_driver(clk_mt8167_mm_drv); +module_platform_driver(clk_mt8167_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/cl= k-mt8173-mm.c index 435cfae25492..ba51c22cbe7a 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -107,8 +107,7 @@ static struct platform_driver clk_mt8173_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, .remove =3D mtk_clk_pdev_remove, }; - -builtin_platform_driver(clk_mt8173_mm_drv); +module_platform_driver(clk_mt8173_mm_drv); =20 MODULE_DESCRIPTION("MediaTek MT8173 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek= /clk-mt8183-audio.c index 3f1630290b93..24cc2178c769 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -106,5 +106,4 @@ static struct platform_driver clk_mt8183_audio_drv =3D { .of_match_table =3D of_match_clk_mt8183_audio, }, }; - -builtin_platform_driver(clk_mt8183_audio_drv); +module_platform_driver(clk_mt8183_audio_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-cam.c b/drivers/clk/mediatek/c= lk-mt8183-cam.c index 6907b1a6a824..7ff183da0075 100644 --- a/drivers/clk/mediatek/clk-mt8183-cam.c +++ b/drivers/clk/mediatek/clk-mt8183-cam.c @@ -56,5 +56,4 @@ static struct platform_driver clk_mt8183_cam_drv =3D { .of_match_table =3D of_match_clk_mt8183_cam, }, }; - -builtin_platform_driver(clk_mt8183_cam_drv); +module_platform_driver(clk_mt8183_cam_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/c= lk-mt8183-img.c index 8d884425d79f..e4a9d3201e33 100644 --- a/drivers/clk/mediatek/clk-mt8183-img.c +++ b/drivers/clk/mediatek/clk-mt8183-img.c @@ -56,5 +56,4 @@ static struct platform_driver clk_mt8183_img_drv =3D { .of_match_table =3D of_match_clk_mt8183_img, }, }; - -builtin_platform_driver(clk_mt8183_img_drv); +module_platform_driver(clk_mt8183_img_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu0.c b/drivers/clk/mediatek/= clk-mt8183-ipu0.c index 953a8a33d048..68d4cda89d6f 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu0.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu0.c @@ -49,5 +49,4 @@ static struct platform_driver clk_mt8183_ipu_core0_drv = =3D { .of_match_table =3D of_match_clk_mt8183_ipu_core0, }, }; - -builtin_platform_driver(clk_mt8183_ipu_core0_drv); +module_platform_driver(clk_mt8183_ipu_core0_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu1.c b/drivers/clk/mediatek/= clk-mt8183-ipu1.c index 221d12265974..50950bed9226 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu1.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu1.c @@ -49,5 +49,4 @@ static struct platform_driver clk_mt8183_ipu_core1_drv = =3D { .of_match_table =3D of_match_clk_mt8183_ipu_core1, }, }; - -builtin_platform_driver(clk_mt8183_ipu_core1_drv); +module_platform_driver(clk_mt8183_ipu_core1_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c b/drivers/clk/mediat= ek/clk-mt8183-ipu_adl.c index 8c4fd96df821..2044d5c664b8 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c @@ -47,5 +47,4 @@ static struct platform_driver clk_mt8183_ipu_adl_drv =3D { .of_match_table =3D of_match_clk_mt8183_ipu_adl, }, }; - -builtin_platform_driver(clk_mt8183_ipu_adl_drv); +module_platform_driver(clk_mt8183_ipu_adl_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c b/drivers/clk/media= tek/clk-mt8183-ipu_conn.c index 14a4c3ff82a1..6e7833656c9a 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c @@ -116,5 +116,4 @@ static struct platform_driver clk_mt8183_ipu_conn_drv = =3D { .of_match_table =3D of_match_clk_mt8183_ipu_conn, }, }; - -builtin_platform_driver(clk_mt8183_ipu_conn_drv); +module_platform_driver(clk_mt8183_ipu_conn_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8183-mfgcfg.c index 730c9ae5ea12..5a71ef094e03 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -48,5 +48,4 @@ static struct platform_driver clk_mt8183_mfg_drv =3D { .of_match_table =3D of_match_clk_mt8183_mfg, }, }; - -builtin_platform_driver(clk_mt8183_mfg_drv); +module_platform_driver(clk_mt8183_mfg_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/cl= k-mt8183-mm.c index 669dcdd66efb..25a04f311dc3 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -100,5 +100,4 @@ static struct platform_driver clk_mt8183_mm_drv =3D { }, .id_table =3D clk_mt8183_mm_id_table, }; - -builtin_platform_driver(clk_mt8183_mm_drv); +module_platform_driver(clk_mt8183_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/= clk-mt8183-vdec.c index c294e50b96b7..4c56d02a9d34 100644 --- a/drivers/clk/mediatek/clk-mt8183-vdec.c +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c @@ -60,5 +60,4 @@ static struct platform_driver clk_mt8183_vdec_drv =3D { .of_match_table =3D of_match_clk_mt8183_vdec, }, }; - -builtin_platform_driver(clk_mt8183_vdec_drv); +module_platform_driver(clk_mt8183_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt8183-venc.c b/drivers/clk/mediatek/= clk-mt8183-venc.c index 0051c5d92fc5..5b86d7d42613 100644 --- a/drivers/clk/mediatek/clk-mt8183-venc.c +++ b/drivers/clk/mediatek/clk-mt8183-venc.c @@ -52,5 +52,4 @@ static struct platform_driver clk_mt8183_venc_drv =3D { .of_match_table =3D of_match_clk_mt8183_venc, }, }; - -builtin_platform_driver(clk_mt8183_venc_drv); +module_platform_driver(clk_mt8183_venc_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index 9fded5020ca4..ab500b985900 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -192,4 +192,4 @@ static struct platform_driver clk_mt8186_apmixed_drv = =3D { .of_match_table =3D of_match_clk_mt8186_apmixed, }, }; -builtin_platform_driver(clk_mt8186_apmixed_drv); +module_platform_driver(clk_mt8186_apmixed_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-cam.c b/drivers/clk/mediatek/c= lk-mt8186-cam.c index 9ec345a2ce66..220c8af7848e 100644 --- a/drivers/clk/mediatek/clk-mt8186-cam.c +++ b/drivers/clk/mediatek/clk-mt8186-cam.c @@ -87,4 +87,4 @@ static struct platform_driver clk_mt8186_cam_drv =3D { .of_match_table =3D of_match_clk_mt8186_cam, }, }; -builtin_platform_driver(clk_mt8186_cam_drv); +module_platform_driver(clk_mt8186_cam_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-img.c b/drivers/clk/mediatek/c= lk-mt8186-img.c index 08a625475aee..bac0e52bd51c 100644 --- a/drivers/clk/mediatek/clk-mt8186-img.c +++ b/drivers/clk/mediatek/clk-mt8186-img.c @@ -65,4 +65,4 @@ static struct platform_driver clk_mt8186_img_drv =3D { .of_match_table =3D of_match_clk_mt8186_img, }, }; -builtin_platform_driver(clk_mt8186_img_drv); +module_platform_driver(clk_mt8186_img_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8186-imp_iic_wrap.c index 47f2e480a05e..9301dc3e86fb 100644 --- a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c @@ -64,4 +64,4 @@ static struct platform_driver clk_mt8186_imp_iic_wrap_drv= =3D { .of_match_table =3D of_match_clk_mt8186_imp_iic_wrap, }, }; -builtin_platform_driver(clk_mt8186_imp_iic_wrap_drv); +module_platform_driver(clk_mt8186_imp_iic_wrap_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-infra_ao.c b/drivers/clk/media= tek/clk-mt8186-infra_ao.c index df2a6bd1aefa..e705d57032a6 100644 --- a/drivers/clk/mediatek/clk-mt8186-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8186-infra_ao.c @@ -236,4 +236,4 @@ static struct platform_driver clk_mt8186_infra_ao_drv = =3D { .of_match_table =3D of_match_clk_mt8186_infra_ao, }, }; -builtin_platform_driver(clk_mt8186_infra_ao_drv); +module_platform_driver(clk_mt8186_infra_ao_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-ipe.c b/drivers/clk/mediatek/c= lk-mt8186-ipe.c index 8fca148effa6..36f6338f8237 100644 --- a/drivers/clk/mediatek/clk-mt8186-ipe.c +++ b/drivers/clk/mediatek/clk-mt8186-ipe.c @@ -52,4 +52,4 @@ static struct platform_driver clk_mt8186_ipe_drv =3D { .of_match_table =3D of_match_clk_mt8186_ipe, }, }; -builtin_platform_driver(clk_mt8186_ipe_drv); +module_platform_driver(clk_mt8186_ipe_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-mdp.c b/drivers/clk/mediatek/c= lk-mt8186-mdp.c index 05174088ef20..faf5cdc7523f 100644 --- a/drivers/clk/mediatek/clk-mt8186-mdp.c +++ b/drivers/clk/mediatek/clk-mt8186-mdp.c @@ -77,4 +77,4 @@ static struct platform_driver clk_mt8186_mdp_drv =3D { .of_match_table =3D of_match_clk_mt8186_mdp, }, }; -builtin_platform_driver(clk_mt8186_mdp_drv); +module_platform_driver(clk_mt8186_mdp_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-mfg.c b/drivers/clk/mediatek/c= lk-mt8186-mfg.c index 0142d741053a..468fa7e37074 100644 --- a/drivers/clk/mediatek/clk-mt8186-mfg.c +++ b/drivers/clk/mediatek/clk-mt8186-mfg.c @@ -46,4 +46,4 @@ static struct platform_driver clk_mt8186_mfg_drv =3D { .of_match_table =3D of_match_clk_mt8186_mfg, }, }; -builtin_platform_driver(clk_mt8186_mfg_drv); +module_platform_driver(clk_mt8186_mfg_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/cl= k-mt8186-mm.c index 6506a8b848a9..03dfb4d99930 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -75,4 +75,4 @@ static struct platform_driver clk_mt8186_mm_drv =3D { }, .id_table =3D clk_mt8186_mm_id_table, }; -builtin_platform_driver(clk_mt8186_mm_drv); +module_platform_driver(clk_mt8186_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/media= tek/clk-mt8186-topckgen.c index c6786c8b315f..7f2a59347166 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -730,4 +730,4 @@ static struct platform_driver clk_mt8186_topck_drv =3D { .of_match_table =3D of_match_clk_mt8186_topck, }, }; -builtin_platform_driver(clk_mt8186_topck_drv); +module_platform_driver(clk_mt8186_topck_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-vdec.c b/drivers/clk/mediatek/= clk-mt8186-vdec.c index 5ad7e1ae0bac..76e226be8f72 100644 --- a/drivers/clk/mediatek/clk-mt8186-vdec.c +++ b/drivers/clk/mediatek/clk-mt8186-vdec.c @@ -85,4 +85,4 @@ static struct platform_driver clk_mt8186_vdec_drv =3D { .of_match_table =3D of_match_clk_mt8186_vdec, }, }; -builtin_platform_driver(clk_mt8186_vdec_drv); +module_platform_driver(clk_mt8186_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-venc.c b/drivers/clk/mediatek/= clk-mt8186-venc.c index f5519f794c45..96c15b859e37 100644 --- a/drivers/clk/mediatek/clk-mt8186-venc.c +++ b/drivers/clk/mediatek/clk-mt8186-venc.c @@ -48,4 +48,4 @@ static struct platform_driver clk_mt8186_venc_drv =3D { .of_match_table =3D of_match_clk_mt8186_venc, }, }; -builtin_platform_driver(clk_mt8186_venc_drv); +module_platform_driver(clk_mt8186_venc_drv); diff --git a/drivers/clk/mediatek/clk-mt8186-wpe.c b/drivers/clk/mediatek/c= lk-mt8186-wpe.c index 8db3e9178a1e..dbd8a81b170d 100644 --- a/drivers/clk/mediatek/clk-mt8186-wpe.c +++ b/drivers/clk/mediatek/clk-mt8186-wpe.c @@ -48,4 +48,4 @@ static struct platform_driver clk_mt8186_wpe_drv =3D { .of_match_table =3D of_match_clk_mt8186_wpe, }, }; -builtin_platform_driver(clk_mt8186_wpe_drv); +module_platform_driver(clk_mt8186_wpe_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/c= lk-mt8192-aud.c index 29affb68e854..deb292cc9da1 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -116,5 +116,4 @@ static struct platform_driver clk_mt8192_aud_drv =3D { .of_match_table =3D of_match_clk_mt8192_aud, }, }; - -builtin_platform_driver(clk_mt8192_aud_drv); +module_platform_driver(clk_mt8192_aud_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/c= lk-mt8192-cam.c index 90b57d46eef7..00dbd0d27fbc 100644 --- a/drivers/clk/mediatek/clk-mt8192-cam.c +++ b/drivers/clk/mediatek/clk-mt8192-cam.c @@ -104,5 +104,4 @@ static struct platform_driver clk_mt8192_cam_drv =3D { .of_match_table =3D of_match_clk_mt8192_cam, }, }; - -builtin_platform_driver(clk_mt8192_cam_drv); +module_platform_driver(clk_mt8192_cam_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/c= lk-mt8192-img.c index da82d65a7650..00abbec6c666 100644 --- a/drivers/clk/mediatek/clk-mt8192-img.c +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -67,5 +67,4 @@ static struct platform_driver clk_mt8192_img_drv =3D { .of_match_table =3D of_match_clk_mt8192_img, }, }; - -builtin_platform_driver(clk_mt8192_img_drv); +module_platform_driver(clk_mt8192_img_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8192-imp_iic_wrap.c index ff8e20bb44bb..6663b70a5d47 100644 --- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c @@ -116,5 +116,4 @@ static struct platform_driver clk_mt8192_imp_iic_wrap_d= rv =3D { .of_match_table =3D of_match_clk_mt8192_imp_iic_wrap, }, }; - -builtin_platform_driver(clk_mt8192_imp_iic_wrap_drv); +module_platform_driver(clk_mt8192_imp_iic_wrap_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/c= lk-mt8192-ipe.c index 0225abe4170a..6a8d3fb7e0c5 100644 --- a/drivers/clk/mediatek/clk-mt8192-ipe.c +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c @@ -54,5 +54,4 @@ static struct platform_driver clk_mt8192_ipe_drv =3D { .of_match_table =3D of_match_clk_mt8192_ipe, }, }; - -builtin_platform_driver(clk_mt8192_ipe_drv); +module_platform_driver(clk_mt8192_ipe_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/c= lk-mt8192-mdp.c index 4675788d7816..782f83fbe97b 100644 --- a/drivers/clk/mediatek/clk-mt8192-mdp.c +++ b/drivers/clk/mediatek/clk-mt8192-mdp.c @@ -79,5 +79,4 @@ static struct platform_driver clk_mt8192_mdp_drv =3D { .of_match_table =3D of_match_clk_mt8192_mdp, }, }; - -builtin_platform_driver(clk_mt8192_mdp_drv); +module_platform_driver(clk_mt8192_mdp_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/c= lk-mt8192-mfg.c index ec5b44ffa458..c007e561f008 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -49,5 +49,4 @@ static struct platform_driver clk_mt8192_mfg_drv =3D { .of_match_table =3D of_match_clk_mt8192_mfg, }, }; - -builtin_platform_driver(clk_mt8192_mfg_drv); +module_platform_driver(clk_mt8192_mfg_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/cl= k-mt8192-mm.c index 638e6faae84c..184d7fb82abc 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -98,5 +98,4 @@ static struct platform_driver clk_mt8192_mm_drv =3D { }, .id_table =3D clk_mt8192_mm_id_table, }; - -builtin_platform_driver(clk_mt8192_mm_drv); +module_platform_driver(clk_mt8192_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/= clk-mt8192-msdc.c index a72e1b73fce8..cb21a40dfe83 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -61,5 +61,4 @@ static struct platform_driver clk_mt8192_msdc_drv =3D { .of_match_table =3D of_match_clk_mt8192_msdc, }, }; - -builtin_platform_driver(clk_mt8192_msdc_drv); +module_platform_driver(clk_mt8192_msdc_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/media= tek/clk-mt8192-scp_adsp.c index 18a8679108b8..b7aa68e6c555 100644 --- a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c @@ -47,5 +47,4 @@ static struct platform_driver clk_mt8192_scp_adsp_drv =3D= { .of_match_table =3D of_match_clk_mt8192_scp_adsp, }, }; - -builtin_platform_driver(clk_mt8192_scp_adsp_drv); +module_platform_driver(clk_mt8192_scp_adsp_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/= clk-mt8192-vdec.c index e149962dbbf9..9ddc6e99c8d7 100644 --- a/drivers/clk/mediatek/clk-mt8192-vdec.c +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -91,5 +91,4 @@ static struct platform_driver clk_mt8192_vdec_drv =3D { .of_match_table =3D of_match_clk_mt8192_vdec, }, }; - -builtin_platform_driver(clk_mt8192_vdec_drv); +module_platform_driver(clk_mt8192_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/= clk-mt8192-venc.c index 80b8bb170996..67136a341d77 100644 --- a/drivers/clk/mediatek/clk-mt8192-venc.c +++ b/drivers/clk/mediatek/clk-mt8192-venc.c @@ -50,5 +50,4 @@ static struct platform_driver clk_mt8192_venc_drv =3D { .of_match_table =3D of_match_clk_mt8192_venc, }, }; - -builtin_platform_driver(clk_mt8192_venc_drv); +module_platform_driver(clk_mt8192_venc_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index c0db31ce0741..29124ed9398b 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -230,4 +230,4 @@ static struct platform_driver clk_mt8195_apmixed_drv = =3D { .of_match_table =3D of_match_clk_mt8195_apmixed, }, }; -builtin_platform_driver(clk_mt8195_apmixed_drv); +module_platform_driver(clk_mt8195_apmixed_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/med= iatek/clk-mt8195-apusys_pll.c index 0b52f6a009c4..ca60d90e5257 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -110,4 +110,4 @@ static struct platform_driver clk_mt8195_apusys_pll_drv= =3D { .of_match_table =3D of_match_clk_mt8195_apusys_pll, }, }; -builtin_platform_driver(clk_mt8195_apusys_pll_drv); +module_platform_driver(clk_mt8195_apusys_pll_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-cam.c b/drivers/clk/mediatek/c= lk-mt8195-cam.c index e4d00fe6e757..c0fd32270a8e 100644 --- a/drivers/clk/mediatek/clk-mt8195-cam.c +++ b/drivers/clk/mediatek/clk-mt8195-cam.c @@ -140,4 +140,4 @@ static struct platform_driver clk_mt8195_cam_drv =3D { .of_match_table =3D of_match_clk_mt8195_cam, }, }; -builtin_platform_driver(clk_mt8195_cam_drv); +module_platform_driver(clk_mt8195_cam_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/c= lk-mt8195-ccu.c index 4e326b6301ba..9e8220bcdf9f 100644 --- a/drivers/clk/mediatek/clk-mt8195-ccu.c +++ b/drivers/clk/mediatek/clk-mt8195-ccu.c @@ -48,4 +48,4 @@ static struct platform_driver clk_mt8195_ccu_drv =3D { .of_match_table =3D of_match_clk_mt8195_ccu, }, }; -builtin_platform_driver(clk_mt8195_ccu_drv); +module_platform_driver(clk_mt8195_ccu_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/c= lk-mt8195-img.c index 12f5c436d075..822efce6f79b 100644 --- a/drivers/clk/mediatek/clk-mt8195-img.c +++ b/drivers/clk/mediatek/clk-mt8195-img.c @@ -94,4 +94,4 @@ static struct platform_driver clk_mt8195_img_drv =3D { .of_match_table =3D of_match_clk_mt8195_img, }, }; -builtin_platform_driver(clk_mt8195_img_drv); +module_platform_driver(clk_mt8195_img_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8195-imp_iic_wrap.c index fbc809d05072..01f8fab27c22 100644 --- a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c @@ -64,4 +64,4 @@ static struct platform_driver clk_mt8195_imp_iic_wrap_drv= =3D { .of_match_table =3D of_match_clk_mt8195_imp_iic_wrap, }, }; -builtin_platform_driver(clk_mt8195_imp_iic_wrap_drv); +module_platform_driver(clk_mt8195_imp_iic_wrap_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/media= tek/clk-mt8195-infra_ao.c index fcd410461d3b..75084251ea74 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -238,4 +238,4 @@ static struct platform_driver clk_mt8195_infra_ao_drv = =3D { .of_match_table =3D of_match_clk_mt8195_infra_ao, }, }; -builtin_platform_driver(clk_mt8195_infra_ao_drv); +module_platform_driver(clk_mt8195_infra_ao_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/c= lk-mt8195-ipe.c index b0d745cf7752..b713fea470dd 100644 --- a/drivers/clk/mediatek/clk-mt8195-ipe.c +++ b/drivers/clk/mediatek/clk-mt8195-ipe.c @@ -49,4 +49,4 @@ static struct platform_driver clk_mt8195_ipe_drv =3D { .of_match_table =3D of_match_clk_mt8195_ipe, }, }; -builtin_platform_driver(clk_mt8195_ipe_drv); +module_platform_driver(clk_mt8195_ipe_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/c= lk-mt8195-mfg.c index c94cb71bd9b9..fcd2d0b7e3c9 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -47,4 +47,4 @@ static struct platform_driver clk_mt8195_mfg_drv =3D { .of_match_table =3D of_match_clk_mt8195_mfg, }, }; -builtin_platform_driver(clk_mt8195_mfg_drv); +module_platform_driver(clk_mt8195_mfg_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-peri_ao.c b/drivers/clk/mediat= ek/clk-mt8195-peri_ao.c index 2f6b3bb657db..f66fbea2e080 100644 --- a/drivers/clk/mediatek/clk-mt8195-peri_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-peri_ao.c @@ -60,4 +60,4 @@ static struct platform_driver clk_mt8195_peri_ao_drv =3D { .of_match_table =3D of_match_clk_mt8195_peri_ao, }, }; -builtin_platform_driver(clk_mt8195_peri_ao_drv); +module_platform_driver(clk_mt8195_peri_ao_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c b/drivers/clk/media= tek/clk-mt8195-scp_adsp.c index e16c383f631b..1987172c98a4 100644 --- a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c @@ -45,4 +45,4 @@ static struct platform_driver clk_mt8195_scp_adsp_drv =3D= { .of_match_table =3D of_match_clk_mt8195_scp_adsp, }, }; -builtin_platform_driver(clk_mt8195_scp_adsp_drv); +module_platform_driver(clk_mt8195_scp_adsp_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index cf520f85de73..a9bb7e4687ec 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1340,4 +1340,4 @@ static struct platform_driver clk_mt8195_topck_drv = =3D { .of_match_table =3D of_match_clk_mt8195_topck, }, }; -builtin_platform_driver(clk_mt8195_topck_drv); +module_platform_driver(clk_mt8195_topck_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/= clk-mt8195-vdec.c index a1446b666385..a75ea99a9a4c 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdec.c +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c @@ -102,4 +102,4 @@ static struct platform_driver clk_mt8195_vdec_drv =3D { .of_match_table =3D of_match_clk_mt8195_vdec, }, }; -builtin_platform_driver(clk_mt8195_vdec_drv); +module_platform_driver(clk_mt8195_vdec_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/= clk-mt8195-vdo0.c index 492c1e133d0d..1ed152b072bd 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -102,6 +102,7 @@ static const struct platform_device_id clk_mt8195_vdo0_= id_table[] =3D { { .name =3D "clk-mt8195-vdo0", .driver_data =3D (kernel_ulong_t)&vdo0_des= c }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo0_id_table); =20 static struct platform_driver clk_mt8195_vdo0_drv =3D { .probe =3D mtk_clk_pdev_probe, @@ -111,4 +112,4 @@ static struct platform_driver clk_mt8195_vdo0_drv =3D { }, .id_table =3D clk_mt8195_vdo0_id_table, }; -builtin_platform_driver(clk_mt8195_vdo0_drv); +module_platform_driver(clk_mt8195_vdo0_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/= clk-mt8195-vdo1.c index 76e9f4496e43..cbd0a34884c7 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -129,6 +129,7 @@ static const struct platform_device_id clk_mt8195_vdo1_= id_table[] =3D { { .name =3D "clk-mt8195-vdo1", .driver_data =3D (kernel_ulong_t)&vdo1_des= c }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo1_id_table); =20 static struct platform_driver clk_mt8195_vdo1_drv =3D { .probe =3D mtk_clk_pdev_probe, @@ -138,4 +139,4 @@ static struct platform_driver clk_mt8195_vdo1_drv =3D { }, .id_table =3D clk_mt8195_vdo1_id_table, }; -builtin_platform_driver(clk_mt8195_vdo1_drv); +module_platform_driver(clk_mt8195_vdo1_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/= clk-mt8195-venc.c index 622f57804f96..8b46cbe9ce83 100644 --- a/drivers/clk/mediatek/clk-mt8195-venc.c +++ b/drivers/clk/mediatek/clk-mt8195-venc.c @@ -67,4 +67,4 @@ static struct platform_driver clk_mt8195_venc_drv =3D { .of_match_table =3D of_match_clk_mt8195_venc, }, }; -builtin_platform_driver(clk_mt8195_venc_drv); +module_platform_driver(clk_mt8195_venc_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/= clk-mt8195-vpp0.c index 15f1a081358a..ca1288b76990 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -104,4 +104,4 @@ static struct platform_driver clk_mt8195_vpp0_drv =3D { }, .id_table =3D clk_mt8195_vpp0_id_table, }; -builtin_platform_driver(clk_mt8195_vpp0_drv); +module_platform_driver(clk_mt8195_vpp0_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/= clk-mt8195-vpp1.c index 794f21cf5e65..d9a260b6ee30 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -102,4 +102,4 @@ static struct platform_driver clk_mt8195_vpp1_drv =3D { }, .id_table =3D clk_mt8195_vpp1_id_table, }; -builtin_platform_driver(clk_mt8195_vpp1_drv); +module_platform_driver(clk_mt8195_vpp1_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/c= lk-mt8195-wpe.c index b483fab10e18..8878b5ef9e44 100644 --- a/drivers/clk/mediatek/clk-mt8195-wpe.c +++ b/drivers/clk/mediatek/clk-mt8195-wpe.c @@ -141,4 +141,4 @@ static struct platform_driver clk_mt8195_wpe_drv =3D { .of_match_table =3D of_match_clk_mt8195_wpe, }, }; -builtin_platform_driver(clk_mt8195_wpe_drv); +module_platform_driver(clk_mt8195_wpe_drv); diff --git a/drivers/clk/mediatek/clk-mt8365-apu.c b/drivers/clk/mediatek/c= lk-mt8365-apu.c index 91ffe89d9721..5a594f8eccdc 100644 --- a/drivers/clk/mediatek/clk-mt8365-apu.c +++ b/drivers/clk/mediatek/clk-mt8365-apu.c @@ -51,5 +51,5 @@ static struct platform_driver clk_mt8365_apu_drv =3D { .of_match_table =3D of_match_clk_mt8365_apu, }, }; -builtin_platform_driver(clk_mt8365_apu_drv); +module_platform_driver(clk_mt8365_apu_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-cam.c b/drivers/clk/mediatek/c= lk-mt8365-cam.c index 31d5b5cd6de1..ed1d8dd7043c 100644 --- a/drivers/clk/mediatek/clk-mt8365-cam.c +++ b/drivers/clk/mediatek/clk-mt8365-cam.c @@ -53,5 +53,5 @@ static struct platform_driver clk_mt8365_cam_drv =3D { .of_match_table =3D of_match_clk_mt8365_cam, }, }; -builtin_platform_driver(clk_mt8365_cam_drv); +module_platform_driver(clk_mt8365_cam_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-mfg.c b/drivers/clk/mediatek/c= lk-mt8365-mfg.c index 587b49128b03..b3d10b017f0d 100644 --- a/drivers/clk/mediatek/clk-mt8365-mfg.c +++ b/drivers/clk/mediatek/clk-mt8365-mfg.c @@ -59,5 +59,5 @@ static struct platform_driver clk_mt8365_mfg_drv =3D { .of_match_table =3D of_match_clk_mt8365_mfg, }, }; -builtin_platform_driver(clk_mt8365_mfg_drv); +module_platform_driver(clk_mt8365_mfg_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/cl= k-mt8365-mm.c index 9569be54127c..7ae33997ba86 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -90,5 +90,5 @@ static struct platform_driver clk_mt8365_mm_drv =3D { }, .id_table =3D clk_mt8365_mm_id_table, }; -builtin_platform_driver(clk_mt8365_mm_drv); +module_platform_driver(clk_mt8365_mm_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-vdec.c b/drivers/clk/mediatek/= clk-mt8365-vdec.c index cdc678e8941c..d5caddcc5932 100644 --- a/drivers/clk/mediatek/clk-mt8365-vdec.c +++ b/drivers/clk/mediatek/clk-mt8365-vdec.c @@ -59,5 +59,5 @@ static struct platform_driver clk_mt8365_vdec_drv =3D { .of_match_table =3D of_match_clk_mt8365_vdec, }, }; -builtin_platform_driver(clk_mt8365_vdec_drv); +module_platform_driver(clk_mt8365_vdec_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-venc.c b/drivers/clk/mediatek/= clk-mt8365-venc.c index 0e080c22119d..08b7c0ee52e7 100644 --- a/drivers/clk/mediatek/clk-mt8365-venc.c +++ b/drivers/clk/mediatek/clk-mt8365-venc.c @@ -48,5 +48,5 @@ static struct platform_driver clk_mt8365_venc_drv =3D { .of_match_table =3D of_match_clk_mt8365_venc, }, }; -builtin_platform_driver(clk_mt8365_venc_drv); +module_platform_driver(clk_mt8365_venc_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/c= lk-mt8516-aud.c index 119dbbd0c3e0..5f34487aad7e 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -60,7 +60,7 @@ static struct platform_driver clk_mt8516_aud_drv =3D { .of_match_table =3D of_match_clk_mt8516_aud, }, }; -builtin_platform_driver(clk_mt8516_aud_drv); +module_platform_driver(clk_mt8516_aud_drv); =20 MODULE_DESCRIPTION("MediaTek MT8516 audiosys clocks driver"); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 651D7C64ED8 for ; Mon, 20 Feb 2023 15:04:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232745AbjBTPEI (ORCPT ); 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IfrmRG5TltDy0/SZeMcqYqJgw/h9tcjfOUIStTDxoiz3y3wyhVVdMkmrWYFFbP5iC Qd8KQHrm4I79GuviYa2EN7m80ZtRku1Hu93N50gLrkjknnm3VmjcibwvncYAXIXKd8 x9n9HKWkqIHFQVqvFVts+RM8sx8loni1zCUBq48dT3cHjiwVLfBjxinM0sNkhhwCPb GSWkq1t1VsNnQ7mKy90cd1kSpBbTqO/yE/jJ98wv/Kdtl2AUxm/JfdaKhyGZgZxtiY PAWazicrXnNnVQVi8harUc01iB7Z729ym8wBwR57juwt9l7UM0FjxKf7pmC3EeAI7P 7dYxbxhxdIgVw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 37/55] clk: mediatek: Add MODULE_LICENSE() where missing Date: Mon, 20 Feb 2023 16:00:53 +0100 Message-Id: <20230220150111.77897-38-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to successfully build clock drivers as modules it is required to declare a module license: add it where missing. While at it, also change the MODULE_LICENSE text from "GPL v2" to "GPL" (which means the same) on clk-mt7981-eth.c. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2701-aud.c | 1 + drivers/clk/mediatek/clk-mt2701-bdp.c | 1 + drivers/clk/mediatek/clk-mt2701-eth.c | 1 + drivers/clk/mediatek/clk-mt2701-g3d.c | 1 + drivers/clk/mediatek/clk-mt2701-hif.c | 1 + drivers/clk/mediatek/clk-mt2701-img.c | 1 + drivers/clk/mediatek/clk-mt2701-mm.c | 1 + drivers/clk/mediatek/clk-mt2701-vdec.c | 1 + drivers/clk/mediatek/clk-mt2701.c | 1 + drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt2712-bdp.c | 1 + drivers/clk/mediatek/clk-mt2712-img.c | 1 + drivers/clk/mediatek/clk-mt2712-jpgdec.c | 1 + drivers/clk/mediatek/clk-mt2712-mfg.c | 1 + drivers/clk/mediatek/clk-mt2712-mm.c | 1 + drivers/clk/mediatek/clk-mt2712-vdec.c | 1 + drivers/clk/mediatek/clk-mt2712-venc.c | 1 + drivers/clk/mediatek/clk-mt2712.c | 1 + drivers/clk/mediatek/clk-mt6765-audio.c | 1 + drivers/clk/mediatek/clk-mt6765-cam.c | 1 + drivers/clk/mediatek/clk-mt6765-img.c | 1 + drivers/clk/mediatek/clk-mt6765-mipi0a.c | 1 + drivers/clk/mediatek/clk-mt6765-mm.c | 1 + drivers/clk/mediatek/clk-mt6765-vcodec.c | 1 + drivers/clk/mediatek/clk-mt6765.c | 1 + drivers/clk/mediatek/clk-mt6797-img.c | 1 + drivers/clk/mediatek/clk-mt6797-mm.c | 1 + drivers/clk/mediatek/clk-mt6797-vdec.c | 1 + drivers/clk/mediatek/clk-mt6797-venc.c | 1 + drivers/clk/mediatek/clk-mt6797.c | 1 + drivers/clk/mediatek/clk-mt7622-aud.c | 1 + drivers/clk/mediatek/clk-mt7622-eth.c | 1 + drivers/clk/mediatek/clk-mt7622-hif.c | 1 + drivers/clk/mediatek/clk-mt7629-eth.c | 1 + drivers/clk/mediatek/clk-mt7629-hif.c | 1 + drivers/clk/mediatek/clk-mt7629.c | 1 + drivers/clk/mediatek/clk-mt7981-apmixed.c | 1 + drivers/clk/mediatek/clk-mt7981-eth.c | 2 +- drivers/clk/mediatek/clk-mt7981-infracfg.c | 1 + drivers/clk/mediatek/clk-mt7981-topckgen.c | 1 + drivers/clk/mediatek/clk-mt7986-apmixed.c | 1 + drivers/clk/mediatek/clk-mt7986-topckgen.c | 1 + drivers/clk/mediatek/clk-mt8135.c | 1 + drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8167-aud.c | 1 + drivers/clk/mediatek/clk-mt8167-img.c | 1 + drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 1 + drivers/clk/mediatek/clk-mt8167-mm.c | 1 + drivers/clk/mediatek/clk-mt8167-vdec.c | 1 + drivers/clk/mediatek/clk-mt8167.c | 1 + drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8183-audio.c | 1 + drivers/clk/mediatek/clk-mt8183-cam.c | 1 + drivers/clk/mediatek/clk-mt8183-img.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu0.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu1.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 1 + drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 1 + drivers/clk/mediatek/clk-mt8183-mm.c | 1 + drivers/clk/mediatek/clk-mt8183-vdec.c | 1 + drivers/clk/mediatek/clk-mt8183-venc.c | 1 + drivers/clk/mediatek/clk-mt8183.c | 1 + drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8186-cam.c | 1 + drivers/clk/mediatek/clk-mt8186-img.c | 1 + drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c | 1 + drivers/clk/mediatek/clk-mt8186-infra_ao.c | 1 + drivers/clk/mediatek/clk-mt8186-ipe.c | 1 + drivers/clk/mediatek/clk-mt8186-mdp.c | 1 + drivers/clk/mediatek/clk-mt8186-mfg.c | 1 + drivers/clk/mediatek/clk-mt8186-mm.c | 1 + drivers/clk/mediatek/clk-mt8186-topckgen.c | 1 + drivers/clk/mediatek/clk-mt8186-vdec.c | 1 + drivers/clk/mediatek/clk-mt8186-venc.c | 1 + drivers/clk/mediatek/clk-mt8186-wpe.c | 1 + drivers/clk/mediatek/clk-mt8192-aud.c | 1 + drivers/clk/mediatek/clk-mt8192-cam.c | 1 + drivers/clk/mediatek/clk-mt8192-img.c | 1 + drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c | 1 + drivers/clk/mediatek/clk-mt8192-ipe.c | 1 + drivers/clk/mediatek/clk-mt8192-mdp.c | 1 + drivers/clk/mediatek/clk-mt8192-mfg.c | 1 + drivers/clk/mediatek/clk-mt8192-mm.c | 1 + drivers/clk/mediatek/clk-mt8192-msdc.c | 1 + drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 1 + drivers/clk/mediatek/clk-mt8192-vdec.c | 1 + drivers/clk/mediatek/clk-mt8192-venc.c | 1 + drivers/clk/mediatek/clk-mt8192.c | 1 + drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 1 + drivers/clk/mediatek/clk-mt8195-cam.c | 1 + drivers/clk/mediatek/clk-mt8195-ccu.c | 1 + drivers/clk/mediatek/clk-mt8195-img.c | 1 + drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c | 1 + drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 + drivers/clk/mediatek/clk-mt8195-ipe.c | 1 + drivers/clk/mediatek/clk-mt8195-mfg.c | 1 + drivers/clk/mediatek/clk-mt8195-peri_ao.c | 1 + drivers/clk/mediatek/clk-mt8195-scp_adsp.c | 1 + drivers/clk/mediatek/clk-mt8195-topckgen.c | 1 + drivers/clk/mediatek/clk-mt8195-vdec.c | 1 + drivers/clk/mediatek/clk-mt8195-vdo0.c | 1 + drivers/clk/mediatek/clk-mt8195-vdo1.c | 1 + drivers/clk/mediatek/clk-mt8195-venc.c | 1 + drivers/clk/mediatek/clk-mt8195-vpp0.c | 1 + drivers/clk/mediatek/clk-mt8195-vpp1.c | 1 + drivers/clk/mediatek/clk-mt8195-wpe.c | 1 + drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 1 + 109 files changed, 109 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index cff6c3b8896f..113ab5b0bf8d 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -164,3 +164,4 @@ static struct platform_driver clk_mt2701_aud_drv =3D { }, }; module_platform_driver(clk_mt2701_aud_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/c= lk-mt2701-bdp.c index dad9a35e9310..e7b43329d305 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -105,3 +105,4 @@ static struct platform_driver clk_mt2701_bdp_drv =3D { }, }; module_platform_driver(clk_mt2701_bdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index 2c4781f9141a..d30567ac4ff1 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -59,3 +59,4 @@ static struct platform_driver clk_mt2701_eth_drv =3D { }, }; module_platform_driver(clk_mt2701_eth_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 2fed9f96d1e5..6f881eabdc67 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -58,3 +58,4 @@ static struct platform_driver clk_mt2701_g3d_drv =3D { }, }; module_platform_driver(clk_mt2701_g3d_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index ac47a20047da..b2ee73c4de4e 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -56,3 +56,4 @@ static struct platform_driver clk_mt2701_hif_drv =3D { }, }; module_platform_driver(clk_mt2701_hif_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/c= lk-mt2701-img.c index 776f470623ca..35a5fd938a6e 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -53,3 +53,4 @@ static struct platform_driver clk_mt2701_img_drv =3D { }, }; module_platform_driver(clk_mt2701_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/cl= k-mt2701-mm.c index f23208b8dcba..75611d0ab865 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -86,3 +86,4 @@ static struct platform_driver clk_mt2701_mm_drv =3D { .id_table =3D clk_mt2701_mm_id_table, }; module_platform_driver(clk_mt2701_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/= clk-mt2701-vdec.c index 57e7020aaab5..dca4335a52a7 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -58,3 +58,4 @@ static struct platform_driver clk_mt2701_vdec_drv =3D { }, }; module_platform_driver(clk_mt2701_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index e9c27b1364b6..d3097d9f0c7a 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -1032,3 +1032,4 @@ static int __init clk_mt2701_init(void) } =20 arch_initcall(clk_mt2701_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c index 2f4061c9a59e..eade747d2812 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -164,3 +164,4 @@ static struct platform_driver clk_mt2712_apmixed_drv = =3D { }, }; module_platform_driver(clk_mt2712_apmixed_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/c= lk-mt2712-bdp.c index 5324544039b3..d4979f2fb1d3 100644 --- a/drivers/clk/mediatek/clk-mt2712-bdp.c +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c @@ -75,3 +75,4 @@ static struct platform_driver clk_mt2712_bdp_drv =3D { }, }; module_platform_driver(clk_mt2712_bdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/c= lk-mt2712-img.c index c16453c6b421..cd2d2af6bd56 100644 --- a/drivers/clk/mediatek/clk-mt2712-img.c +++ b/drivers/clk/mediatek/clk-mt2712-img.c @@ -53,3 +53,4 @@ static struct platform_driver clk_mt2712_img_drv =3D { }, }; module_platform_driver(clk_mt2712_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediate= k/clk-mt2712-jpgdec.c index c1363eb5d893..815be759e7c9 100644 --- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c @@ -49,3 +49,4 @@ static struct platform_driver clk_mt2712_jpgdec_drv =3D { }, }; module_platform_driver(clk_mt2712_jpgdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/c= lk-mt2712-mfg.c index d91d788babcf..9f958fadca86 100644 --- a/drivers/clk/mediatek/clk-mt2712-mfg.c +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c @@ -48,3 +48,4 @@ static struct platform_driver clk_mt2712_mfg_drv =3D { }, }; module_platform_driver(clk_mt2712_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/cl= k-mt2712-mm.c index 6245b79bab90..2649d67f2a56 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -127,3 +127,4 @@ static struct platform_driver clk_mt2712_mm_drv =3D { .id_table =3D clk_mt2712_mm_id_table, }; module_platform_driver(clk_mt2712_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/= clk-mt2712-vdec.c index 1d3e65f60808..1cb150fa7ab4 100644 --- a/drivers/clk/mediatek/clk-mt2712-vdec.c +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c @@ -61,3 +61,4 @@ static struct platform_driver clk_mt2712_vdec_drv =3D { }, }; module_platform_driver(clk_mt2712_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/= clk-mt2712-venc.c index 09f2683f0f13..4073fa6c040f 100644 --- a/drivers/clk/mediatek/clk-mt2712-venc.c +++ b/drivers/clk/mediatek/clk-mt2712-venc.c @@ -50,3 +50,4 @@ static struct platform_driver clk_mt2712_venc_drv =3D { }, }; module_platform_driver(clk_mt2712_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index d0e6a4fbfa99..b2cf91622ebf 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1001,3 +1001,4 @@ static struct platform_driver clk_mt2712_drv =3D { }, }; module_platform_driver(clk_mt2712_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek= /clk-mt6765-audio.c index 712e0da78b4b..c1fecf22f8ad 100644 --- a/drivers/clk/mediatek/clk-mt6765-audio.c +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -75,3 +75,4 @@ static struct platform_driver clk_mt6765_audio_drv =3D { }, }; module_platform_driver(clk_mt6765_audio_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/c= lk-mt6765-cam.c index 0581a1f3971e..15737c8f6b69 100644 --- a/drivers/clk/mediatek/clk-mt6765-cam.c +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -56,3 +56,4 @@ static struct platform_driver clk_mt6765_cam_drv =3D { }, }; module_platform_driver(clk_mt6765_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/c= lk-mt6765-img.c index 7c605dc155eb..7e421f4d01b8 100644 --- a/drivers/clk/mediatek/clk-mt6765-img.c +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -52,3 +52,4 @@ static struct platform_driver clk_mt6765_img_drv =3D { }, }; module_platform_driver(clk_mt6765_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediate= k/clk-mt6765-mipi0a.c index b299db047138..17186a308e94 100644 --- a/drivers/clk/mediatek/clk-mt6765-mipi0a.c +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -49,3 +49,4 @@ static struct platform_driver clk_mt6765_mipi0a_drv =3D { }, }; module_platform_driver(clk_mt6765_mipi0a_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/cl= k-mt6765-mm.c index ec2b287cf1a3..af2213db17cb 100644 --- a/drivers/clk/mediatek/clk-mt6765-mm.c +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -78,3 +78,4 @@ static struct platform_driver clk_mt6765_mm_drv =3D { }, }; module_platform_driver(clk_mt6765_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediate= k/clk-mt6765-vcodec.c index 17355923325e..48014cc71d9f 100644 --- a/drivers/clk/mediatek/clk-mt6765-vcodec.c +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -51,3 +51,4 @@ static struct platform_driver clk_mt6765_vcodec_drv =3D { }, }; module_platform_driver(clk_mt6765_vcodec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index 0c20ce678350..61f93b6fdf8b 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -873,3 +873,4 @@ static int __init clk_mt6765_init(void) } =20 arch_initcall(clk_mt6765_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/c= lk-mt6797-img.c index d46a3a3ac3ad..22779829370f 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -49,3 +49,4 @@ static struct platform_driver clk_mt6797_img_drv =3D { }, }; module_platform_driver(clk_mt6797_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index 899a0e6fa988..8722fae10de9 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -99,3 +99,4 @@ static struct platform_driver clk_mt6797_mm_drv =3D { .id_table =3D clk_mt6797_mm_id_table, }; module_platform_driver(clk_mt6797_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/= clk-mt6797-vdec.c index f2b979b1ea19..c5a82d4a958b 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -60,3 +60,4 @@ static struct platform_driver clk_mt6797_vdec_drv =3D { }, }; module_platform_driver(clk_mt6797_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/= clk-mt6797-venc.c index 9fbf4cd5160e..afdd288d313a 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -51,3 +51,4 @@ static struct platform_driver clk_mt6797_venc_drv =3D { }, }; module_platform_driver(clk_mt6797_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index 17b23ee4faee..4094fd75d16e 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -703,3 +703,4 @@ static int __init clk_mt6797_init(void) } =20 arch_initcall(clk_mt6797_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index 7cca52693a3f..4e14a4ff465a 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -155,3 +155,4 @@ static struct platform_driver clk_mt7622_aud_drv =3D { }, }; module_platform_driver(clk_mt7622_aud_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 89e68c836d40..4475d0846176 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -87,3 +87,4 @@ static struct platform_driver clk_mt7622_eth_drv =3D { }, }; module_platform_driver(clk_mt7622_eth_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index 06ade985dfe2..19f394af1132 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -99,3 +99,4 @@ static struct platform_driver clk_mt7622_hif_drv =3D { }, }; module_platform_driver(clk_mt7622_hif_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index 719a47fef798..ee84a3de7f2c 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -154,3 +154,4 @@ static struct platform_driver clk_mt7629_eth_drv =3D { }; =20 builtin_platform_driver(clk_mt7629_eth_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 79bcd91386fc..464c4131d98a 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -94,3 +94,4 @@ static struct platform_driver clk_mt7629_hif_drv =3D { }, }; module_platform_driver(clk_mt7629_hif_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index 09c85fda43d8..f3279f002e93 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -693,3 +693,4 @@ static int clk_mt7629_init(void) } =20 arch_initcall(clk_mt7629_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediat= ek/clk-mt7981-apmixed.c index 52b7123232bf..53c974c66f89 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -100,3 +100,4 @@ static struct platform_driver clk_mt7981_apmixed_drv = =3D { }, }; builtin_platform_driver(clk_mt7981_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-eth.c b/drivers/clk/mediatek/c= lk-mt7981-eth.c index 773350911be2..f27fadd6bf94 100644 --- a/drivers/clk/mediatek/clk-mt7981-eth.c +++ b/drivers/clk/mediatek/clk-mt7981-eth.c @@ -115,4 +115,4 @@ static struct platform_driver clk_mt7981_eth_drv =3D { }, }; module_platform_driver(clk_mt7981_eth_drv); -MODULE_LICENSE("GPL v2"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/media= tek/clk-mt7981-infracfg.c index 35cd126408b6..d1709323d34e 100644 --- a/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c @@ -205,3 +205,4 @@ static struct platform_driver clk_mt7981_infracfg_drv = =3D { }, }; module_platform_driver(clk_mt7981_infracfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/media= tek/clk-mt7981-topckgen.c index f4c31cb1c74e..e09ffc22b13a 100644 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -420,3 +420,4 @@ static struct platform_driver clk_mt7981_topckgen_drv = =3D { }, }; module_platform_driver(clk_mt7981_topckgen_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediat= ek/clk-mt7986-apmixed.c index 227ca572056e..dc949ed1b587 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -98,3 +98,4 @@ static struct platform_driver clk_mt7986_apmixed_drv =3D { }, }; builtin_platform_driver(clk_mt7986_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/media= tek/clk-mt7986-topckgen.c index dacaf5492286..af9df453d6d7 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -314,3 +314,4 @@ static struct platform_driver clk_mt7986_topckgen_drv = =3D { }, }; module_platform_driver(clk_mt7986_topckgen_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 97a115d2c3da..98165b1f7c97 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -638,3 +638,4 @@ static void __init mtk_apmixedsys_init(struct device_no= de *node) } CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", mtk_apmixedsys_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8167-apmixedsys.c index 27597fdeb6e9..5d8b5093ed02 100644 --- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -141,3 +141,4 @@ static struct platform_driver clk_mt8167_apmixed_drv = =3D { }, }; builtin_platform_driver(clk_mt8167_apmixed_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index 8869c53da79c..63736642f383 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -62,3 +62,4 @@ static struct platform_driver clk_mt8167_audsys_drv =3D { }, }; module_platform_driver(clk_mt8167_audsys_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index 6a068f2a9dce..c2537e149aa8 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -54,3 +54,4 @@ static struct platform_driver clk_mt8167_imgsys_drv =3D { }, }; module_platform_driver(clk_mt8167_imgsys_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 7fcb944134b6..340c608e7ddb 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -52,3 +52,4 @@ static struct platform_driver clk_mt8167_mfgcfg_drv =3D { }, }; module_platform_driver(clk_mt8167_mfgcfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/cl= k-mt8167-mm.c index de6c2283b695..0344f9c98d36 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -93,3 +93,4 @@ static struct platform_driver clk_mt8167_mm_drv =3D { .id_table =3D clk_mt8167_mm_id_table, }; module_platform_driver(clk_mt8167_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index b3eccc2eca58..35b0380f22dc 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -61,3 +61,4 @@ static struct platform_driver clk_mt8167_vdec_drv =3D { }, }; module_platform_driver(clk_mt8167_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index 507e1ebe3ba8..d9a837686865 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -893,3 +893,4 @@ static struct platform_driver clk_mt8167_drv =3D { }, }; module_platform_driver(clk_mt8167_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8183-apmixedsys.c index e66e90163bb4..5addda17211f 100644 --- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -191,3 +191,4 @@ static struct platform_driver clk_mt8183_apmixed_drv = =3D { }, }; builtin_platform_driver(clk_mt8183_apmixed_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek= /clk-mt8183-audio.c index 24cc2178c769..fe510f02dadb 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -107,3 +107,4 @@ static struct platform_driver clk_mt8183_audio_drv =3D { }, }; module_platform_driver(clk_mt8183_audio_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-cam.c b/drivers/clk/mediatek/c= lk-mt8183-cam.c index 7ff183da0075..7ecbfc50e8fe 100644 --- a/drivers/clk/mediatek/clk-mt8183-cam.c +++ b/drivers/clk/mediatek/clk-mt8183-cam.c @@ -57,3 +57,4 @@ static struct platform_driver clk_mt8183_cam_drv =3D { }, }; module_platform_driver(clk_mt8183_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/c= lk-mt8183-img.c index e4a9d3201e33..e75d6e6205f9 100644 --- a/drivers/clk/mediatek/clk-mt8183-img.c +++ b/drivers/clk/mediatek/clk-mt8183-img.c @@ -57,3 +57,4 @@ static struct platform_driver clk_mt8183_img_drv =3D { }, }; module_platform_driver(clk_mt8183_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu0.c b/drivers/clk/mediatek/= clk-mt8183-ipu0.c index 68d4cda89d6f..d1dd76e7eafd 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu0.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu0.c @@ -50,3 +50,4 @@ static struct platform_driver clk_mt8183_ipu_core0_drv = =3D { }, }; module_platform_driver(clk_mt8183_ipu_core0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu1.c b/drivers/clk/mediatek/= clk-mt8183-ipu1.c index 50950bed9226..0b4906cca119 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu1.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu1.c @@ -50,3 +50,4 @@ static struct platform_driver clk_mt8183_ipu_core1_drv = =3D { }, }; module_platform_driver(clk_mt8183_ipu_core1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c b/drivers/clk/mediat= ek/clk-mt8183-ipu_adl.c index 2044d5c664b8..32a82ec965ef 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c @@ -48,3 +48,4 @@ static struct platform_driver clk_mt8183_ipu_adl_drv =3D { }, }; module_platform_driver(clk_mt8183_ipu_adl_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c b/drivers/clk/media= tek/clk-mt8183-ipu_conn.c index 6e7833656c9a..1e2ebc0eab8b 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c @@ -117,3 +117,4 @@ static struct platform_driver clk_mt8183_ipu_conn_drv = =3D { }, }; module_platform_driver(clk_mt8183_ipu_conn_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8183-mfgcfg.c index 5a71ef094e03..20cdbd74817f 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -49,3 +49,4 @@ static struct platform_driver clk_mt8183_mfg_drv =3D { }, }; module_platform_driver(clk_mt8183_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/cl= k-mt8183-mm.c index 25a04f311dc3..a76e44ebf322 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -101,3 +101,4 @@ static struct platform_driver clk_mt8183_mm_drv =3D { .id_table =3D clk_mt8183_mm_id_table, }; module_platform_driver(clk_mt8183_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/= clk-mt8183-vdec.c index 4c56d02a9d34..0182745e2a18 100644 --- a/drivers/clk/mediatek/clk-mt8183-vdec.c +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c @@ -61,3 +61,4 @@ static struct platform_driver clk_mt8183_vdec_drv =3D { }, }; module_platform_driver(clk_mt8183_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-venc.c b/drivers/clk/mediatek/= clk-mt8183-venc.c index 5b86d7d42613..c840e6ebe375 100644 --- a/drivers/clk/mediatek/clk-mt8183-venc.c +++ b/drivers/clk/mediatek/clk-mt8183-venc.c @@ -53,3 +53,4 @@ static struct platform_driver clk_mt8183_venc_drv =3D { }, }; module_platform_driver(clk_mt8183_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 02176ee97cd2..5ae0f1f9ca0a 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -878,3 +878,4 @@ static struct platform_driver clk_mt8183_drv =3D { }, }; module_platform_driver(clk_mt8183_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index ab500b985900..e429d2cdc84a 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -193,3 +193,4 @@ static struct platform_driver clk_mt8186_apmixed_drv = =3D { }, }; module_platform_driver(clk_mt8186_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-cam.c b/drivers/clk/mediatek/c= lk-mt8186-cam.c index 220c8af7848e..90d91d045909 100644 --- a/drivers/clk/mediatek/clk-mt8186-cam.c +++ b/drivers/clk/mediatek/clk-mt8186-cam.c @@ -88,3 +88,4 @@ static struct platform_driver clk_mt8186_cam_drv =3D { }, }; module_platform_driver(clk_mt8186_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-img.c b/drivers/clk/mediatek/c= lk-mt8186-img.c index bac0e52bd51c..11314dba4e41 100644 --- a/drivers/clk/mediatek/clk-mt8186-img.c +++ b/drivers/clk/mediatek/clk-mt8186-img.c @@ -66,3 +66,4 @@ static struct platform_driver clk_mt8186_img_drv =3D { }, }; module_platform_driver(clk_mt8186_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8186-imp_iic_wrap.c index 9301dc3e86fb..f8d1ee294f09 100644 --- a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c @@ -65,3 +65,4 @@ static struct platform_driver clk_mt8186_imp_iic_wrap_drv= =3D { }, }; module_platform_driver(clk_mt8186_imp_iic_wrap_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-infra_ao.c b/drivers/clk/media= tek/clk-mt8186-infra_ao.c index e705d57032a6..766c8e6bcf8d 100644 --- a/drivers/clk/mediatek/clk-mt8186-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8186-infra_ao.c @@ -237,3 +237,4 @@ static struct platform_driver clk_mt8186_infra_ao_drv = =3D { }, }; module_platform_driver(clk_mt8186_infra_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-ipe.c b/drivers/clk/mediatek/c= lk-mt8186-ipe.c index 36f6338f8237..0876440839df 100644 --- a/drivers/clk/mediatek/clk-mt8186-ipe.c +++ b/drivers/clk/mediatek/clk-mt8186-ipe.c @@ -53,3 +53,4 @@ static struct platform_driver clk_mt8186_ipe_drv =3D { }, }; module_platform_driver(clk_mt8186_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mdp.c b/drivers/clk/mediatek/c= lk-mt8186-mdp.c index faf5cdc7523f..194f20f16f8c 100644 --- a/drivers/clk/mediatek/clk-mt8186-mdp.c +++ b/drivers/clk/mediatek/clk-mt8186-mdp.c @@ -78,3 +78,4 @@ static struct platform_driver clk_mt8186_mdp_drv =3D { }, }; module_platform_driver(clk_mt8186_mdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mfg.c b/drivers/clk/mediatek/c= lk-mt8186-mfg.c index 468fa7e37074..f16d3c44ef41 100644 --- a/drivers/clk/mediatek/clk-mt8186-mfg.c +++ b/drivers/clk/mediatek/clk-mt8186-mfg.c @@ -47,3 +47,4 @@ static struct platform_driver clk_mt8186_mfg_drv =3D { }, }; module_platform_driver(clk_mt8186_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/cl= k-mt8186-mm.c index 03dfb4d99930..9e9853a2ea91 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -76,3 +76,4 @@ static struct platform_driver clk_mt8186_mm_drv =3D { .id_table =3D clk_mt8186_mm_id_table, }; module_platform_driver(clk_mt8186_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/media= tek/clk-mt8186-topckgen.c index 7f2a59347166..a48172d9c5ab 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -731,3 +731,4 @@ static struct platform_driver clk_mt8186_topck_drv =3D { }, }; module_platform_driver(clk_mt8186_topck_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-vdec.c b/drivers/clk/mediatek/= clk-mt8186-vdec.c index 76e226be8f72..877ca9d8ff65 100644 --- a/drivers/clk/mediatek/clk-mt8186-vdec.c +++ b/drivers/clk/mediatek/clk-mt8186-vdec.c @@ -86,3 +86,4 @@ static struct platform_driver clk_mt8186_vdec_drv =3D { }, }; module_platform_driver(clk_mt8186_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-venc.c b/drivers/clk/mediatek/= clk-mt8186-venc.c index 96c15b859e37..a89e82285d4c 100644 --- a/drivers/clk/mediatek/clk-mt8186-venc.c +++ b/drivers/clk/mediatek/clk-mt8186-venc.c @@ -49,3 +49,4 @@ static struct platform_driver clk_mt8186_venc_drv =3D { }, }; module_platform_driver(clk_mt8186_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-wpe.c b/drivers/clk/mediatek/c= lk-mt8186-wpe.c index dbd8a81b170d..fba55f08129c 100644 --- a/drivers/clk/mediatek/clk-mt8186-wpe.c +++ b/drivers/clk/mediatek/clk-mt8186-wpe.c @@ -49,3 +49,4 @@ static struct platform_driver clk_mt8186_wpe_drv =3D { }, }; module_platform_driver(clk_mt8186_wpe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/c= lk-mt8192-aud.c index deb292cc9da1..9b14d8514b4f 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -117,3 +117,4 @@ static struct platform_driver clk_mt8192_aud_drv =3D { }, }; module_platform_driver(clk_mt8192_aud_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/c= lk-mt8192-cam.c index 00dbd0d27fbc..321693aff33f 100644 --- a/drivers/clk/mediatek/clk-mt8192-cam.c +++ b/drivers/clk/mediatek/clk-mt8192-cam.c @@ -105,3 +105,4 @@ static struct platform_driver clk_mt8192_cam_drv =3D { }, }; module_platform_driver(clk_mt8192_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/c= lk-mt8192-img.c index 00abbec6c666..b2c148ead7f8 100644 --- a/drivers/clk/mediatek/clk-mt8192-img.c +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -68,3 +68,4 @@ static struct platform_driver clk_mt8192_img_drv =3D { }, }; module_platform_driver(clk_mt8192_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8192-imp_iic_wrap.c index 6663b70a5d47..fd731eb6d62e 100644 --- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c @@ -117,3 +117,4 @@ static struct platform_driver clk_mt8192_imp_iic_wrap_d= rv =3D { }, }; module_platform_driver(clk_mt8192_imp_iic_wrap_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/c= lk-mt8192-ipe.c index 6a8d3fb7e0c5..3fd37977ea16 100644 --- a/drivers/clk/mediatek/clk-mt8192-ipe.c +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c @@ -55,3 +55,4 @@ static struct platform_driver clk_mt8192_ipe_drv =3D { }, }; module_platform_driver(clk_mt8192_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/c= lk-mt8192-mdp.c index 782f83fbe97b..817e8bf4543b 100644 --- a/drivers/clk/mediatek/clk-mt8192-mdp.c +++ b/drivers/clk/mediatek/clk-mt8192-mdp.c @@ -80,3 +80,4 @@ static struct platform_driver clk_mt8192_mdp_drv =3D { }, }; module_platform_driver(clk_mt8192_mdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/c= lk-mt8192-mfg.c index c007e561f008..7f77e2d8b765 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -50,3 +50,4 @@ static struct platform_driver clk_mt8192_mfg_drv =3D { }, }; module_platform_driver(clk_mt8192_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/cl= k-mt8192-mm.c index 184d7fb82abc..3e81018a038b 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -99,3 +99,4 @@ static struct platform_driver clk_mt8192_mm_drv =3D { .id_table =3D clk_mt8192_mm_id_table, }; module_platform_driver(clk_mt8192_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/= clk-mt8192-msdc.c index cb21a40dfe83..cde8c88673e4 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -62,3 +62,4 @@ static struct platform_driver clk_mt8192_msdc_drv =3D { }, }; module_platform_driver(clk_mt8192_msdc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/media= tek/clk-mt8192-scp_adsp.c index b7aa68e6c555..df086b95d447 100644 --- a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c @@ -48,3 +48,4 @@ static struct platform_driver clk_mt8192_scp_adsp_drv =3D= { }, }; module_platform_driver(clk_mt8192_scp_adsp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/= clk-mt8192-vdec.c index 9ddc6e99c8d7..2ea8b6d4d405 100644 --- a/drivers/clk/mediatek/clk-mt8192-vdec.c +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -92,3 +92,4 @@ static struct platform_driver clk_mt8192_vdec_drv =3D { }, }; module_platform_driver(clk_mt8192_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/= clk-mt8192-venc.c index 67136a341d77..d73c12bc2ae9 100644 --- a/drivers/clk/mediatek/clk-mt8192-venc.c +++ b/drivers/clk/mediatek/clk-mt8192-venc.c @@ -51,3 +51,4 @@ static struct platform_driver clk_mt8192_venc_drv =3D { }, }; module_platform_driver(clk_mt8192_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 0f9f10172148..35afe496b1c1 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1242,3 +1242,4 @@ static int __init clk_mt8192_init(void) } =20 arch_initcall(clk_mt8192_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index 29124ed9398b..75cc4d7a39f9 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -231,3 +231,4 @@ static struct platform_driver clk_mt8195_apmixed_drv = =3D { }, }; module_platform_driver(clk_mt8195_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/med= iatek/clk-mt8195-apusys_pll.c index ca60d90e5257..b167b8d31bcc 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -111,3 +111,4 @@ static struct platform_driver clk_mt8195_apusys_pll_drv= =3D { }, }; module_platform_driver(clk_mt8195_apusys_pll_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-cam.c b/drivers/clk/mediatek/c= lk-mt8195-cam.c index c0fd32270a8e..c515650214bd 100644 --- a/drivers/clk/mediatek/clk-mt8195-cam.c +++ b/drivers/clk/mediatek/clk-mt8195-cam.c @@ -141,3 +141,4 @@ static struct platform_driver clk_mt8195_cam_drv =3D { }, }; module_platform_driver(clk_mt8195_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/c= lk-mt8195-ccu.c index 9e8220bcdf9f..a86f848a785d 100644 --- a/drivers/clk/mediatek/clk-mt8195-ccu.c +++ b/drivers/clk/mediatek/clk-mt8195-ccu.c @@ -49,3 +49,4 @@ static struct platform_driver clk_mt8195_ccu_drv =3D { }, }; module_platform_driver(clk_mt8195_ccu_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/c= lk-mt8195-img.c index 822efce6f79b..214baa2bc974 100644 --- a/drivers/clk/mediatek/clk-mt8195-img.c +++ b/drivers/clk/mediatek/clk-mt8195-img.c @@ -95,3 +95,4 @@ static struct platform_driver clk_mt8195_img_drv =3D { }, }; module_platform_driver(clk_mt8195_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8195-imp_iic_wrap.c index 01f8fab27c22..191f482186ae 100644 --- a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c @@ -65,3 +65,4 @@ static struct platform_driver clk_mt8195_imp_iic_wrap_drv= =3D { }, }; module_platform_driver(clk_mt8195_imp_iic_wrap_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/media= tek/clk-mt8195-infra_ao.c index 75084251ea74..6ad72a320d5e 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -239,3 +239,4 @@ static struct platform_driver clk_mt8195_infra_ao_drv = =3D { }, }; module_platform_driver(clk_mt8195_infra_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/c= lk-mt8195-ipe.c index b713fea470dd..b547a99b4ad9 100644 --- a/drivers/clk/mediatek/clk-mt8195-ipe.c +++ b/drivers/clk/mediatek/clk-mt8195-ipe.c @@ -50,3 +50,4 @@ static struct platform_driver clk_mt8195_ipe_drv =3D { }, }; module_platform_driver(clk_mt8195_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/c= lk-mt8195-mfg.c index fcd2d0b7e3c9..75cf643ab885 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -48,3 +48,4 @@ static struct platform_driver clk_mt8195_mfg_drv =3D { }, }; module_platform_driver(clk_mt8195_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-peri_ao.c b/drivers/clk/mediat= ek/clk-mt8195-peri_ao.c index f66fbea2e080..7d65a478182d 100644 --- a/drivers/clk/mediatek/clk-mt8195-peri_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-peri_ao.c @@ -61,3 +61,4 @@ static struct platform_driver clk_mt8195_peri_ao_drv =3D { }, }; module_platform_driver(clk_mt8195_peri_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c b/drivers/clk/media= tek/clk-mt8195-scp_adsp.c index 1987172c98a4..24e09339ed7d 100644 --- a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c @@ -46,3 +46,4 @@ static struct platform_driver clk_mt8195_scp_adsp_drv =3D= { }, }; module_platform_driver(clk_mt8195_scp_adsp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index a9bb7e4687ec..adc6bb7ce750 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1341,3 +1341,4 @@ static struct platform_driver clk_mt8195_topck_drv = =3D { }, }; module_platform_driver(clk_mt8195_topck_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/= clk-mt8195-vdec.c index a75ea99a9a4c..f9e2bd402627 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdec.c +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c @@ -103,3 +103,4 @@ static struct platform_driver clk_mt8195_vdec_drv =3D { }, }; module_platform_driver(clk_mt8195_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/= clk-mt8195-vdo0.c index 1ed152b072bd..509780750e43 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -113,3 +113,4 @@ static struct platform_driver clk_mt8195_vdo0_drv =3D { .id_table =3D clk_mt8195_vdo0_id_table, }; module_platform_driver(clk_mt8195_vdo0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/= clk-mt8195-vdo1.c index cbd0a34884c7..0a5214a1ed25 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -140,3 +140,4 @@ static struct platform_driver clk_mt8195_vdo1_drv =3D { .id_table =3D clk_mt8195_vdo1_id_table, }; module_platform_driver(clk_mt8195_vdo1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/= clk-mt8195-venc.c index 8b46cbe9ce83..d050d87bb3f2 100644 --- a/drivers/clk/mediatek/clk-mt8195-venc.c +++ b/drivers/clk/mediatek/clk-mt8195-venc.c @@ -68,3 +68,4 @@ static struct platform_driver clk_mt8195_venc_drv =3D { }, }; module_platform_driver(clk_mt8195_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/= clk-mt8195-vpp0.c index ca1288b76990..84805a114387 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -105,3 +105,4 @@ static struct platform_driver clk_mt8195_vpp0_drv =3D { .id_table =3D clk_mt8195_vpp0_id_table, }; module_platform_driver(clk_mt8195_vpp0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/= clk-mt8195-vpp1.c index d9a260b6ee30..3e91dfed2996 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -103,3 +103,4 @@ static struct platform_driver clk_mt8195_vpp1_drv =3D { .id_table =3D clk_mt8195_vpp1_id_table, }; module_platform_driver(clk_mt8195_vpp1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/c= lk-mt8195-wpe.c index 8878b5ef9e44..52cebe297abf 100644 --- a/drivers/clk/mediatek/clk-mt8195-wpe.c +++ b/drivers/clk/mediatek/clk-mt8195-wpe.c @@ -142,3 +142,4 @@ static struct platform_driver clk_mt8195_wpe_drv =3D { }, }; module_platform_driver(clk_mt8195_wpe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8365-apmixedsys.c index 6f0fdf92bbd2..55faa4e37116 100644 --- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -162,3 +162,4 @@ static struct platform_driver clk_mt8365_apmixed_drv = =3D { }, }; builtin_platform_driver(clk_mt8365_apmixed_drv) +MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9C00C64EC7 for ; Mon, 20 Feb 2023 15:04:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232231AbjBTPEM (ORCPT ); Mon, 20 Feb 2023 10:04:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232212AbjBTPDY (ORCPT ); Mon, 20 Feb 2023 10:03:24 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D477A1F912; Mon, 20 Feb 2023 07:02:14 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5E39066021C5; Mon, 20 Feb 2023 15:02:08 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905329; bh=vmZboqnY88zhAaEwDm8Q0/dnSl1U3JPvdAiFCCN2+8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UaUTf00yKdUCYO8hhmC1pnqicu+zw35t48TSwAwzGJ7dmKmNE4dem+IfNe1FxYtuG BSQL1uukt8AotRWvHuOQwJXEVm7Gc2d7aK+2JyGDwh9c8K/X1X+ecRvZejlHJuooCQ RXq+GnWlzUIyKgDqaWm7ziSKcv+AYrY28IgW7H46X+m+xhCbmN6OsH9RDclWlMv9Ht Wpkb5NPfbsw9c5k9+nL6NpnIrTMhzEh0jZQ25znAEvU/ZEqDaN2aM5CtoMqIKRLTvI xSTZcLunPCl2/CBWJK/nYgT2sOdzLS3dKuUxF2PlyEofB72avYeYTR5kE3WYYHovt9 DJC8tx6Mfz86g== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 38/55] clk: mediatek: mt2712: Change Kconfig options to allow module build Date: Mon, 20 Feb 2023 16:00:54 +0100 Message-Id: <20230220150111.77897-39-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the mt2712 drivers have been converted to platform drivers! Change the Kconfig options for all MT2712 clocks to tristate to allow building all clock drivers as modules. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index b9c0a9e21cf1..45b7aea7648d 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -75,7 +75,7 @@ config COMMON_CLK_MT2701_G3DSYS This driver supports MediaTek MT2701 g3dsys clocks. =20 config COMMON_CLK_MT2712 - bool "Clock driver for MediaTek MT2712" + tristate "Clock driver for MediaTek MT2712" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM64 @@ -83,43 +83,43 @@ config COMMON_CLK_MT2712 This driver supports MediaTek MT2712 basic clocks. =20 config COMMON_CLK_MT2712_BDPSYS - bool "Clock driver for MediaTek MT2712 bdpsys" + tristate "Clock driver for MediaTek MT2712 bdpsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 bdpsys clocks. =20 config COMMON_CLK_MT2712_IMGSYS - bool "Clock driver for MediaTek MT2712 imgsys" + tristate "Clock driver for MediaTek MT2712 imgsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 imgsys clocks. =20 config COMMON_CLK_MT2712_JPGDECSYS - bool "Clock driver for MediaTek MT2712 jpgdecsys" + tristate "Clock driver for MediaTek MT2712 jpgdecsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 jpgdecsys clocks. =20 config COMMON_CLK_MT2712_MFGCFG - bool "Clock driver for MediaTek MT2712 mfgcfg" + tristate "Clock driver for MediaTek MT2712 mfgcfg" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 mfgcfg clocks. =20 config COMMON_CLK_MT2712_MMSYS - bool "Clock driver for MediaTek MT2712 mmsys" + tristate "Clock driver for MediaTek MT2712 mmsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 mmsys clocks. =20 config COMMON_CLK_MT2712_VDECSYS - bool "Clock driver for MediaTek MT2712 vdecsys" + tristate "Clock driver for MediaTek MT2712 vdecsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 vdecsys clocks. =20 config COMMON_CLK_MT2712_VENCSYS - bool "Clock driver for MediaTek MT2712 vencsys" + tristate "Clock driver for MediaTek MT2712 vencsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 vencsys clocks. --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE51DC64EC7 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905330; bh=9U0oofs05zidsvFPSyTv8mUKQonv3/rdeQIkcPOGxgo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=At3pei5t4L+9Ak7nICglm8W2vqM8nxnAWl24FLzFKJ60uOXMAB/XJj7TBmuEpp3oB WGYVKEWF7W1FUWHfT3jA331VgoKWRe3E5NWWx8Da8R5ET49BkpH8YQ9TEghVxaAqZP SEw4cgGrSRd9Qzq0Ipgt19Jc47uq2EoRIDD0Q1UUKHLCjJ66rZWEGQsy45mu5CNRdD fVRBy4p0wVkhiv9582TZZz3z7WUwwMLmh9EzOYIAAf/lt9+G2BYDEvleVX+h6gEoqW G5K2jkvUmut2IhuVt/5n73Gs8gz/MSCLEfPLkOMIEr2v8o9YL4IJWoNnCd7nW8XV7/ k0jHHuj9Jyn8g== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 39/55] clk: mediatek: Split MT8195 clock drivers and allow module build Date: Mon, 20 Feb 2023 16:00:55 +0100 Message-Id: <20230220150111.77897-40-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MT8195 clock drivers were encapsulated in one single (and big) Kconfig option: there's no reason to do that, as it is totally unnecessary to build in all or none of them. Split them out: keep boot-critical clocks as bool and allow choosing non critical clocks as tristate. As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS are not for build-time but rather for runtime, as clocks registered by those have runtime dependencies on either or both VPP and IMGSYS. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 100 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/Makefile | 20 ++++--- 2 files changed, 113 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 45b7aea7648d..49919da2be26 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -692,6 +692,106 @@ config COMMON_CLK_MT8195 help This driver supports MediaTek MT8195 clocks. =20 +config COMMON_CLK_MT8195_APUSYS + tristate "Clock driver for MediaTek MT8195 apusys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 AI Processor Unit System clocks. + +config COMMON_CLK_MT8195_AUDSYS + tristate "Clock driver for MediaTek MT8195 audsys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 audsys clocks. + +config COMMON_CLK_MT8195_IMP_IIC_WRAP + tristate "Clock driver for MediaTek MT8195 imp_iic_wrap" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 I2C/I3C clocks. + +config COMMON_CLK_MT8195_IPESYS + tristate "Clock driver for MediaTek MT8195 ipesys" + depends on COMMON_CLK_MT8195_IMGSYS + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 ipesys clocks. + +config COMMON_CLK_MT8195_MFGCFG + tristate "Clock driver for MediaTek MT8195 mfgcfg" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 mfgcfg clocks. + +config COMMON_CLK_MT8195_MSDC + tristate "Clock driver for MediaTek MT8195 msdc" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 MMC and SD Controller's + msdc and msdc_top clocks. + +config COMMON_CLK_MT8195_SCP_ADSP + tristate "Clock driver for MediaTek MT8195 scp_adsp" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 System Companion Processor + Audio DSP clocks. + +config COMMON_CLK_MT8195_VDOSYS + tristate "Clock driver for MediaTek MT8195 vdosys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 vdosys0/1 (multimedia) clocks. + +config COMMON_CLK_MT8195_VPPSYS + tristate "Clock driver for MediaTek MT8195 vppsys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 vppsys0/1 clocks. + +config COMMON_CLK_MT8195_CAMSYS + tristate "Clock driver for MediaTek MT8195 camsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 camsys and camsys_raw clocks. + +config COMMON_CLK_MT8195_IMGSYS + tristate "Clock driver for MediaTek MT8195 imgsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 imgsys and imgsys2 clocks. + +config COMMON_CLK_MT8195_WPESYS + tristate "Clock driver for MediaTek MT8195 wpesys" + depends on COMMON_CLK_MT8195_IMGSYS + default COMMON_CLK_MT8195_IMGSYS + help + This driver supports MediaTek MT8195 Warp Engine clocks. + +config COMMON_CLK_MT8195_VDECSYS + tristate "Clock driver for MediaTek MT8195 vdecsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 vdecsys and vdecsys_soc clocks. + +config COMMON_CLK_MT8195_VENCSYS + tristate "Clock driver for MediaTek MT8195 vencsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 vencsys clocks. + config COMMON_CLK_MT8365 tristate "Clock driver for MediaTek MT8365" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 3133ad8c2028..63351957f862 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -106,13 +106,19 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) +=3D clk-mt8= 192-scp_adsp.o obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) +=3D clk-mt8192-vdec.o obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) +=3D clk-mt8192-venc.o obj-$(CONFIG_COMMON_CLK_MT8195) +=3D clk-mt8195-apmixedsys.o clk-mt8195-to= pckgen.o \ - clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \ - clk-mt8195-cam.o clk-mt8195-ccu.o clk-mt8195-img.o \ - clk-mt8195-ipe.o clk-mt8195-mfg.o clk-mt8195-scp_adsp.o \ - clk-mt8195-vdec.o clk-mt8195-vdo0.o clk-mt8195-vdo1.o \ - clk-mt8195-venc.o clk-mt8195-vpp0.o clk-mt8195-vpp1.o \ - clk-mt8195-wpe.o clk-mt8195-imp_iic_wrap.o \ - clk-mt8195-apusys_pll.o + clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o +obj-$(CONFIG_COMMON_CLK_MT8195_APUSYS) +=3D clk-mt8195-apusys_pll.o +obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) +=3D clk-mt8195-cam.o clk-mt8195-cc= u.o +obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) +=3D clk-mt8195-img.o +obj-$(CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP) +=3D clk-mt8195-imp_iic_wrap.o +obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) +=3D clk-mt8195-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) +=3D clk-mt8195-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) +=3D clk-mt8195-scp_adsp.o +obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) +=3D clk-mt8195-vdec.o +obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) +=3D clk-mt8195-vdo0.o clk-mt8195-v= do1.o +obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) +=3D clk-mt8195-venc.o +obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) +=3D clk-mt8195-vpp0.o clk-mt8195-v= pp1.o +obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) +=3D clk-mt8195-wpe.o obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365.o clk-mt8365-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) +=3D clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) +=3D clk-mt8365-cam.o --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 610B9C636CC for ; Mon, 20 Feb 2023 15:04:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232331AbjBTPEZ (ORCPT ); Mon, 20 Feb 2023 10:04:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231881AbjBTPD2 (ORCPT ); Mon, 20 Feb 2023 10:03:28 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93110206AA; Mon, 20 Feb 2023 07:02:22 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 233BC66021C4; Mon, 20 Feb 2023 15:02:11 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905332; bh=23yRTeVWUXmnOiJrCv3GdiTdq7Ghlfk/tGRYNluEPEY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SQbLEipwdnCYWFpB/zc0yqk/jGqQqC4N8qPlq0fND8mPOvKMlX37XdG0AMlV3/hnl DBBAbiAgRCxOVlfSzJrXvZMXHF0wJwzqYa/w+roJqUbfDQI8H9bMJiqvZY1kd16dZA rKEwTwFA0bVHmV2qoYi4FwgmajqCGW/0KjjyR0d/JJcZp+uVFZZiM5/tohl/9ofgph LEOu3o8kDogRa2EC1Zx87ZuScaXs2Y5oRAlXrWll8+GJ1Ro+yVCJJvIFEKY8j8Mt0+ N24b7lleoA7qC4soht0dttef8zjnCboe7heDWn1gvFUC4+90xn9rxcHYXhBUv5Rw30 CyIkYqZyDC0Lg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 40/55] clk: mediatek: Allow building MT8192 non-critical clocks as modules Date: Mon, 20 Feb 2023 16:00:56 +0100 Message-Id: <20230220150111.77897-41-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow building non boot critical clocks for MT8192 SoC as modules by changing them to tristate. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 49919da2be26..ac90b304d422 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -613,73 +613,73 @@ config COMMON_CLK_MT8192 This driver supports MediaTek MT8192 basic clocks. =20 config COMMON_CLK_MT8192_AUDSYS - bool "Clock driver for MediaTek MT8192 audsys" + tristate "Clock driver for MediaTek MT8192 audsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 audsys clocks. =20 config COMMON_CLK_MT8192_CAMSYS - bool "Clock driver for MediaTek MT8192 camsys" + tristate "Clock driver for MediaTek MT8192 camsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 camsys and camsys_raw clocks. =20 config COMMON_CLK_MT8192_IMGSYS - bool "Clock driver for MediaTek MT8192 imgsys" + tristate "Clock driver for MediaTek MT8192 imgsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 imgsys and imgsys2 clocks. =20 config COMMON_CLK_MT8192_IMP_IIC_WRAP - bool "Clock driver for MediaTek MT8192 imp_iic_wrap" + tristate "Clock driver for MediaTek MT8192 imp_iic_wrap" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 imp_iic_wrap clocks. =20 config COMMON_CLK_MT8192_IPESYS - bool "Clock driver for MediaTek MT8192 ipesys" + tristate "Clock driver for MediaTek MT8192 ipesys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 ipesys clocks. =20 config COMMON_CLK_MT8192_MDPSYS - bool "Clock driver for MediaTek MT8192 mdpsys" + tristate "Clock driver for MediaTek MT8192 mdpsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 mdpsys clocks. =20 config COMMON_CLK_MT8192_MFGCFG - bool "Clock driver for MediaTek MT8192 mfgcfg" + tristate "Clock driver for MediaTek MT8192 mfgcfg" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 mfgcfg clocks. =20 config COMMON_CLK_MT8192_MMSYS - bool "Clock driver for MediaTek MT8192 mmsys" + tristate "Clock driver for MediaTek MT8192 mmsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 mmsys clocks. =20 config COMMON_CLK_MT8192_MSDC - bool "Clock driver for MediaTek MT8192 msdc" + tristate "Clock driver for MediaTek MT8192 msdc" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 msdc and msdc_top clocks. =20 config COMMON_CLK_MT8192_SCP_ADSP - bool "Clock driver for MediaTek MT8192 scp_adsp" + tristate "Clock driver for MediaTek MT8192 scp_adsp" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 scp_adsp clocks. =20 config COMMON_CLK_MT8192_VDECSYS - bool "Clock driver for MediaTek MT8192 vdecsys" + tristate "Clock driver for MediaTek MT8192 vdecsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks. =20 config COMMON_CLK_MT8192_VENCSYS - bool "Clock driver for MediaTek MT8192 vencsys" + tristate "Clock driver for MediaTek MT8192 vencsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 vencsys clocks. --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80423C64EC4 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905333; bh=359HCE2F82NoU72fBczXZLXG7a2FJTqYmJkaO8gQsAE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L8IugqbYbyEzVumbULnOrzVCntO87sHB0RCOU5dGTpOSnnoC/h2pHuVClUyoEhb2n wzPB0u10yjTSxHGJYTZHfnGSMZLhnuNTM7my6ScEymKBsKSMPMs5/bUTt3WrQlzQCf PINRe2rmdD3r6Vpt/zpOeCrLIyhoMH5vsdBxExgDe2XgPtfE/VW0iUBa6O1Em21kL8 kv1f7j+doucjqjVuddsw7RyJISK+NpGEODt1yD4s7cFRvdP6qws48rH/pC9ubmvcw/ sUaB57spz2VULUstFpmV3Vyn+jLhKtjnLHAHuQnfuYrOJpRw6pWX0tyxDIGjO1i3o4 G+KGp1bfoaz7w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 41/55] clk: mediatek: Allow MT7622 clocks to be built as modules Date: Mon, 20 Feb 2023 16:00:57 +0100 Message-Id: <20230220150111.77897-42-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that all drivers are using the simple probe mechanism change the MT7622 clock drivers to tristate in Kconfig to allow module build. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index ac90b304d422..5f3894ce2418 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -336,7 +336,7 @@ config COMMON_CLK_MT6797_VENCSYS This driver supports MediaTek MT6797 vencsys clocks. =20 config COMMON_CLK_MT7622 - bool "Clock driver for MediaTek MT7622" + tristate "Clock driver for MediaTek MT7622" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -345,21 +345,21 @@ config COMMON_CLK_MT7622 required for various periperals found on MediaTek. =20 config COMMON_CLK_MT7622_ETHSYS - bool "Clock driver for MediaTek MT7622 ETHSYS" + tristate "Clock driver for MediaTek MT7622 ETHSYS" depends on COMMON_CLK_MT7622 help This driver add support for clocks for Ethernet and SGMII required on MediaTek MT7622 SoC. =20 config COMMON_CLK_MT7622_HIFSYS - bool "Clock driver for MediaTek MT7622 HIFSYS" + tristate "Clock driver for MediaTek MT7622 HIFSYS" depends on COMMON_CLK_MT7622 help This driver supports MediaTek MT7622 HIFSYS clocks providing to PCI-E and USB. =20 config COMMON_CLK_MT7622_AUDSYS - bool "Clock driver for MediaTek MT7622 AUDSYS" + tristate "Clock driver for MediaTek MT7622 AUDSYS" depends on COMMON_CLK_MT7622 help This driver supports MediaTek MT7622 AUDSYS clocks providing --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2EA3C05027 for ; Mon, 20 Feb 2023 15:04:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232920AbjBTPEU (ORCPT ); Mon, 20 Feb 2023 10:04:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232830AbjBTPD1 (ORCPT ); Mon, 20 Feb 2023 10:03:27 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B205D206B7; Mon, 20 Feb 2023 07:02:22 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id ECED36602176; Mon, 20 Feb 2023 15:02:13 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905335; bh=MjQrecKRreRZSY+0h+AnsA7DFOSdZygxphASeOcJGt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hYxi9f35ISdPhkxOEi8qxEd2nYMjFVnf6LqlRytSNDuGw5+JqRGDhqVRtX2hsbd7i W4eAMMlcbuwJQroHlMfJ8LISJngYoHB4yOdYPEKCrVWZO+v7E2KzsIqe5tCtBx+zoQ X1KCsYHpLPTeZh7aXXvIou+MJhHAk2rebauv81kPTW4W4YTsnbyv/bi6gVu3iq3PG4 HA8NANos0sNP4PHmWL8RsIUBTN1TJVOLUmm4CZEtld6o8RnaVSfNCK7DD0v8VdJ2A3 w3Imxcq9KsVWE+kPVIKRVjgwSTLJ+O1OIH6IsZ6p4d/SWYeRctyeJozum97E9f656m TiPPFyDjKCfVg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 42/55] clk: mediatek: Allow all MT8167 clocks to be built as modules Date: Mon, 20 Feb 2023 16:00:58 +0100 Message-Id: <20230220150111.77897-43-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Almost all MT8167 clocks have been converted to use the common probe mechanism, moreover, now all of them are platform drivers: allow building as modules. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 5f3894ce2418..6cbc69e713dd 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -406,7 +406,7 @@ config COMMON_CLK_MT7981_ETHSYS required on MediaTek MT7981 SoC. =20 config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" + tristate "Clock driver for MediaTek MT7986" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -415,7 +415,7 @@ config COMMON_CLK_MT7986 required for various peripherals found on MediaTek. =20 config COMMON_CLK_MT7986_ETHSYS - bool "Clock driver for MediaTek MT7986 ETHSYS" + tristate "Clock driver for MediaTek MT7986 ETHSYS" depends on COMMON_CLK_MT7986 default COMMON_CLK_MT7986 help @@ -431,7 +431,7 @@ config COMMON_CLK_MT8135 This driver supports MediaTek MT8135 clocks. =20 config COMMON_CLK_MT8167 - bool "Clock driver for MediaTek MT8167" + tristate "Clock driver for MediaTek MT8167" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -439,35 +439,35 @@ config COMMON_CLK_MT8167 This driver supports MediaTek MT8167 basic clocks. =20 config COMMON_CLK_MT8167_AUDSYS - bool "Clock driver for MediaTek MT8167 audsys" + tristate "Clock driver for MediaTek MT8167 audsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 audsys clocks. =20 config COMMON_CLK_MT8167_IMGSYS - bool "Clock driver for MediaTek MT8167 imgsys" + tristate "Clock driver for MediaTek MT8167 imgsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 imgsys clocks. =20 config COMMON_CLK_MT8167_MFGCFG - bool "Clock driver for MediaTek MT8167 mfgcfg" + tristate "Clock driver for MediaTek MT8167 mfgcfg" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 mfgcfg clocks. =20 config COMMON_CLK_MT8167_MMSYS - bool "Clock driver for MediaTek MT8167 mmsys" + tristate "Clock driver for MediaTek MT8167 mmsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 mmsys clocks. =20 config COMMON_CLK_MT8167_VDECSYS - bool "Clock driver for MediaTek MT8167 vdecsys" + tristate "Clock driver for MediaTek MT8167 vdecsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help --=20 2.39.1 From nobody Thu Nov 14 07:15:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1B52C636D6 for ; Mon, 20 Feb 2023 15:05:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233005AbjBTPFo (ORCPT ); Mon, 20 Feb 2023 10:05:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232797AbjBTPFZ (ORCPT ); Mon, 20 Feb 2023 10:05:25 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0502820569; Mon, 20 Feb 2023 07:03:32 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5B45266021C7; Mon, 20 Feb 2023 15:02:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905336; bh=zK57pu6YreEhk+8+0/wsk/oSJuvEwA1BCrX0LjW9yCw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DbNTnmaGgiRU1R5tSO6gZHxGlWb8PPOQTQrSOoketnQD6Ukz74zBkGOqBEPx70LtM sxsPx854BprmifxmozCFhsaWFUj8nswrPXGESmaQbAJAhxffWfyIMMVjk+ubnlXWqw 0Mc3v6TCt7zrPV1Df3mal+8G+UiuMibMx4DgWLsyoYPZxxqsiKT9XwOhzVlx+137mi HFjGrIXlPgqZnv9vH6o3Q79Hzdt8hY8UyZOitbJRF/9okFjRTzG+5L0CO1HBJeTw7Y qgwQFteXzeLjeI+FyP22GjIm5KNEsVjOrh4K2DTFGw6M9av0EW9JNUSlOMWlWpgQFk H6X1rX/9oG4ZQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 43/55] clk: mediatek: Allow all MT8183 clocks to be built as modules Date: Mon, 20 Feb 2023 16:00:59 +0100 Message-Id: <20230220150111.77897-44-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All MT8183 clocks are platform drivers now! Allow module build for all of them. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 6cbc69e713dd..ff04d82278eb 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -511,7 +511,7 @@ config COMMON_CLK_MT8173_VENCSYS This driver supports MediaTek MT8173 vencsys clocks. =20 config COMMON_CLK_MT8183 - bool "Clock driver for MediaTek MT8183" + tristate "Clock driver for MediaTek MT8183" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM64 @@ -519,77 +519,77 @@ config COMMON_CLK_MT8183 This driver supports MediaTek MT8183 basic clocks. =20 config COMMON_CLK_MT8183_AUDIOSYS - bool "Clock driver for MediaTek MT8183 audiosys" + tristate "Clock driver for MediaTek MT8183 audiosys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 audiosys clocks. =20 config COMMON_CLK_MT8183_CAMSYS - bool "Clock driver for MediaTek MT8183 camsys" + tristate "Clock driver for MediaTek MT8183 camsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 camsys clocks. =20 config COMMON_CLK_MT8183_IMGSYS - bool "Clock driver for MediaTek MT8183 imgsys" + tristate "Clock driver for MediaTek MT8183 imgsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 imgsys clocks. =20 config COMMON_CLK_MT8183_IPU_CORE0 - bool "Clock driver for MediaTek MT8183 ipu_core0" + tristate "Clock driver for MediaTek MT8183 ipu_core0" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_core0 clocks. =20 config COMMON_CLK_MT8183_IPU_CORE1 - bool "Clock driver for MediaTek MT8183 ipu_core1" + tristate "Clock driver for MediaTek MT8183 ipu_core1" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_core1 clocks. =20 config COMMON_CLK_MT8183_IPU_ADL - bool "Clock driver for MediaTek MT8183 ipu_adl" + tristate "Clock driver for MediaTek MT8183 ipu_adl" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_adl clocks. =20 config COMMON_CLK_MT8183_IPU_CONN - bool "Clock driver for MediaTek MT8183 ipu_conn" + tristate "Clock driver for MediaTek MT8183 ipu_conn" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_conn clocks. =20 config COMMON_CLK_MT8183_MFGCFG - bool "Clock driver for MediaTek MT8183 mfgcfg" + tristate "Clock driver for MediaTek MT8183 mfgcfg" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 mfgcfg clocks. =20 config COMMON_CLK_MT8183_MMSYS - bool "Clock driver for MediaTek MT8183 mmsys" + tristate "Clock driver for MediaTek MT8183 mmsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 mmsys clocks. =20 config COMMON_CLK_MT8183_VDECSYS - bool "Clock driver for MediaTek MT8183 vdecsys" + tristate "Clock driver for MediaTek MT8183 vdecsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 vdecsys clocks. =20 config COMMON_CLK_MT8183_VENCSYS - bool "Clock driver for MediaTek MT8183 vencsys" + tristate "Clock driver for MediaTek MT8183 vencsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46654C636CC for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905338; bh=k7bncCcPZA4qJIjsoCxr5pF3cB6dN/coulSPVCKj5oE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FLnPTZYmYlZvv3YSyemi0IWXB/YVGIybetNfat8LUIdS7+eIarg6jiUO7jGAfpSDn OHiqyT+2gXNyEJxeJNNiV8nOS7rkJ9H3Vn3saL3D04iAYKhM7z5G595LyR1wISabNb HVisk6ftzHzsfqVzXFoVatQyRVh/fGedk30FXIC+uN5cNMXuULkQOseeNwqPub2ENq vwLCLieEuac1JNwUiSitaVxy5MlBCQExubaJ8rwnSQ0QJOq+ngsK6EubRnWoYzHV0w dIM6N+dnyFDCPRsIa7z+3//FeeEvAE5O5mqCMIbPGKfcEQ6i+sEquEBP1G3+pv2gm2 i+AgNPdZFDneA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 44/55] clk: mediatek: Allow building most MT6765 clock drivers as modules Date: Mon, 20 Feb 2023 16:01:00 +0100 Message-Id: <20230220150111.77897-45-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Most of the MT6765 clock drivers can be built as modules: change them to tristate to allow that. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index ff04d82278eb..bf27dad1b490 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -133,79 +133,79 @@ config COMMON_CLK_MT6765 This driver supports MediaTek MT6765 basic clocks. =20 config COMMON_CLK_MT6765_AUDIOSYS - bool "Clock driver for MediaTek MT6765 audiosys" + tristate "Clock driver for MediaTek MT6765 audiosys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 audiosys clocks. =20 config COMMON_CLK_MT6765_CAMSYS - bool "Clock driver for MediaTek MT6765 camsys" + tristate "Clock driver for MediaTek MT6765 camsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 camsys clocks. =20 config COMMON_CLK_MT6765_GCESYS - bool "Clock driver for MediaTek MT6765 gcesys" + tristate "Clock driver for MediaTek MT6765 gcesys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 gcesys clocks. =20 config COMMON_CLK_MT6765_MMSYS - bool "Clock driver for MediaTek MT6765 mmsys" + tristate "Clock driver for MediaTek MT6765 mmsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mmsys clocks. =20 config COMMON_CLK_MT6765_IMGSYS - bool "Clock driver for MediaTek MT6765 imgsys" + tristate "Clock driver for MediaTek MT6765 imgsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 imgsys clocks. =20 config COMMON_CLK_MT6765_VCODECSYS - bool "Clock driver for MediaTek MT6765 vcodecsys" + tristate "Clock driver for MediaTek MT6765 vcodecsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 vcodecsys clocks. =20 config COMMON_CLK_MT6765_MFGSYS - bool "Clock driver for MediaTek MT6765 mfgsys" + tristate "Clock driver for MediaTek MT6765 mfgsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mfgsys clocks. =20 config COMMON_CLK_MT6765_MIPI0ASYS - bool "Clock driver for MediaTek MT6765 mipi0asys" + tristate "Clock driver for MediaTek MT6765 mipi0asys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi0asys clocks. =20 config COMMON_CLK_MT6765_MIPI0BSYS - bool "Clock driver for MediaTek MT6765 mipi0bsys" + tristate "Clock driver for MediaTek MT6765 mipi0bsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi0bsys clocks. =20 config COMMON_CLK_MT6765_MIPI1ASYS - bool "Clock driver for MediaTek MT6765 mipi1asys" + tristate "Clock driver for MediaTek MT6765 mipi1asys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi1asys clocks. =20 config COMMON_CLK_MT6765_MIPI1BSYS - bool "Clock driver for MediaTek MT6765 mipi1bsys" + tristate "Clock driver for MediaTek MT6765 mipi1bsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi1bsys clocks. =20 config COMMON_CLK_MT6765_MIPI2ASYS - bool "Clock driver for MediaTek MT6765 mipi2asys" + tristate "Clock driver for MediaTek MT6765 mipi2asys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi2asys clocks. =20 config COMMON_CLK_MT6765_MIPI2BSYS - bool "Clock driver for MediaTek MT6765 mipi2bsys" + tristate "Clock driver for MediaTek MT6765 mipi2bsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi2bsys clocks. --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B31C6C64ED9 for ; Mon, 20 Feb 2023 15:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231511AbjBTPFi (ORCPT ); Mon, 20 Feb 2023 10:05:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232963AbjBTPFL (ORCPT ); Mon, 20 Feb 2023 10:05:11 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EB2A20066; Mon, 20 Feb 2023 07:03:25 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2E44A6602173; Mon, 20 Feb 2023 15:02:18 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905339; bh=uU/7bQ25kUBitf+IxOTEtWvQReBBcOYpCxGIBYu7/dc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GBiSxGsT4w2/Cm27RnUimOwEWAiuCUvrpjO8Nhpm2vKhaIS5gu+O1Z5wwS35kGlrd RGxXPMXP9Fkp3ejw33tHOXP5mGQrIzHmYD6Z9B6YCXSFjbfEpuO8aL/ejVu3TaUIyW MjTX1Yp10pCpu1FW5HMARY7SCEjYhbWGirJxSnmzNaTBalFw1Zf9CI/Xef8MyxC+do ON3eIb7ru5Qu8Wm30C1KgkMAVa/0adsh5qH4fpgqNwBE9exyUSVNSAIeplyXqMnnJX asC0CokdsKry0To8Dz100TqCEKijI5zhKTZQStFeiYWba2YsoYl/wxr5n3+jp7Q0OD wfeiDNcfzR3ig== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 45/55] clk: mediatek: Allow building most MT6797 clock drivers as modules Date: Mon, 20 Feb 2023 16:01:01 +0100 Message-Id: <20230220150111.77897-46-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Most of the MT6797 clock drivers can be built as modules: change them to tristate to allow that. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index bf27dad1b490..a558e951d759 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -312,25 +312,25 @@ config COMMON_CLK_MT6797 This driver supports MediaTek MT6797 basic clocks. =20 config COMMON_CLK_MT6797_MMSYS - bool "Clock driver for MediaTek MT6797 mmsys" + tristate "Clock driver for MediaTek MT6797 mmsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 mmsys clocks. =20 config COMMON_CLK_MT6797_IMGSYS - bool "Clock driver for MediaTek MT6797 imgsys" + tristate "Clock driver for MediaTek MT6797 imgsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 imgsys clocks. =20 config COMMON_CLK_MT6797_VDECSYS - bool "Clock driver for MediaTek MT6797 vdecsys" + tristate "Clock driver for MediaTek MT6797 vdecsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 vdecsys clocks. =20 config COMMON_CLK_MT6797_VENCSYS - bool "Clock driver for MediaTek MT6797 vencsys" + tristate "Clock driver for MediaTek MT6797 vencsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 vencsys clocks. --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED41C636D6 for ; Mon, 20 Feb 2023 15:04:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232960AbjBTPEx (ORCPT ); Mon, 20 Feb 2023 10:04:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229810AbjBTPEK (ORCPT ); Mon, 20 Feb 2023 10:04:10 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AD3020D0D; Mon, 20 Feb 2023 07:02:38 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 90475660217D; Mon, 20 Feb 2023 15:02:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905340; bh=qNjIvg0DPQshUABYHxEL6t8PvZGn3/N8UqW924VnahA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TBm7IERtMtk8KDGMqwk43nbr5LpwubgauGz48XSFxZdS56MK7GPwodi7N+Q+CFaV0 77zVwnkHfRWHCNKSiurfw7JJ+SiqZwHq4kA/VP1oBCkfQS0s5sccfW5kmrcVCaBkLR qLHCAjWGhCG4dZJ+3SOGcG9QZG+sX/S8fqEKHeO8d2RcOUCsWSHJyXHPNWKxxuEpw/ SzHlswKEGC0WJLbZrblUuR7RzRMAiLVILEliVn4/VdPFWLU1UEIRSmun6NwpoiIOLl lRilqpFYuzX8gUzUe3JnD2BFicozemMPuIsFg49Ylhil+5iKJ/ejmLQ8Ao0dS8urAy bfQdExhaxzhbw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 46/55] clk: mediatek: Split configuration options for MT8186 clock drivers Date: Mon, 20 Feb 2023 16:01:02 +0100 Message-Id: <20230220150111.77897-47-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When building clock drivers for MT8186, some may want to build in only some of them to, for example, get CPUFreq up faster, and some may want to leave out some clock drivers entirely as a machine may not need the Warp Engine or the camera ISP (hence, their clock drivers). Split the various clock drivers in their own configuration options, keeping MT8186 configuration options consistent with other MediaTek SoCs. While at it, also allow building the remaining clock drivers as modules by switching COMMON_CLK_MT8186 to tristate. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 79 ++++++++++++++++++++++++++++++++++- drivers/clk/mediatek/Makefile | 18 +++++--- 2 files changed, 91 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index a558e951d759..6f970d54a2cd 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -596,7 +596,7 @@ config COMMON_CLK_MT8183_VENCSYS This driver supports MediaTek MT8183 vencsys clocks. =20 config COMMON_CLK_MT8186 - bool "Clock driver for MediaTek MT8186" + tristate "Clock driver for MediaTek MT8186" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK select COMMON_CLK_MEDIATEK_FHCTL @@ -604,6 +604,83 @@ config COMMON_CLK_MT8186 help This driver supports MediaTek MT8186 clocks. =20 +config COMMON_CLK_MT8186_CAMSYS + tristate "Clock driver for MediaTek MT8186 camsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 camsys and camsys_raw clocks. + +config COMMON_CLK_MT8186_IMGSYS + tristate "Clock driver for MediaTek MT8186 imgsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 imgsys and imgsys2 clocks. + +config COMMON_CLK_MT8186_IPESYS + tristate "Clock driver for MediaTek MT8186 ipesys" + depends on COMMON_CLK_MT8186_IMGSYS + default COMMON_CLK_MT8186_IMGSYS + help + This driver supports MediaTek MT8186 ipesys clocks. + +config COMMON_CLK_MT8186_WPESYS + tristate "Clock driver for MediaTek MT8186 wpesys" + depends on COMMON_CLK_MT8186_IMGSYS + default COMMON_CLK_MT8186_IMGSYS + help + This driver supports MediaTek MT8186 Warp Engine clocks. + +config COMMON_CLK_MT8186_IMP_IIC_WRAP + tristate "Clock driver for MediaTek MT8186 imp_iic_wrap" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 imp_iic_wrap clocks. + +config COMMON_CLK_MT8186_MCUSYS + tristate "Clock driver for MediaTek MT8186 mcusys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mcusys clocks. + +config COMMON_CLK_MT8186_MDPSYS + tristate "Clock driver for MediaTek MT8186 mdpsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mdpsys clocks. + +config COMMON_CLK_MT8186_MFGCFG + tristate "Clock driver for MediaTek MT8186 mfgcfg" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mfgcfg clocks. + +config COMMON_CLK_MT8186_MMSYS + tristate "Clock driver for MediaTek MT8186 mmsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mmsys clocks. + +config COMMON_CLK_MT8186_VDECSYS + tristate "Clock driver for MediaTek MT8186 vdecsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 vdecsys and vdecsys_soc clocks. + +config COMMON_CLK_MT8186_VENCSYS + tristate "Clock driver for MediaTek MT8186 vencsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 vencsys clocks. + config COMMON_CLK_MT8192 bool "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 63351957f862..6204ad17b7ca 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -87,11 +87,19 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) +=3D clk-mt8183-= mfgcfg.o obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) +=3D clk-mt8183-mm.o obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) +=3D clk-mt8183-vdec.o obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) +=3D clk-mt8183-venc.o -obj-$(CONFIG_COMMON_CLK_MT8186) +=3D clk-mt8186-mcu.o clk-mt8186-topckgen.= o clk-mt8186-infra_ao.o \ - clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \ - clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \ - clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \ - clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8186) +=3D clk-mt8186-apmixedsys.o clk-mt8186-in= fra_ao.o \ + clk-mt8186-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT8186_CAMSYS) +=3D clk-mt8186-cam.o +obj-$(CONFIG_COMMON_CLK_MT8186_IMGSYS) +=3D clk-mt8186-img.o +obj-$(CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP) +=3D clk-mt8186-imp_iic_wrap.o +obj-$(CONFIG_COMMON_CLK_MT8186_IPESYS) +=3D clk-mt8186-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8186_MCUSYS) +=3D clk-mt8186-mcu.o +obj-$(CONFIG_COMMON_CLK_MT8186_MDPSYS) +=3D clk-mt8186-mdp.o +obj-$(CONFIG_COMMON_CLK_MT8186_MFGCFG) +=3D clk-mt8186-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8186_MMSYS) +=3D clk-mt8186-mm.o +obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) +=3D clk-mt8186-vdec.o +obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) +=3D clk-mt8186-venc.o +obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) +=3D clk-mt8186-wpe.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F4DAC05027 for ; Mon, 20 Feb 2023 15:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233001AbjBTPFm (ORCPT ); Mon, 20 Feb 2023 10:05:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230203AbjBTPFY (ORCPT ); Mon, 20 Feb 2023 10:05:24 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D721920550; Mon, 20 Feb 2023 07:03:28 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id F38B466021C9; Mon, 20 Feb 2023 15:02:20 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905342; bh=icsavTwrDqIH6RiZC0arodFRjMxY0YRQtj8Fgou62kY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q/ynuJ7tvOG4ZlgjHIoaZi7acOOTqu4N/WXiiU8lHdimDYgvAfUW5xiOvxNcVAjG2 5OmGUN5M23tyXs3o8mrG/48cGq1gNIUl4heCq9YYyk7y/8KKwZl+NSdWgoBDVnBH5H WplixQUZ8soJNDlExD8b0WyLWrppL71zgN4M0+CgwHjdJeYP9fivis70l02d9/Z4em QWT1DFSPZ7AS/HEY0kPFp/sCXla0EG7YuRUlqU2L5Xvf7EgJBnsVDwncHHdaenQd7m //PuyCXLtC/vATLMOorg8gxDsHM+6BliUn5oVzhZzW/s6MLEcerT+wdtmcFyJ5CEfF q4YfEPQuxzbMw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 47/55] clk: mediatek: mt8192: Move apmixedsys clock driver to its own file Date: Mon, 20 Feb 2023 16:01:03 +0100 Message-Id: <20230220150111.77897-48-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is the last man standing in clk-mt8192.c that won't allow us to use the module_platform_driver() macro, and for *no* good reason. Move it to clk-mt8192-apmixedsys.c and while at it, also add a .remove() callback for it. Also, since the need for "clk-mt8192-simple" and "clk-mt8192" was just due to them being in the same file and probing different clocks, and since now there's just one platform_driver struct per file, it seemed natural to rename the `-simple` variant to just "clk-mt8192". Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 214 ++++++++++++++++++ drivers/clk/mediatek/clk-mt8192.c | 221 +------------------ 3 files changed, 219 insertions(+), 218 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8192-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 6204ad17b7ca..5facbe93141e 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -100,7 +100,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186_MMSYS) +=3D clk-mt8186-m= m.o obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) +=3D clk-mt8186-vdec.o obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) +=3D clk-mt8186-venc.o obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) +=3D clk-mt8186-wpe.o -obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192.o +obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192.o clk-mt8192-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) +=3D clk-mt8192-img.o diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8192-apmixedsys.c new file mode 100644 index 000000000000..1e6988d5289a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + * Chun-Jie Chen + * Copyright (c) 2023 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include "clk-fhctl.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" +#include "clk-pllfh.h" + +static const struct mtk_gate_regs apmixed_cg_regs =3D { + .set_ofs =3D 0x14, + .clr_ofs =3D 0x14, + .sta_ofs =3D 0x14, +}; + +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr_inv) + +static const struct mtk_gate apmixed_clks[] =3D { + GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), +}; + +#define MT8192_PLL_FMAX (3800UL * MHZ) +#define MT8192_PLL_FMIN (1500UL * MHZ) +#define MT8192_INTEGER_BITS 8 + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, _pcw_chg_reg, \ + _en_reg, _pll_en_bit) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D _rst_bar_mask, \ + .fmax =3D MT8192_PLL_FMAX, \ + .fmin =3D MT8192_PLL_FMIN, \ + .pcwbits =3D _pcwbits, \ + .pcwibits =3D MT8192_INTEGER_BITS, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .tuner_en_reg =3D _tuner_en_reg, \ + .tuner_en_bit =3D _tuner_en_bit, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .pcw_chg_reg =3D _pcw_chg_reg, \ + .en_reg =3D _en_reg, \ + .pll_en_bit =3D _pll_en_bit, \ + } + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift) \ + PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, 0, 0, 0) + +static const struct mtk_pll_data plls[] =3D { + PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), + PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), + PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, + 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), + PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, + 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), + PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, + 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), + PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, + 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), + PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, + 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), + PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, + 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), +}; + +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL0, + FH_ARMPLL_BL1, + FH_ARMPLL_BL2, + FH_ARMPLL_BL3, + FH_CCIPLL, + FH_MFGPLL, + FH_MEMPLL, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_ADSPPLL, + FH_APUPLL, + FH_TVDPLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), +}; + +static const struct of_device_id of_match_clk_mt8192_apmixed[] =3D { + { .compatible =3D "mediatek,mt8192-apmixedsys" }, + { /* sentinel */ } +}; + +static int clk_mt8192_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + const u8 *fhctl_node =3D "mediatek,mt8192-fhctl"; + int r; + + clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); + if (r) + goto free_clk_data; + + r =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (r) + goto unregister_plls; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_gates; + + return r; + +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); +unregister_plls: + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt8192_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt8192_apmixed_drv =3D { + .driver =3D { + .name =3D "clk-mt8192-apmixed", + .of_match_table =3D of_match_clk_mt8192_apmixed, + }, + .probe =3D clk_mt8192_apmixed_probe, + .remove =3D clk_mt8192_apmixed_remove, +}; +module_platform_driver(clk_mt8192_apmixed_drv); +MODULE_DESCRIPTION("MediaTek MT8192 apmixed clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 35afe496b1c1..45eccda51471 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -12,12 +12,9 @@ #include #include =20 -#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-pll.h" -#include "clk-pllfh.h" =20 #include #include @@ -714,19 +711,6 @@ static struct mtk_composite top_muxes[] =3D { DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10= , 0x338, 8, 16), }; =20 -static const struct mtk_gate_regs apmixed_cg_regs =3D { - .set_ofs =3D 0x14, - .clr_ofs =3D 0x14, - .sta_ofs =3D 0x14, -}; - -#define GATE_APMIXED(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops= _no_setclr_inv) - -static const struct mtk_gate apmixed_clks[] =3D { - GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), -}; - static const struct mtk_gate_regs infra0_cg_regs =3D { .set_ofs =3D 0x80, .clr_ofs =3D 0x84, @@ -980,121 +964,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D= { .rst_idx_map_nr =3D ARRAY_SIZE(infra_ao_idx_map), }; =20 -#define MT8192_PLL_FMAX (3800UL * MHZ) -#define MT8192_PLL_FMIN (1500UL * MHZ) -#define MT8192_INTEGER_BITS 8 - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, _pcw_chg_reg, \ - _en_reg, _pll_en_bit) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D _rst_bar_mask, \ - .fmax =3D MT8192_PLL_FMAX, \ - .fmin =3D MT8192_PLL_FMIN, \ - .pcwbits =3D _pcwbits, \ - .pcwibits =3D MT8192_INTEGER_BITS, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .tuner_en_reg =3D _tuner_en_reg, \ - .tuner_en_bit =3D _tuner_en_bit, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .pcw_chg_reg =3D _pcw_chg_reg, \ - .en_reg =3D _en_reg, \ - .pll_en_bit =3D _pll_en_bit, \ - } - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift) \ - PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, 0, 0, 0) - -static const struct mtk_pll_data plls[] =3D { - PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), - PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), - PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, - 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), - PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, - 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), - PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), - PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, - 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), - PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, - 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), - PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, - 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), - PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, - 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), -}; - -enum fh_pll_id { - FH_ARMPLL_LL, - FH_ARMPLL_BL0, - FH_ARMPLL_BL1, - FH_ARMPLL_BL2, - FH_ARMPLL_BL3, - FH_CCIPLL, - FH_MFGPLL, - FH_MEMPLL, - FH_MPLL, - FH_MMPLL, - FH_MAINPLL, - FH_MSDCPLL, - FH_ADSPPLL, - FH_APUPLL, - FH_TVDPLL, - FH_NR_FH, -}; - -#define FH(_pllid, _fhid, _offset) { \ - .data =3D { \ - .pll_id =3D _pllid, \ - .fh_id =3D _fhid, \ - .fh_ver =3D FHCTL_PLLFH_V2, \ - .fhx_offset =3D _offset, \ - .dds_mask =3D GENMASK(21, 0), \ - .slope0_value =3D 0x6003c97, \ - .slope1_value =3D 0x6003c97, \ - .sfstrx_en =3D BIT(2), \ - .frddsx_en =3D BIT(1), \ - .fhctlx_en =3D BIT(0), \ - .tgl_org =3D BIT(31), \ - .dvfs_tri =3D BIT(31), \ - .pcwchg =3D BIT(31), \ - .dt_val =3D 0x0, \ - .df_val =3D 0x9, \ - .updnlmt_shft =3D 16, \ - .msk_frddsx_dys =3D GENMASK(23, 20), \ - .msk_frddsx_dts =3D GENMASK(19, 16), \ - }, \ - } - -static struct mtk_pllfh_data pllfhs[] =3D { - FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), - FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), - FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), - FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), - FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c), - FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), -}; - /* Register mux notifier for MFG mux */ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) { @@ -1117,70 +986,6 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct dev= ice *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } =20 -static int clk_mt8192_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - const u8 *fhctl_node =3D "mediatek,mt8192-fhctl"; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); - - r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), - pllfhs, ARRAY_SIZE(pllfhs), clk_data); - if (r) - goto free_clk_data; - - r =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - if (r) - goto unregister_plls; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); -unregister_plls: - mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, - ARRAY_SIZE(pllfhs), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt8192[] =3D { - { - .compatible =3D "mediatek,mt8192-apmixedsys", - .data =3D clk_mt8192_apmixed_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt8192_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe =3D of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r =3D clk_probe(pdev); - if (r) - dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev-= >name, r); - - return r; -} - static const struct mtk_clk_desc infra_desc =3D { .clks =3D infra_clks, .num_clks =3D ARRAY_SIZE(infra_clks), @@ -1208,38 +1013,20 @@ static const struct mtk_clk_desc topck_desc =3D { .mfg_clk_idx =3D CLK_TOP_MFG_PLL_SEL, }; =20 -static const struct of_device_id of_match_clk_mt8192_simple[] =3D { +static const struct of_device_id of_match_clk_mt8192[] =3D { { .compatible =3D "mediatek,mt8192-infracfg", .data =3D &infra_desc }, { .compatible =3D "mediatek,mt8192-pericfg", .data =3D &peri_desc }, { .compatible =3D "mediatek,mt8192-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 -static struct platform_driver clk_mt8192_simple_drv =3D { - .probe =3D mtk_clk_simple_probe, - .remove =3D mtk_clk_simple_remove, - .driver =3D { - .name =3D "clk-mt8192-simple", - .of_match_table =3D of_match_clk_mt8192_simple, - }, -}; - static struct platform_driver clk_mt8192_drv =3D { - .probe =3D clk_mt8192_probe, .driver =3D { .name =3D "clk-mt8192", .of_match_table =3D of_match_clk_mt8192, }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; - -static int __init clk_mt8192_init(void) -{ - int ret =3D platform_driver_register(&clk_mt8192_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt8192_simple_drv); -} - -arch_initcall(clk_mt8192_init); +module_platform_driver(clk_mt8192_drv); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13524C64EC4 for ; Mon, 20 Feb 2023 15:09:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232902AbjBTPJo (ORCPT ); Mon, 20 Feb 2023 10:09:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232387AbjBTPJV (ORCPT ); Mon, 20 Feb 2023 10:09:21 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 952E020578; Mon, 20 Feb 2023 07:08:45 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5FD3366021CB; Mon, 20 Feb 2023 15:02:22 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905343; bh=n2hgQCHC+yZ31qlw6R7gz49FBg/5g7apceJcI0oFfeU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lscCxmE2S9xd4sCl+fB5xOhzRFNXZkJTRy5qaT6pa6r9Ho1BgHsDiDH5096XNQw+k V3KNXiZcdpaRSN79Zpkq+pNls2Am9jM9tXJxA8Z9551n85SdpK4sm79oNAKkkIDBQm GmhCfInEX8g7v9mCAZGksV0VVmADMOFMbdctkcbhGIgrKJlYTIdPrv3NMWYCigP3AO BpnFsvJJkJB+55qtDefpkxXbWCaoCdVsi8cIpd+2UnrusKaC66KDvl6+RZQRgoYFYJ B8f9EDS1+6yQWr+juCvzVzadEI5c710ijQr3NYQrFyTeVDYgXxSPjRTEDsDRqUUfG3 itpOqhSFu0OWw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 48/55] clk: mediatek: Kconfig: Allow module build for core mt8192 clocks Date: Mon, 20 Feb 2023 16:01:04 +0100 Message-Id: <20230220150111.77897-49-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Bootloaders must in a way setup the SoC to boot Linux: this means that it will be possible to decompress a ramdisk and eventually insert the core clock driver module from there. Allow module build for all MT8192 clocks by switching to tristate. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 6f970d54a2cd..90691261cddb 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -682,7 +682,7 @@ config COMMON_CLK_MT8186_VENCSYS This driver supports MediaTek MT8186 vencsys clocks. =20 config COMMON_CLK_MT8192 - bool "Clock driver for MediaTek MT8192" + tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARM64 --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAB62C64EC7 for ; Mon, 20 Feb 2023 15:06:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233019AbjBTPGI (ORCPT ); Mon, 20 Feb 2023 10:06:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232964AbjBTPFv (ORCPT ); Mon, 20 Feb 2023 10:05:51 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8195B21280; Mon, 20 Feb 2023 07:04:05 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C5F3E6602166; Mon, 20 Feb 2023 15:02:23 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905345; bh=rEw9oTl9L47teEVrs+UZRmLruZIeQA8fRtCQFxBZD9U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R+ZN3aXI2Ej+zAk5HzzZ0/hv4+nB8a/QZljZHL1J9vLeT6J+d7FV17slPhsauLsUi ue0fzT6+xnB6sy/WSctGef8HPCj62Bf2kytylDtGiH5Jd8DyCPct55GyCiFb/TRpIP 9rdvXDp9xg2DpOwewbG8fOcqkT2fsWba5faWfmN4XCx0NAtOuImkJoUnXC4kVtQkdA w71J7SNPyK9iMfrfuNmHp4+dbtjV+Yuk4Q6Ds5VD4HzAS8pt7uFT9/lI99cgAzEvu2 zkABRsKzwmEPNlh0LzitNKTxhA+J0PjE2vK+3Hsvk3K9/jFCiMB5OO0YOHUDEk0Iqa mp+Hz4rPQGT/A== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 49/55] clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriate Date: Mon, 20 Feb 2023 16:01:05 +0100 Message-Id: <20230220150111.77897-50-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt2701-aud.c | 1 + drivers/clk/mediatek/clk-mt2701-bdp.c | 1 + drivers/clk/mediatek/clk-mt2701-eth.c | 1 + drivers/clk/mediatek/clk-mt2701-g3d.c | 1 + drivers/clk/mediatek/clk-mt2701-hif.c | 1 + drivers/clk/mediatek/clk-mt2701-img.c | 1 + drivers/clk/mediatek/clk-mt2701-mm.c | 1 + drivers/clk/mediatek/clk-mt2701-vdec.c | 1 + drivers/clk/mediatek/clk-mt2701.c | 1 + drivers/clk/mediatek/clk-mt2712-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt2712-bdp.c | 1 + drivers/clk/mediatek/clk-mt2712-img.c | 1 + drivers/clk/mediatek/clk-mt2712-jpgdec.c | 1 + drivers/clk/mediatek/clk-mt2712-mfg.c | 1 + drivers/clk/mediatek/clk-mt2712-mm.c | 1 + drivers/clk/mediatek/clk-mt2712-vdec.c | 1 + drivers/clk/mediatek/clk-mt2712-venc.c | 1 + drivers/clk/mediatek/clk-mt2712.c | 1 + drivers/clk/mediatek/clk-mt6765-audio.c | 1 + drivers/clk/mediatek/clk-mt6765-cam.c | 1 + drivers/clk/mediatek/clk-mt6765-img.c | 1 + drivers/clk/mediatek/clk-mt6765-mipi0a.c | 1 + drivers/clk/mediatek/clk-mt6765-mm.c | 1 + drivers/clk/mediatek/clk-mt6765-vcodec.c | 1 + drivers/clk/mediatek/clk-mt6765.c | 1 + drivers/clk/mediatek/clk-mt6779-aud.c | 1 + drivers/clk/mediatek/clk-mt6779-cam.c | 1 + drivers/clk/mediatek/clk-mt6779-img.c | 1 + drivers/clk/mediatek/clk-mt6779-ipe.c | 1 + drivers/clk/mediatek/clk-mt6779-mfg.c | 1 + drivers/clk/mediatek/clk-mt6779-mm.c | 1 + drivers/clk/mediatek/clk-mt6779-vdec.c | 1 + drivers/clk/mediatek/clk-mt6779-venc.c | 1 + drivers/clk/mediatek/clk-mt6779.c | 1 + drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt6795-infracfg.c | 1 + drivers/clk/mediatek/clk-mt6795-mfg.c | 1 + drivers/clk/mediatek/clk-mt6795-mm.c | 1 + drivers/clk/mediatek/clk-mt6795-pericfg.c | 1 + drivers/clk/mediatek/clk-mt6795-topckgen.c | 1 + drivers/clk/mediatek/clk-mt6795-vdecsys.c | 1 + drivers/clk/mediatek/clk-mt6795-vencsys.c | 1 + drivers/clk/mediatek/clk-mt6797-img.c | 1 + drivers/clk/mediatek/clk-mt6797-mm.c | 1 + drivers/clk/mediatek/clk-mt6797-vdec.c | 1 + drivers/clk/mediatek/clk-mt6797-venc.c | 1 + drivers/clk/mediatek/clk-mt6797.c | 1 + drivers/clk/mediatek/clk-mt7622-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt7622-aud.c | 1 + drivers/clk/mediatek/clk-mt7622-eth.c | 1 + drivers/clk/mediatek/clk-mt7622-hif.c | 1 + drivers/clk/mediatek/clk-mt7622-infracfg.c | 1 + drivers/clk/mediatek/clk-mt7622.c | 1 + drivers/clk/mediatek/clk-mt7629-eth.c | 1 + drivers/clk/mediatek/clk-mt7629-hif.c | 1 + drivers/clk/mediatek/clk-mt7629.c | 1 + drivers/clk/mediatek/clk-mt7981-apmixed.c | 1 + drivers/clk/mediatek/clk-mt7981-eth.c | 1 + drivers/clk/mediatek/clk-mt7981-infracfg.c | 1 + drivers/clk/mediatek/clk-mt7981-topckgen.c | 1 + drivers/clk/mediatek/clk-mt7986-apmixed.c | 3 ++- drivers/clk/mediatek/clk-mt7986-eth.c | 1 + drivers/clk/mediatek/clk-mt7986-infracfg.c | 1 + drivers/clk/mediatek/clk-mt7986-topckgen.c | 1 + drivers/clk/mediatek/clk-mt8167-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8167-aud.c | 1 + drivers/clk/mediatek/clk-mt8167-img.c | 1 + drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 1 + drivers/clk/mediatek/clk-mt8167-mm.c | 1 + drivers/clk/mediatek/clk-mt8167-vdec.c | 1 + drivers/clk/mediatek/clk-mt8167.c | 1 + drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8173-img.c | 1 + drivers/clk/mediatek/clk-mt8173-infracfg.c | 1 + drivers/clk/mediatek/clk-mt8173-mm.c | 1 + drivers/clk/mediatek/clk-mt8173-pericfg.c | 1 + drivers/clk/mediatek/clk-mt8173-topckgen.c | 1 + drivers/clk/mediatek/clk-mt8173-vdecsys.c | 1 + drivers/clk/mediatek/clk-mt8173-vencsys.c | 1 + drivers/clk/mediatek/clk-mt8183-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8183-audio.c | 1 + drivers/clk/mediatek/clk-mt8183-cam.c | 1 + drivers/clk/mediatek/clk-mt8183-img.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu0.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu1.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 1 + drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 1 + drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 1 + drivers/clk/mediatek/clk-mt8183-mm.c | 1 + drivers/clk/mediatek/clk-mt8183-vdec.c | 1 + drivers/clk/mediatek/clk-mt8183-venc.c | 1 + drivers/clk/mediatek/clk-mt8183.c | 1 + drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8186-cam.c | 1 + drivers/clk/mediatek/clk-mt8186-img.c | 1 + drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c | 1 + drivers/clk/mediatek/clk-mt8186-infra_ao.c | 1 + drivers/clk/mediatek/clk-mt8186-ipe.c | 1 + drivers/clk/mediatek/clk-mt8186-mcu.c | 1 + drivers/clk/mediatek/clk-mt8186-mdp.c | 1 + drivers/clk/mediatek/clk-mt8186-mfg.c | 1 + drivers/clk/mediatek/clk-mt8186-mm.c | 2 ++ drivers/clk/mediatek/clk-mt8186-topckgen.c | 1 + drivers/clk/mediatek/clk-mt8186-vdec.c | 1 + drivers/clk/mediatek/clk-mt8186-venc.c | 1 + drivers/clk/mediatek/clk-mt8186-wpe.c | 1 + drivers/clk/mediatek/clk-mt8192-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8192-aud.c | 1 + drivers/clk/mediatek/clk-mt8192-cam.c | 1 + drivers/clk/mediatek/clk-mt8192-img.c | 1 + drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c | 1 + drivers/clk/mediatek/clk-mt8192-ipe.c | 1 + drivers/clk/mediatek/clk-mt8192-mdp.c | 1 + drivers/clk/mediatek/clk-mt8192-mfg.c | 1 + drivers/clk/mediatek/clk-mt8192-mm.c | 1 + drivers/clk/mediatek/clk-mt8192-msdc.c | 1 + drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 1 + drivers/clk/mediatek/clk-mt8192-vdec.c | 1 + drivers/clk/mediatek/clk-mt8192-venc.c | 1 + drivers/clk/mediatek/clk-mt8192.c | 1 + drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 1 + drivers/clk/mediatek/clk-mt8195-cam.c | 1 + drivers/clk/mediatek/clk-mt8195-ccu.c | 1 + drivers/clk/mediatek/clk-mt8195-img.c | 1 + drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c | 1 + drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 + drivers/clk/mediatek/clk-mt8195-ipe.c | 1 + drivers/clk/mediatek/clk-mt8195-mfg.c | 1 + drivers/clk/mediatek/clk-mt8195-peri_ao.c | 1 + drivers/clk/mediatek/clk-mt8195-scp_adsp.c | 1 + drivers/clk/mediatek/clk-mt8195-topckgen.c | 1 + drivers/clk/mediatek/clk-mt8195-vdec.c | 1 + drivers/clk/mediatek/clk-mt8195-venc.c | 1 + drivers/clk/mediatek/clk-mt8195-vpp0.c | 1 + drivers/clk/mediatek/clk-mt8195-vpp1.c | 1 + drivers/clk/mediatek/clk-mt8195-wpe.c | 1 + drivers/clk/mediatek/clk-mt8365-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8365-apu.c | 1 + drivers/clk/mediatek/clk-mt8365-cam.c | 1 + drivers/clk/mediatek/clk-mt8365-mfg.c | 1 + drivers/clk/mediatek/clk-mt8365-mm.c | 1 + drivers/clk/mediatek/clk-mt8365-vdec.c | 1 + drivers/clk/mediatek/clk-mt8365-venc.c | 1 + drivers/clk/mediatek/clk-mt8365.c | 1 + drivers/clk/mediatek/clk-mt8516-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8516-aud.c | 1 + drivers/clk/mediatek/clk-mt8516.c | 1 + 148 files changed, 150 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index 113ab5b0bf8d..5cd343b98685 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -124,6 +124,7 @@ static const struct of_device_id of_match_clk_mt2701_au= d[] =3D { { .compatible =3D "mediatek,mt2701-audsys", .data =3D &audio_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_aud); =20 static int clk_mt2701_aud_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/c= lk-mt2701-bdp.c index e7b43329d305..4c5b70d48df9 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -95,6 +95,7 @@ static const struct of_device_id of_match_clk_mt2701_bdp[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_bdp); =20 static struct platform_driver clk_mt2701_bdp_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index d30567ac4ff1..9a1fb0c93964 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -49,6 +49,7 @@ static const struct of_device_id of_match_clk_mt2701_eth[= ] =3D { { .compatible =3D "mediatek,mt2701-ethsys", .data =3D ð_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_eth); =20 static struct platform_driver clk_mt2701_eth_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 6f881eabdc67..c0006861a317 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -48,6 +48,7 @@ static const struct of_device_id of_match_clk_mt2701_g3d[= ] =3D { { .compatible =3D "mediatek,mt2701-g3dsys", .data =3D &g3d_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_g3d); =20 static struct platform_driver clk_mt2701_g3d_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index b2ee73c4de4e..ff7c0b3228e4 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -46,6 +46,7 @@ static const struct of_device_id of_match_clk_mt2701_hif[= ] =3D { { .compatible =3D "mediatek,mt2701-hifsys", .data =3D &hif_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_hif); =20 static struct platform_driver clk_mt2701_hif_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/c= lk-mt2701-img.c index 35a5fd938a6e..baa1194eb01e 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt2701_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_img); =20 static struct platform_driver clk_mt2701_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/cl= k-mt2701-mm.c index 75611d0ab865..c62c56fd2b7e 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -76,6 +76,7 @@ static const struct platform_device_id clk_mt2701_mm_id_t= able[] =3D { { .name =3D "clk-mt2701-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt2701_mm_id_table); =20 static struct platform_driver clk_mt2701_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/= clk-mt2701-vdec.c index dca4335a52a7..b7f97bc51c16 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -48,6 +48,7 @@ static const struct of_device_id of_match_clk_mt2701_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_vdec); =20 static struct platform_driver clk_mt2701_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index d3097d9f0c7a..4a154da8a543 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -999,6 +999,7 @@ static const struct of_device_id of_match_clk_mt2701[] = =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701); =20 static int clk_mt2701_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/med= iatek/clk-mt2712-apmixedsys.c index eade747d2812..9d2fcda285fb 100644 --- a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -154,6 +154,7 @@ static const struct of_device_id of_match_clk_mt2712_ap= mixed[] =3D { { .compatible =3D "mediatek,mt2712-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_apmixed); =20 static struct platform_driver clk_mt2712_apmixed_drv =3D { .probe =3D clk_mt2712_apmixed_probe, diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/c= lk-mt2712-bdp.c index d4979f2fb1d3..f78e01819316 100644 --- a/drivers/clk/mediatek/clk-mt2712-bdp.c +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c @@ -65,6 +65,7 @@ static const struct of_device_id of_match_clk_mt2712_bdp[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_bdp); =20 static struct platform_driver clk_mt2712_bdp_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/c= lk-mt2712-img.c index cd2d2af6bd56..fbe7084886a0 100644 --- a/drivers/clk/mediatek/clk-mt2712-img.c +++ b/drivers/clk/mediatek/clk-mt2712-img.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt2712_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_img); =20 static struct platform_driver clk_mt2712_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediate= k/clk-mt2712-jpgdec.c index 815be759e7c9..7e8c2ebcdee0 100644 --- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt2712_jpgd= ec[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_jpgdec); =20 static struct platform_driver clk_mt2712_jpgdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/c= lk-mt2712-mfg.c index 9f958fadca86..932ea449d299 100644 --- a/drivers/clk/mediatek/clk-mt2712-mfg.c +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c @@ -38,6 +38,7 @@ static const struct of_device_id of_match_clk_mt2712_mfg[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_mfg); =20 static struct platform_driver clk_mt2712_mfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/cl= k-mt2712-mm.c index 2649d67f2a56..204a3eae08dc 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -117,6 +117,7 @@ static const struct platform_device_id clk_mt2712_mm_id= _table[] =3D { { .name =3D "clk-mt2712-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt2712_mm_id_table); =20 static struct platform_driver clk_mt2712_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/= clk-mt2712-vdec.c index 1cb150fa7ab4..2fc1f82ebf5d 100644 --- a/drivers/clk/mediatek/clk-mt2712-vdec.c +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt2712_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_vdec); =20 static struct platform_driver clk_mt2712_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/= clk-mt2712-venc.c index 4073fa6c040f..6d053a00cf95 100644 --- a/drivers/clk/mediatek/clk-mt2712-venc.c +++ b/drivers/clk/mediatek/clk-mt2712-venc.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt2712_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_venc); =20 static struct platform_driver clk_mt2712_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index b2cf91622ebf..74c529f6163d 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -991,6 +991,7 @@ static const struct of_device_id of_match_clk_mt2712[] = =3D { { .compatible =3D "mediatek,mt2712-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712); =20 static struct platform_driver clk_mt2712_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek= /clk-mt6765-audio.c index c1fecf22f8ad..9e98d6997329 100644 --- a/drivers/clk/mediatek/clk-mt6765-audio.c +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -65,6 +65,7 @@ static const struct of_device_id of_match_clk_mt6765_audi= o[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_audio); =20 static struct platform_driver clk_mt6765_audio_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/c= lk-mt6765-cam.c index 15737c8f6b69..6f6b29d8b29a 100644 --- a/drivers/clk/mediatek/clk-mt6765-cam.c +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -46,6 +46,7 @@ static const struct of_device_id of_match_clk_mt6765_cam[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_cam); =20 static struct platform_driver clk_mt6765_cam_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/c= lk-mt6765-img.c index 7e421f4d01b8..984201077a20 100644 --- a/drivers/clk/mediatek/clk-mt6765-img.c +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -42,6 +42,7 @@ static const struct of_device_id of_match_clk_mt6765_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_img); =20 static struct platform_driver clk_mt6765_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediate= k/clk-mt6765-mipi0a.c index 17186a308e94..a47937f4efe5 100644 --- a/drivers/clk/mediatek/clk-mt6765-mipi0a.c +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt6765_mipi= 0a[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mipi0a); =20 static struct platform_driver clk_mt6765_mipi0a_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/cl= k-mt6765-mm.c index af2213db17cb..2b8fc052558e 100644 --- a/drivers/clk/mediatek/clk-mt6765-mm.c +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -68,6 +68,7 @@ static const struct of_device_id of_match_clk_mt6765_mm[]= =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mm); =20 static struct platform_driver clk_mt6765_mm_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediate= k/clk-mt6765-vcodec.c index 48014cc71d9f..36df9615b1be 100644 --- a/drivers/clk/mediatek/clk-mt6765-vcodec.c +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -41,6 +41,7 @@ static const struct of_device_id of_match_clk_mt6765_vcod= ec[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_vcodec); =20 static struct platform_driver clk_mt6765_vcodec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index 61f93b6fdf8b..fa7948ef1e68 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -840,6 +840,7 @@ static const struct of_device_id of_match_clk_mt6765[] = =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765); =20 static int clk_mt6765_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/c= lk-mt6779-aud.c index 6e473ae1fd90..6e3280d3a2e6 100644 --- a/drivers/clk/mediatek/clk-mt6779-aud.c +++ b/drivers/clk/mediatek/clk-mt6779-aud.c @@ -102,6 +102,7 @@ static const struct of_device_id of_match_clk_mt6779_au= d[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_aud); =20 static struct platform_driver clk_mt6779_aud_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/c= lk-mt6779-cam.c index 7be3db90fa4a..b4c4c7248672 100644 --- a/drivers/clk/mediatek/clk-mt6779-cam.c +++ b/drivers/clk/mediatek/clk-mt6779-cam.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt6779_cam[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_cam); =20 static struct platform_driver clk_mt6779_cam_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/c= lk-mt6779-img.c index 9bc51fc82dbd..b760a8af3462 100644 --- a/drivers/clk/mediatek/clk-mt6779-img.c +++ b/drivers/clk/mediatek/clk-mt6779-img.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt6779_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_img); =20 static struct platform_driver clk_mt6779_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/c= lk-mt6779-ipe.c index 92e9d1ade422..9285a792c59b 100644 --- a/drivers/clk/mediatek/clk-mt6779-ipe.c +++ b/drivers/clk/mediatek/clk-mt6779-ipe.c @@ -45,6 +45,7 @@ static const struct of_device_id of_match_clk_mt6779_ipe[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_ipe); =20 static struct platform_driver clk_mt6779_ipe_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/c= lk-mt6779-mfg.c index efc793a1969a..d20f32d4f827 100644 --- a/drivers/clk/mediatek/clk-mt6779-mfg.c +++ b/drivers/clk/mediatek/clk-mt6779-mfg.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt6779_mfg[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_mfg); =20 static struct platform_driver clk_mt6779_mfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/cl= k-mt6779-mm.c index 219a3a7920cd..c2f700ae6c2c 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -94,6 +94,7 @@ static const struct platform_device_id clk_mt6779_mm_id_t= able[] =3D { { .name =3D "clk-mt6779-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt6779_mm_id_table); =20 static struct platform_driver clk_mt6779_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/= clk-mt6779-vdec.c index 3209a6518d5b..e062ed5aa45f 100644 --- a/drivers/clk/mediatek/clk-mt6779-vdec.c +++ b/drivers/clk/mediatek/clk-mt6779-vdec.c @@ -52,6 +52,7 @@ static const struct of_device_id of_match_clk_mt6779_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_vdec); =20 static struct platform_driver clk_mt6779_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/= clk-mt6779-venc.c index c25035c0f334..0ae8ac28f838 100644 --- a/drivers/clk/mediatek/clk-mt6779-venc.c +++ b/drivers/clk/mediatek/clk-mt6779-venc.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt6779_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_venc); =20 static struct platform_driver clk_mt6779_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 827025d127d9..1f5ea1508f61 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1299,6 +1299,7 @@ static const struct of_device_id of_match_clk_mt6779_= infra[] =3D { { .compatible =3D "mediatek,mt6779-infracfg_ao", .data =3D &infra_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779); =20 static struct platform_driver clk_mt6779_infra_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6795-apmixedsys.c index 03fa30527868..8b30109f253c 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -131,6 +131,7 @@ static const struct of_device_id of_match_clk_mt6795_ap= mixed[] =3D { { .compatible =3D "mediatek,mt6795-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_apmixed); =20 static int clk_mt6795_apmixed_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/media= tek/clk-mt6795-infracfg.c index 23d9fc057e61..086ea1438564 100644 --- a/drivers/clk/mediatek/clk-mt6795-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c @@ -81,6 +81,7 @@ static const struct of_device_id of_match_clk_mt6795_infr= acfg[] =3D { { .compatible =3D "mediatek,mt6795-infracfg" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_infracfg); =20 static int clk_mt6795_infracfg_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt6795-mfg.c b/drivers/clk/mediatek/c= lk-mt6795-mfg.c index ee7aab24eb24..1d658bb19e82 100644 --- a/drivers/clk/mediatek/clk-mt6795-mfg.c +++ b/drivers/clk/mediatek/clk-mt6795-mfg.c @@ -35,6 +35,7 @@ static const struct of_device_id of_match_clk_mt6795_mfg[= ] =3D { { .compatible =3D "mediatek,mt6795-mfgcfg", .data =3D &mfg_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_mfg); =20 static struct platform_driver clk_mt6795_mfg_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt6795-mm.c b/drivers/clk/mediatek/cl= k-mt6795-mm.c index c0c61a08cd72..8acc9cad2875 100644 --- a/drivers/clk/mediatek/clk-mt6795-mm.c +++ b/drivers/clk/mediatek/clk-mt6795-mm.c @@ -85,6 +85,7 @@ static const struct platform_device_id clk_mt6795_mm_id_t= able[] =3D { { .name =3D "clk-mt6795-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt6795_mm_id_table); =20 static struct platform_driver clk_mt6795_mm_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediat= ek/clk-mt6795-pericfg.c index 08aaa9b09c36..62cc19eee2c7 100644 --- a/drivers/clk/mediatek/clk-mt6795-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c @@ -89,6 +89,7 @@ static const struct of_device_id of_match_clk_mt6795_peri= cfg[] =3D { { .compatible =3D "mediatek,mt6795-pericfg" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_pericfg); =20 static int clk_mt6795_pericfg_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt6795-topckgen.c b/drivers/clk/media= tek/clk-mt6795-topckgen.c index e80fa588e309..9c6d63a80b19 100644 --- a/drivers/clk/mediatek/clk-mt6795-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6795-topckgen.c @@ -539,6 +539,7 @@ static const struct of_device_id of_match_clk_mt6795_to= pckgen[] =3D { { .compatible =3D "mediatek,mt6795-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_topckgen); =20 static struct platform_driver clk_mt6795_topckgen_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt6795-vdecsys.c b/drivers/clk/mediat= ek/clk-mt6795-vdecsys.c index d85d04e0d016..f2968f859dca 100644 --- a/drivers/clk/mediatek/clk-mt6795-vdecsys.c +++ b/drivers/clk/mediatek/clk-mt6795-vdecsys.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt6795_vdec= sys[] =3D { { .compatible =3D "mediatek,mt6795-vdecsys", .data =3D &vdec_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vdecsys); =20 static struct platform_driver clk_mt6795_vdecsys_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6795-vencsys.c b/drivers/clk/mediat= ek/clk-mt6795-vencsys.c index de40a982ca96..2f8d48da1a85 100644 --- a/drivers/clk/mediatek/clk-mt6795-vencsys.c +++ b/drivers/clk/mediatek/clk-mt6795-vencsys.c @@ -35,6 +35,7 @@ static const struct of_device_id of_match_clk_mt6795_venc= sys[] =3D { { .compatible =3D "mediatek,mt6795-vencsys", .data =3D &venc_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vencsys); =20 static struct platform_driver clk_mt6795_vencsys_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/c= lk-mt6797-img.c index 22779829370f..00fc0a03e646 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt6797_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_img); =20 static struct platform_driver clk_mt6797_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index 8722fae10de9..caacfa40a5bc 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -89,6 +89,7 @@ static const struct platform_device_id clk_mt6797_mm_id_t= able[] =3D { { .name =3D "clk-mt6797-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt6797_mm_id_table); =20 static struct platform_driver clk_mt6797_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/= clk-mt6797-vdec.c index c5a82d4a958b..447fe6fa8e15 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -50,6 +50,7 @@ static const struct of_device_id of_match_clk_mt6797_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_vdec); =20 static struct platform_driver clk_mt6797_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/= clk-mt6797-venc.c index afdd288d313a..95b89ff8fd19 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -41,6 +41,7 @@ static const struct of_device_id of_match_clk_mt6797_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_venc); =20 static struct platform_driver clk_mt6797_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index 4094fd75d16e..4c87c0348e5f 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -670,6 +670,7 @@ static const struct of_device_id of_match_clk_mt6797[] = =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797); =20 static int clk_mt6797_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/med= iatek/clk-mt7622-apmixedsys.c index a9f3057d7080..a36808d074d6 100644 --- a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -136,6 +136,7 @@ static const struct of_device_id of_match_clk_mt7622_ap= mixed[] =3D { { .compatible =3D "mediatek,mt7622-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_apmixed); =20 static struct platform_driver clk_mt7622_apmixed_drv =3D { .probe =3D clk_mt7622_apmixed_probe, diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index 4e14a4ff465a..dd1799dd8435 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -145,6 +145,7 @@ static const struct of_device_id of_match_clk_mt7622_au= d[] =3D { { .compatible =3D "mediatek,mt7622-audsys", .data =3D &audio_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_aud); =20 static struct platform_driver clk_mt7622_aud_drv =3D { .probe =3D clk_mt7622_aud_probe, diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 4475d0846176..f96b36737029 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -77,6 +77,7 @@ static const struct of_device_id of_match_clk_mt7622_eth[= ] =3D { { .compatible =3D "mediatek,mt7622-sgmiisys", .data =3D &sgmii_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth); =20 static struct platform_driver clk_mt7622_eth_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index 19f394af1132..f440943f0d46 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -89,6 +89,7 @@ static const struct of_device_id of_match_clk_mt7622_hif[= ] =3D { { .compatible =3D "mediatek,mt7622-ssusbsys", .data =3D &ssusb_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_hif); =20 static struct platform_driver clk_mt7622_hif_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt7622-infracfg.c b/drivers/clk/media= tek/clk-mt7622-infracfg.c index 09d8ac4d483a..9dc05526f287 100644 --- a/drivers/clk/mediatek/clk-mt7622-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7622-infracfg.c @@ -55,6 +55,7 @@ static const struct of_device_id of_match_clk_mt7622_infr= acfg[] =3D { { .compatible =3D "mediatek,mt7622-infracfg" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg); =20 static int clk_mt7622_infracfg_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 7a002b73fcaa..274895264427 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -518,6 +518,7 @@ static const struct of_device_id of_match_clk_mt7622[] = =3D { { .compatible =3D "mediatek,mt7622-pericfg", .data =3D &peri_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622); =20 static struct platform_driver clk_mt7622_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index ee84a3de7f2c..1e1c77cc14ba 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -126,6 +126,7 @@ static const struct of_device_id of_match_clk_mt7629_et= h[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_eth); =20 static int clk_mt7629_eth_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 464c4131d98a..c89036bee9a7 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -84,6 +84,7 @@ static const struct of_device_id of_match_clk_mt7629_hif[= ] =3D { { .compatible =3D "mediatek,mt7629-ssusbsys", .data =3D &ssusb_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_hif); =20 static struct platform_driver clk_mt7629_hif_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index f3279f002e93..0893fbbb68cc 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -660,6 +660,7 @@ static const struct of_device_id of_match_clk_mt7629[] = =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7629); =20 static int clk_mt7629_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediat= ek/clk-mt7981-apmixed.c index 53c974c66f89..875813d8b4a9 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -66,6 +66,7 @@ static const struct of_device_id of_match_clk_mt7981_apmi= xed[] =3D { { .compatible =3D "mediatek,mt7981-apmixedsys", }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_apmixed); =20 static int clk_mt7981_apmixed_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt7981-eth.c b/drivers/clk/mediatek/c= lk-mt7981-eth.c index f27fadd6bf94..b1f256b5ed4e 100644 --- a/drivers/clk/mediatek/clk-mt7981-eth.c +++ b/drivers/clk/mediatek/clk-mt7981-eth.c @@ -105,6 +105,7 @@ static const struct of_device_id of_match_clk_mt7981_et= h[] =3D { { .compatible =3D "mediatek,mt7981-sgmiisys_1", .data =3D &sgmii1_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_eth); =20 static struct platform_driver clk_mt7981_eth_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/media= tek/clk-mt7981-infracfg.c index d1709323d34e..293261ef71e6 100644 --- a/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c @@ -195,6 +195,7 @@ static const struct of_device_id of_match_clk_mt7981_in= fracfg[] =3D { { .compatible =3D "mediatek,mt7981-infracfg", .data =3D &infracfg_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_infracfg); =20 static struct platform_driver clk_mt7981_infracfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/media= tek/clk-mt7981-topckgen.c index e09ffc22b13a..3aba1a9b9a36 100644 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -410,6 +410,7 @@ static const struct of_device_id of_match_clk_mt7981_to= pckgen[] =3D { { .compatible =3D "mediatek,mt7981-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_topckgen); =20 static struct platform_driver clk_mt7981_topckgen_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediat= ek/clk-mt7986-apmixed.c index dc949ed1b587..6767e9c43886 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -62,8 +62,9 @@ static const struct mtk_pll_data plls[] =3D { =20 static const struct of_device_id of_match_clk_mt7986_apmixed[] =3D { { .compatible =3D "mediatek,mt7986-apmixedsys", }, - {} + { } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_apmixed); =20 static int clk_mt7986_apmixed_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/c= lk-mt7986-eth.c index 138ba0a47221..0681988960cc 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -86,6 +86,7 @@ static const struct of_device_id of_match_clk_mt7986_eth[= ] =3D { { .compatible =3D "mediatek,mt7986-sgmiisys_1", .data =3D &sgmii1_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_eth); =20 static struct platform_driver clk_mt7986_eth_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/media= tek/clk-mt7986-infracfg.c index 0299faad0733..b7efa70c2d6c 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -171,6 +171,7 @@ static const struct of_device_id of_match_clk_mt7986_in= fracfg[] =3D { { .compatible =3D "mediatek,mt7986-infracfg", .data =3D &infra_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_infracfg); =20 static struct platform_driver clk_mt7986_infracfg_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/media= tek/clk-mt7986-topckgen.c index af9df453d6d7..fbca3feded8f 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -304,6 +304,7 @@ static const struct of_device_id of_match_clk_mt7986_to= pckgen[] =3D { { .compatible =3D "mediatek,mt7986-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_topckgen); =20 static struct platform_driver clk_mt7986_topckgen_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8167-apmixedsys.c index 5d8b5093ed02..fca41f50d6ba 100644 --- a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -132,6 +132,7 @@ static const struct of_device_id of_match_clk_mt8167_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8167-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_apmixed); =20 static struct platform_driver clk_mt8167_apmixed_drv =3D { .probe =3D clk_mt8167_apmixed_probe, diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index 63736642f383..86125635c8a6 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -52,6 +52,7 @@ static const struct of_device_id of_match_clk_mt8167_auds= ys[] =3D { { .compatible =3D "mediatek,mt8167-audsys", .data =3D &aud_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_audsys); =20 static struct platform_driver clk_mt8167_audsys_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index c2537e149aa8..315b7f64bad6 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -44,6 +44,7 @@ static const struct of_device_id of_match_clk_mt8167_imgs= ys[] =3D { { .compatible =3D "mediatek,mt8167-imgsys", .data =3D &img_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_imgsys); =20 static struct platform_driver clk_mt8167_imgsys_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 340c608e7ddb..4851f5bf3a90 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -42,6 +42,7 @@ static const struct of_device_id of_match_clk_mt8167_mfgc= fg[] =3D { { .compatible =3D "mediatek,mt8167-mfgcfg", .data =3D &mfg_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_mfgcfg); =20 static struct platform_driver clk_mt8167_mfgcfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/cl= k-mt8167-mm.c index 0344f9c98d36..4e053c61315d 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -83,6 +83,7 @@ static const struct platform_device_id clk_mt8167_mm_id_t= able[] =3D { { .name =3D "clk-mt8167-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8167_mm_id_table); =20 static struct platform_driver clk_mt8167_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index 35b0380f22dc..76900f393d31 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt8167_vdec= [] =3D { { .compatible =3D "mediatek,mt8167-vdecsys", .data =3D &vdec_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_vdec); =20 static struct platform_driver clk_mt8167_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index d9a837686865..b9041f79cbbd 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -883,6 +883,7 @@ static const struct of_device_id of_match_clk_mt8167[] = =3D { { .compatible =3D "mediatek,mt8167-infracfg", .data =3D &infra_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167); =20 static struct platform_driver clk_mt8167_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8173-apmixedsys.c index 0084203e67ad..8c2aa8b0f39e 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -135,6 +135,7 @@ static const struct of_device_id of_match_clk_mt8173_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8173-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed); =20 static int clk_mt8173_apmixed_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt8173-img.c b/drivers/clk/mediatek/c= lk-mt8173-img.c index 7b50ffb7a8a5..6db2b9ab2bc9 100644 --- a/drivers/clk/mediatek/clk-mt8173-img.c +++ b/drivers/clk/mediatek/clk-mt8173-img.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8173_imgs= ys[] =3D { { .compatible =3D "mediatek,mt8173-imgsys", .data =3D &img_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_imgsys); =20 static struct platform_driver clk_mt8173_vdecsys_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/media= tek/clk-mt8173-infracfg.c index 729b3c408c7b..4ed5043076ec 100644 --- a/drivers/clk/mediatek/clk-mt8173-infracfg.c +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -74,6 +74,7 @@ static const struct of_device_id of_match_clk_mt8173_infr= acfg[] =3D { { .compatible =3D "mediatek,mt8173-infracfg" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg); =20 static void clk_mt8173_infra_init_early(struct device_node *node) { diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/cl= k-mt8173-mm.c index ba51c22cbe7a..18e466dbf610 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -98,6 +98,7 @@ static const struct platform_device_id clk_mt8173_mm_id_t= able[] =3D { { .name =3D "clk-mt8173-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8173_mm_id_table); =20 static struct platform_driver clk_mt8173_mm_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt8173-pericfg.c b/drivers/clk/mediat= ek/clk-mt8173-pericfg.c index e87294b72c2c..bebda74d0f43 100644 --- a/drivers/clk/mediatek/clk-mt8173-pericfg.c +++ b/drivers/clk/mediatek/clk-mt8173-pericfg.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8173_pe= ricfg[] =3D { { .compatible =3D "mediatek,mt8173-pericfg", .data =3D &peri_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_pericfg); =20 static struct platform_driver clk_mt8173_pericfg_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt8173-topckgen.c b/drivers/clk/media= tek/clk-mt8173-topckgen.c index 257961528fe2..baa8fd6cb312 100644 --- a/drivers/clk/mediatek/clk-mt8173-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8173-topckgen.c @@ -638,6 +638,7 @@ static const struct of_device_id of_match_clk_mt8173_to= pckgen[] =3D { { .compatible =3D "mediatek,mt8173-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_topckgen); =20 static struct platform_driver clk_mt8173_topckgen_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt8173-vdecsys.c b/drivers/clk/mediat= ek/clk-mt8173-vdecsys.c index 5105b8e0969d..625ca0b09cc2 100644 --- a/drivers/clk/mediatek/clk-mt8173-vdecsys.c +++ b/drivers/clk/mediatek/clk-mt8173-vdecsys.c @@ -42,6 +42,7 @@ static const struct of_device_id of_match_clk_mt8173_vdec= sys[] =3D { { .compatible =3D "mediatek,mt8173-vdecsys", .data =3D &vdec_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vdecsys); =20 static struct platform_driver clk_mt8173_vdecsys_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8173-vencsys.c b/drivers/clk/mediat= ek/clk-mt8173-vencsys.c index ff4f1cb735de..87755dd1a337 100644 --- a/drivers/clk/mediatek/clk-mt8173-vencsys.c +++ b/drivers/clk/mediatek/clk-mt8173-vencsys.c @@ -49,6 +49,7 @@ static const struct of_device_id of_match_clk_mt8173_venc= sys[] =3D { { .compatible =3D "mediatek,mt8173-vencltsys", .data =3D &venc_lt_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vencsys); =20 static struct platform_driver clk_mt8173_vencsys_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8183-apmixedsys.c index 5addda17211f..2b261c0e2b61 100644 --- a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -182,6 +182,7 @@ static const struct of_device_id of_match_clk_mt8183_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8183-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_apmixed); =20 static struct platform_driver clk_mt8183_apmixed_drv =3D { .probe =3D clk_mt8183_apmixed_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek= /clk-mt8183-audio.c index fe510f02dadb..9938c6466e76 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -97,6 +97,7 @@ static const struct of_device_id of_match_clk_mt8183_audi= o[] =3D { { .compatible =3D "mediatek,mt8183-audiosys", .data =3D &audio_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_audio); =20 static struct platform_driver clk_mt8183_audio_drv =3D { .probe =3D clk_mt8183_audio_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-cam.c b/drivers/clk/mediatek/c= lk-mt8183-cam.c index 7ecbfc50e8fe..c0719624004f 100644 --- a/drivers/clk/mediatek/clk-mt8183-cam.c +++ b/drivers/clk/mediatek/clk-mt8183-cam.c @@ -47,6 +47,7 @@ static const struct of_device_id of_match_clk_mt8183_cam[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_cam); =20 static struct platform_driver clk_mt8183_cam_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/c= lk-mt8183-img.c index e75d6e6205f9..55fc80615724 100644 --- a/drivers/clk/mediatek/clk-mt8183-img.c +++ b/drivers/clk/mediatek/clk-mt8183-img.c @@ -47,6 +47,7 @@ static const struct of_device_id of_match_clk_mt8183_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_img); =20 static struct platform_driver clk_mt8183_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-ipu0.c b/drivers/clk/mediatek/= clk-mt8183-ipu0.c index d1dd76e7eafd..59255eab6fe2 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu0.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu0.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8183_ipu_= core0[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_core0); =20 static struct platform_driver clk_mt8183_ipu_core0_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-ipu1.c b/drivers/clk/mediatek/= clk-mt8183-ipu1.c index 0b4906cca119..c4baa052c809 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu1.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu1.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8183_ipu_= core1[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_core1); =20 static struct platform_driver clk_mt8183_ipu_core1_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c b/drivers/clk/mediat= ek/clk-mt8183-ipu_adl.c index 32a82ec965ef..74866e9c50d7 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c @@ -38,6 +38,7 @@ static const struct of_device_id of_match_clk_mt8183_ipu_= adl[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_adl); =20 static struct platform_driver clk_mt8183_ipu_adl_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c b/drivers/clk/media= tek/clk-mt8183-ipu_conn.c index 1e2ebc0eab8b..bd7303105357 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8183_ip= u_conn[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_conn); =20 static struct platform_driver clk_mt8183_ipu_conn_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8183-mfgcfg.c index 20cdbd74817f..816ecf1191ee 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8183_mfg[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_mfg); =20 static struct platform_driver clk_mt8183_mfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/cl= k-mt8183-mm.c index a76e44ebf322..2f99828bff1b 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -91,6 +91,7 @@ static const struct platform_device_id clk_mt8183_mm_id_t= able[] =3D { { .name =3D "clk-mt8183-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8183_mm_id_table); =20 static struct platform_driver clk_mt8183_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/= clk-mt8183-vdec.c index 0182745e2a18..513b7956cbea 100644 --- a/drivers/clk/mediatek/clk-mt8183-vdec.c +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt8183_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_vdec); =20 static struct platform_driver clk_mt8183_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183-venc.c b/drivers/clk/mediatek/= clk-mt8183-venc.c index c840e6ebe375..532f6e12a561 100644 --- a/drivers/clk/mediatek/clk-mt8183-venc.c +++ b/drivers/clk/mediatek/clk-mt8183-venc.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt8183_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_venc); =20 static struct platform_driver clk_mt8183_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 5ae0f1f9ca0a..2336a1b69c09 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -868,6 +868,7 @@ static const struct of_device_id of_match_clk_mt8183[] = =3D { { .compatible =3D "mediatek,mt8183-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183); =20 static struct platform_driver clk_mt8183_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index e429d2cdc84a..da7950d51c64 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -136,6 +136,7 @@ static const struct of_device_id of_match_clk_mt8186_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8186-apmixedsys", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_apmixed); =20 static int clk_mt8186_apmixed_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt8186-cam.c b/drivers/clk/mediatek/c= lk-mt8186-cam.c index 90d91d045909..656d9e6f3ee2 100644 --- a/drivers/clk/mediatek/clk-mt8186-cam.c +++ b/drivers/clk/mediatek/clk-mt8186-cam.c @@ -78,6 +78,7 @@ static const struct of_device_id of_match_clk_mt8186_cam[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_cam); =20 static struct platform_driver clk_mt8186_cam_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-img.c b/drivers/clk/mediatek/c= lk-mt8186-img.c index 11314dba4e41..754b27f03817 100644 --- a/drivers/clk/mediatek/clk-mt8186-img.c +++ b/drivers/clk/mediatek/clk-mt8186-img.c @@ -56,6 +56,7 @@ static const struct of_device_id of_match_clk_mt8186_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_img); =20 static struct platform_driver clk_mt8186_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8186-imp_iic_wrap.c index f8d1ee294f09..7619c357b150 100644 --- a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c @@ -55,6 +55,7 @@ static const struct of_device_id of_match_clk_mt8186_imp_= iic_wrap[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_imp_iic_wrap); =20 static struct platform_driver clk_mt8186_imp_iic_wrap_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-infra_ao.c b/drivers/clk/media= tek/clk-mt8186-infra_ao.c index 766c8e6bcf8d..a907a5def5b8 100644 --- a/drivers/clk/mediatek/clk-mt8186-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8186-infra_ao.c @@ -227,6 +227,7 @@ static const struct of_device_id of_match_clk_mt8186_in= fra_ao[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_infra_ao); =20 static struct platform_driver clk_mt8186_infra_ao_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-ipe.c b/drivers/clk/mediatek/c= lk-mt8186-ipe.c index 0876440839df..50e340035aa7 100644 --- a/drivers/clk/mediatek/clk-mt8186-ipe.c +++ b/drivers/clk/mediatek/clk-mt8186-ipe.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt8186_ipe[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_ipe); =20 static struct platform_driver clk_mt8186_ipe_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-mcu.c b/drivers/clk/mediatek/c= lk-mt8186-mcu.c index 895856df95df..d1640e4dc2ad 100644 --- a/drivers/clk/mediatek/clk-mt8186-mcu.c +++ b/drivers/clk/mediatek/clk-mt8186-mcu.c @@ -52,6 +52,7 @@ static const struct of_device_id of_match_clk_mt8186_mcu[= ] =3D { { .compatible =3D "mediatek,mt8186-mcusys", .data =3D &mcu_desc }, { /* sentinel */} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mcu); =20 static struct platform_driver clk_mt8186_mcu_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt8186-mdp.c b/drivers/clk/mediatek/c= lk-mt8186-mdp.c index 194f20f16f8c..e1d19007e375 100644 --- a/drivers/clk/mediatek/clk-mt8186-mdp.c +++ b/drivers/clk/mediatek/clk-mt8186-mdp.c @@ -68,6 +68,7 @@ static const struct of_device_id of_match_clk_mt8186_mdp[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mdp); =20 static struct platform_driver clk_mt8186_mdp_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-mfg.c b/drivers/clk/mediatek/c= lk-mt8186-mfg.c index f16d3c44ef41..aeb098b54585 100644 --- a/drivers/clk/mediatek/clk-mt8186-mfg.c +++ b/drivers/clk/mediatek/clk-mt8186-mfg.c @@ -37,6 +37,7 @@ static const struct of_device_id of_match_clk_mt8186_mfg[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mfg); =20 static struct platform_driver clk_mt8186_mfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/cl= k-mt8186-mm.c index 9e9853a2ea91..fc3bb6d1f714 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -67,6 +67,8 @@ static const struct platform_device_id clk_mt8186_mm_id_t= able[] =3D { { .name =3D "clk-mt8186-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8186_mm_id_table); + static struct platform_driver clk_mt8186_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, .remove =3D mtk_clk_pdev_remove, diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/media= tek/clk-mt8186-topckgen.c index a48172d9c5ab..1a0340a20beb 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -721,6 +721,7 @@ static const struct of_device_id of_match_clk_mt8186_to= pck[] =3D { { .compatible =3D "mediatek,mt8186-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_topck); =20 static struct platform_driver clk_mt8186_topck_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-vdec.c b/drivers/clk/mediatek/= clk-mt8186-vdec.c index 877ca9d8ff65..9bf3b8632870 100644 --- a/drivers/clk/mediatek/clk-mt8186-vdec.c +++ b/drivers/clk/mediatek/clk-mt8186-vdec.c @@ -76,6 +76,7 @@ static const struct of_device_id of_match_clk_mt8186_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_vdec); =20 static struct platform_driver clk_mt8186_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-venc.c b/drivers/clk/mediatek/= clk-mt8186-venc.c index a89e82285d4c..0c1bc94e84cf 100644 --- a/drivers/clk/mediatek/clk-mt8186-venc.c +++ b/drivers/clk/mediatek/clk-mt8186-venc.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8186_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_venc); =20 static struct platform_driver clk_mt8186_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8186-wpe.c b/drivers/clk/mediatek/c= lk-mt8186-wpe.c index fba55f08129c..c4727b1cb64d 100644 --- a/drivers/clk/mediatek/clk-mt8186-wpe.c +++ b/drivers/clk/mediatek/clk-mt8186-wpe.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8186_wpe[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_wpe); =20 static struct platform_driver clk_mt8186_wpe_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8192-apmixedsys.c index 1e6988d5289a..eafd34297b9a 100644 --- a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -147,6 +147,7 @@ static const struct of_device_id of_match_clk_mt8192_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8192-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed); =20 static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/c= lk-mt8192-aud.c index 9b14d8514b4f..ee251492d4f1 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8192_au= d[] =3D { { .compatible =3D "mediatek,mt8192-audsys", .data =3D &aud_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_aud); =20 static struct platform_driver clk_mt8192_aud_drv =3D { .probe =3D clk_mt8192_aud_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/c= lk-mt8192-cam.c index 321693aff33f..7befd6ee8c79 100644 --- a/drivers/clk/mediatek/clk-mt8192-cam.c +++ b/drivers/clk/mediatek/clk-mt8192-cam.c @@ -95,6 +95,7 @@ static const struct of_device_id of_match_clk_mt8192_cam[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_cam); =20 static struct platform_driver clk_mt8192_cam_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/c= lk-mt8192-img.c index b2c148ead7f8..a7505150a9d0 100644 --- a/drivers/clk/mediatek/clk-mt8192-img.c +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -58,6 +58,7 @@ static const struct of_device_id of_match_clk_mt8192_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_img); =20 static struct platform_driver clk_mt8192_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8192-imp_iic_wrap.c index fd731eb6d62e..cd5d00a7c54b 100644 --- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8192_im= p_iic_wrap[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_imp_iic_wrap); =20 static struct platform_driver clk_mt8192_imp_iic_wrap_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/c= lk-mt8192-ipe.c index 3fd37977ea16..dee671ae38e6 100644 --- a/drivers/clk/mediatek/clk-mt8192-ipe.c +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c @@ -45,6 +45,7 @@ static const struct of_device_id of_match_clk_mt8192_ipe[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_ipe); =20 static struct platform_driver clk_mt8192_ipe_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/c= lk-mt8192-mdp.c index 817e8bf4543b..f7b27264e378 100644 --- a/drivers/clk/mediatek/clk-mt8192-mdp.c +++ b/drivers/clk/mediatek/clk-mt8192-mdp.c @@ -70,6 +70,7 @@ static const struct of_device_id of_match_clk_mt8192_mdp[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_mdp); =20 static struct platform_driver clk_mt8192_mdp_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/c= lk-mt8192-mfg.c index 7f77e2d8b765..85f76a2bbac4 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8192_mfg[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_mfg); =20 static struct platform_driver clk_mt8192_mfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/cl= k-mt8192-mm.c index 3e81018a038b..47335d517714 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -89,6 +89,7 @@ static const struct platform_device_id clk_mt8192_mm_id_t= able[] =3D { { .name =3D "clk-mt8192-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8192_mm_id_table); =20 static struct platform_driver clk_mt8192_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/= clk-mt8192-msdc.c index cde8c88673e4..60d65f96d39a 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -52,6 +52,7 @@ static const struct of_device_id of_match_clk_mt8192_msdc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_msdc); =20 static struct platform_driver clk_mt8192_msdc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/media= tek/clk-mt8192-scp_adsp.c index df086b95d447..6aad57797c39 100644 --- a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c @@ -38,6 +38,7 @@ static const struct of_device_id of_match_clk_mt8192_scp_= adsp[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_scp_adsp); =20 static struct platform_driver clk_mt8192_scp_adsp_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/= clk-mt8192-vdec.c index 2ea8b6d4d405..473afd58495c 100644 --- a/drivers/clk/mediatek/clk-mt8192-vdec.c +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -82,6 +82,7 @@ static const struct of_device_id of_match_clk_mt8192_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_vdec); =20 static struct platform_driver clk_mt8192_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/= clk-mt8192-venc.c index d73c12bc2ae9..57b1b16e2310 100644 --- a/drivers/clk/mediatek/clk-mt8192-venc.c +++ b/drivers/clk/mediatek/clk-mt8192-venc.c @@ -41,6 +41,7 @@ static const struct of_device_id of_match_clk_mt8192_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_venc); =20 static struct platform_driver clk_mt8192_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 45eccda51471..aa11291463f7 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1019,6 +1019,7 @@ static const struct of_device_id of_match_clk_mt8192[= ] =3D { { .compatible =3D "mediatek,mt8192-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192); =20 static struct platform_driver clk_mt8192_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index 75cc4d7a39f9..8b9b5d820286 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -166,6 +166,7 @@ static const struct of_device_id of_match_clk_mt8195_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8195-apmixedsys", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed); =20 static int clk_mt8195_apmixed_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/med= iatek/clk-mt8195-apusys_pll.c index b167b8d31bcc..de04c087c8c3 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -101,6 +101,7 @@ static const struct of_device_id of_match_clk_mt8195_ap= usys_pll[] =3D { { .compatible =3D "mediatek,mt8195-apusys_pll", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apusys_pll); =20 static struct platform_driver clk_mt8195_apusys_pll_drv =3D { .probe =3D clk_mt8195_apusys_pll_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-cam.c b/drivers/clk/mediatek/c= lk-mt8195-cam.c index c515650214bd..77e608be579a 100644 --- a/drivers/clk/mediatek/clk-mt8195-cam.c +++ b/drivers/clk/mediatek/clk-mt8195-cam.c @@ -131,6 +131,7 @@ static const struct of_device_id of_match_clk_mt8195_ca= m[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_cam); =20 static struct platform_driver clk_mt8195_cam_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/c= lk-mt8195-ccu.c index a86f848a785d..bdc2e6f3e9ce 100644 --- a/drivers/clk/mediatek/clk-mt8195-ccu.c +++ b/drivers/clk/mediatek/clk-mt8195-ccu.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8195_ccu[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_ccu); =20 static struct platform_driver clk_mt8195_ccu_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/c= lk-mt8195-img.c index 214baa2bc974..d853e0e63d87 100644 --- a/drivers/clk/mediatek/clk-mt8195-img.c +++ b/drivers/clk/mediatek/clk-mt8195-img.c @@ -85,6 +85,7 @@ static const struct of_device_id of_match_clk_mt8195_img[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_img); =20 static struct platform_driver clk_mt8195_img_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/m= ediatek/clk-mt8195-imp_iic_wrap.c index 191f482186ae..1d808876f5c5 100644 --- a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c @@ -55,6 +55,7 @@ static const struct of_device_id of_match_clk_mt8195_imp_= iic_wrap[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_imp_iic_wrap); =20 static struct platform_driver clk_mt8195_imp_iic_wrap_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/media= tek/clk-mt8195-infra_ao.c index 6ad72a320d5e..f3ee4390707d 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -229,6 +229,7 @@ static const struct of_device_id of_match_clk_mt8195_in= fra_ao[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_infra_ao); =20 static struct platform_driver clk_mt8195_infra_ao_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/c= lk-mt8195-ipe.c index b547a99b4ad9..4c47f6521275 100644 --- a/drivers/clk/mediatek/clk-mt8195-ipe.c +++ b/drivers/clk/mediatek/clk-mt8195-ipe.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8195_ipe[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_ipe); =20 static struct platform_driver clk_mt8195_ipe_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/c= lk-mt8195-mfg.c index 75cf643ab885..038acf0b1167 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -38,6 +38,7 @@ static const struct of_device_id of_match_clk_mt8195_mfg[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_mfg); =20 static struct platform_driver clk_mt8195_mfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-peri_ao.c b/drivers/clk/mediat= ek/clk-mt8195-peri_ao.c index 7d65a478182d..0de162593c01 100644 --- a/drivers/clk/mediatek/clk-mt8195-peri_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-peri_ao.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt8195_peri= _ao[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_peri_ao); =20 static struct platform_driver clk_mt8195_peri_ao_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c b/drivers/clk/media= tek/clk-mt8195-scp_adsp.c index 24e09339ed7d..d0d3e3b09780 100644 --- a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c @@ -36,6 +36,7 @@ static const struct of_device_id of_match_clk_mt8195_scp_= adsp[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_scp_adsp); =20 static struct platform_driver clk_mt8195_scp_adsp_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index adc6bb7ce750..3c2174c3e742 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1219,6 +1219,7 @@ static const struct of_device_id of_match_clk_mt8195_= topck[] =3D { { .compatible =3D "mediatek,mt8195-topckgen", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_topck); =20 /* Register mux notifier for MFG mux */ static int clk_mt8195_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/= clk-mt8195-vdec.c index f9e2bd402627..2bcbceb10326 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdec.c +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c @@ -93,6 +93,7 @@ static const struct of_device_id of_match_clk_mt8195_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_vdec); =20 static struct platform_driver clk_mt8195_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/= clk-mt8195-venc.c index d050d87bb3f2..0991a6968765 100644 --- a/drivers/clk/mediatek/clk-mt8195-venc.c +++ b/drivers/clk/mediatek/clk-mt8195-venc.c @@ -58,6 +58,7 @@ static const struct of_device_id of_match_clk_mt8195_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_venc); =20 static struct platform_driver clk_mt8195_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/= clk-mt8195-vpp0.c index 84805a114387..3d1ad92b663e 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -95,6 +95,7 @@ static const struct platform_device_id clk_mt8195_vpp0_id= _table[] =3D { { .name =3D "clk-mt8195-vpp0", .driver_data =3D (kernel_ulong_t)&vpp0_des= c }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, of_match_clk_mt8195_vpp0); =20 static struct platform_driver clk_mt8195_vpp0_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/= clk-mt8195-vpp1.c index 3e91dfed2996..b463f8e197c6 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -93,6 +93,7 @@ static const struct platform_device_id clk_mt8195_vpp1_id= _table[] =3D { { .name =3D "clk-mt8195-vpp1", .driver_data =3D (kernel_ulong_t)&vpp1_des= c }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, of_match_clk_mt8195_vpp1); =20 static struct platform_driver clk_mt8195_vpp1_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/c= lk-mt8195-wpe.c index 52cebe297abf..289896cb2f6c 100644 --- a/drivers/clk/mediatek/clk-mt8195-wpe.c +++ b/drivers/clk/mediatek/clk-mt8195-wpe.c @@ -132,6 +132,7 @@ static const struct of_device_id of_match_clk_mt8195_wp= e[] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_wpe); =20 static struct platform_driver clk_mt8195_wpe_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8365-apmixedsys.c index 55faa4e37116..9b0bc5daeac0 100644 --- a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -153,6 +153,7 @@ static const struct of_device_id of_match_clk_mt8365_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8365-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apmixed); =20 static struct platform_driver clk_mt8365_apmixed_drv =3D { .probe =3D clk_mt8365_apmixed_probe, diff --git a/drivers/clk/mediatek/clk-mt8365-apu.c b/drivers/clk/mediatek/c= lk-mt8365-apu.c index 5a594f8eccdc..74f7fb22c87f 100644 --- a/drivers/clk/mediatek/clk-mt8365-apu.c +++ b/drivers/clk/mediatek/clk-mt8365-apu.c @@ -42,6 +42,7 @@ static const struct of_device_id of_match_clk_mt8365_apu[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apu); =20 static struct platform_driver clk_mt8365_apu_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8365-cam.c b/drivers/clk/mediatek/c= lk-mt8365-cam.c index ed1d8dd7043c..61516e19acd1 100644 --- a/drivers/clk/mediatek/clk-mt8365-cam.c +++ b/drivers/clk/mediatek/clk-mt8365-cam.c @@ -44,6 +44,7 @@ static const struct of_device_id of_match_clk_mt8365_cam[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_cam); =20 static struct platform_driver clk_mt8365_cam_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8365-mfg.c b/drivers/clk/mediatek/c= lk-mt8365-mfg.c index b3d10b017f0d..4c836c69db4f 100644 --- a/drivers/clk/mediatek/clk-mt8365-mfg.c +++ b/drivers/clk/mediatek/clk-mt8365-mfg.c @@ -50,6 +50,7 @@ static const struct of_device_id of_match_clk_mt8365_mfg[= ] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_mfg); =20 static struct platform_driver clk_mt8365_mfg_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/cl= k-mt8365-mm.c index 7ae33997ba86..44427120846f 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -81,6 +81,7 @@ static const struct platform_device_id clk_mt8365_mm_id_t= able[] =3D { { .name =3D "clk-mt8365-mm", .driver_data =3D (kernel_ulong_t)&mm_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8365_mm_id_table); =20 static struct platform_driver clk_mt8365_mm_drv =3D { .probe =3D mtk_clk_pdev_probe, diff --git a/drivers/clk/mediatek/clk-mt8365-vdec.c b/drivers/clk/mediatek/= clk-mt8365-vdec.c index d5caddcc5932..b51571e9da00 100644 --- a/drivers/clk/mediatek/clk-mt8365-vdec.c +++ b/drivers/clk/mediatek/clk-mt8365-vdec.c @@ -50,6 +50,7 @@ static const struct of_device_id of_match_clk_mt8365_vdec= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_vdec); =20 static struct platform_driver clk_mt8365_vdec_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8365-venc.c b/drivers/clk/mediatek/= clk-mt8365-venc.c index 08b7c0ee52e7..572344645c86 100644 --- a/drivers/clk/mediatek/clk-mt8365-venc.c +++ b/drivers/clk/mediatek/clk-mt8365-venc.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8365_venc= [] =3D { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_venc); =20 static struct platform_driver clk_mt8365_venc_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index 208cdc157918..6b4e193f648d 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -791,6 +791,7 @@ static const struct of_device_id of_match_clk_mt8365[] = =3D { { .compatible =3D "mediatek,mt8365-mcucfg", .data =3D &mcu_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365); =20 static struct platform_driver clk_mt8365_drv =3D { .driver =3D { diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8516-apmixedsys.c index 5b87c9fb81f5..edd9174d2f2f 100644 --- a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8516_ap= mixed[] =3D { { .compatible =3D "mediatek,mt8516-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed); =20 static struct platform_driver clk_mt8516_apmixed_drv =3D { .probe =3D clk_mt8516_apmixed_probe, diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/c= lk-mt8516-aud.c index 5f34487aad7e..48340fc7430d 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt8516_aud[= ] =3D { { .compatible =3D "mediatek,mt8516-audsys", .data =3D &aud_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_aud); =20 static struct platform_driver clk_mt8516_aud_drv =3D { .probe =3D mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index ad59e932d4aa..21eb052b0a53 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -665,6 +665,7 @@ static const struct of_device_id of_match_clk_mt8516[] = =3D { { .compatible =3D "mediatek,mt8516-infracfg", .data =3D &infra_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8516); =20 static struct platform_driver clk_mt8516_drv =3D { .probe =3D mtk_clk_simple_probe, --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99432C05027 for ; Mon, 20 Feb 2023 15:04:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232267AbjBTPE5 (ORCPT ); Mon, 20 Feb 2023 10:04:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229579AbjBTPE1 (ORCPT ); Mon, 20 Feb 2023 10:04:27 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6550211CC; Mon, 20 Feb 2023 07:02:46 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 50A346602179; Mon, 20 Feb 2023 15:02:25 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905346; bh=3IwFA06sVGSDEBr1wpsY6ECVPhWTsgVGoA1+gdS6cFQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jlGcZLev9+vMLx41OHqe5asFd5qR9dztpH7awuQhSVuTel2q77CKcj5J5wdznkdto Abf/3hXzNZ3EBcP0AW9dbqTeHuoFKlMK3xgTr6Z1QKN8gIaJ8aoDRy4kNXj7U4lO8b Z357FIsFeQ2lmauktXyjpGfOCA3clOcdPfVZn7bvV6jSpgNjWOyScQiNPFpffs6zbu 8jSyd1EUOiPvFFye6RKLnE3riFdDHzkoiLjzXw4UDv2J8WXlWlLLcET2ory4vDOT7m AeL2ZvmNKnxQJQ8OJl7nSYRSEdNWWXwXbFAWuQ8xn9O3TB79YPrDm0XNhzeCOHy5vX XfGkwi9N1Zy6g== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 50/55] clk: mediatek: mt8135: Move apmixedsys to its own file Date: Mon, 20 Feb 2023 16:01:06 +0100 Message-Id: <20230220150111.77897-51-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for migrating mt8135 clocks to the common simple probe mechanism, move the apmixedsys clocks to a different file. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Makefile | 2 +- drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 62 ++++++++++++++++++++ drivers/clk/mediatek/clk-mt8135.c | 46 --------------- 3 files changed, 63 insertions(+), 47 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8135-apmixedsys.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 5facbe93141e..228cb3e3a4c4 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -62,7 +62,7 @@ obj-$(CONFIG_COMMON_CLK_MT7986) +=3D clk-mt7986-apmixed.o obj-$(CONFIG_COMMON_CLK_MT7986) +=3D clk-mt7986-topckgen.o obj-$(CONFIG_COMMON_CLK_MT7986) +=3D clk-mt7986-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) +=3D clk-mt7986-eth.o -obj-$(CONFIG_COMMON_CLK_MT8135) +=3D clk-mt8135.o +obj-$(CONFIG_COMMON_CLK_MT8135) +=3D clk-mt8135-apmixedsys.o clk-mt8135.o obj-$(CONFIG_COMMON_CLK_MT8167) +=3D clk-mt8167.o clk-mt8167-apmixedsys.o obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) +=3D clk-mt8167-aud.o obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) +=3D clk-mt8167-img.o diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8135-apmixedsys.c new file mode 100644 index 000000000000..2b4d379300fc --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * James Liao + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-pll.h" + +#define MT8135_PLL_FMAX (2000 * MHZ) +#define CON0_MT8135_RST_BAR BIT(27) + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_re= g, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D CON0_MT8135_RST_BAR, \ + .fmax =3D MT8135_PLL_FMAX, \ + .pcwbits =3D _pcwbits, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + } + +static const struct mtk_pll_data plls[] =3D { + PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x20= 4, 24, 0x0, 0x204, 0), + PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d= 0, 24, 0x0, 0x2d0, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BA= R, 21, 0x21c, 6, 0x0, 0x220, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BA= R, 7, 0x238, 6, 0x0, 0x238, 9), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 2= 1, 0x254, 6, 0x0, 0x258, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x27= 8, 6, 0x0, 0x27c, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294,= 6, 0x0, 0x298, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b= 0, 6, 0x0, 0x2b4, 0), + PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8,= 6, 0x2f8, 0x2ec, 0), + PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b= 0, 6, 0x0, 0x308, 0), +}; + +static void __init mtk_apmixedsys_init(struct device_node *node) +{ + struct clk_hw_onecell_data *clk_data; + + clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return; + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); +} +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", + mtk_apmixedsys_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 98165b1f7c97..2a9405b552c6 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -592,50 +592,4 @@ static void __init mtk_pericfg_init(struct device_node= *node) mtk_register_reset_controller(node, &clk_rst_desc[1]); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); - -#define MT8135_PLL_FMAX (2000 * MHZ) -#define CON0_MT8135_RST_BAR BIT(27) - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_re= g, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D CON0_MT8135_RST_BAR, \ - .fmax =3D MT8135_PLL_FMAX, \ - .pcwbits =3D _pcwbits, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - } - -static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x20= 4, 24, 0x0, 0x204, 0), - PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d= 0, 24, 0x0, 0x2d0, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BA= R, 21, 0x21c, 6, 0x0, 0x220, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BA= R, 7, 0x238, 6, 0x0, 0x238, 9), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 2= 1, 0x254, 6, 0x0, 0x258, 0), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x27= 8, 6, 0x0, 0x27c, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294,= 6, 0x0, 0x298, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b= 0, 6, 0x0, 0x2b4, 0), - PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8,= 6, 0x2f8, 0x2ec, 0), - PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b= 0, 6, 0x0, 0x308, 0), -}; - -static void __init mtk_apmixedsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -} -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", - mtk_apmixedsys_init); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFAC9C636CC for ; Mon, 20 Feb 2023 15:05:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232924AbjBTPFC (ORCPT ); Mon, 20 Feb 2023 10:05:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232314AbjBTPEh (ORCPT ); Mon, 20 Feb 2023 10:04:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA6364492; Mon, 20 Feb 2023 07:02:49 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B25F966021CC; Mon, 20 Feb 2023 15:02:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905347; bh=qI37eAVXpXgAjG1sJQwIW4vaDPf2H9q2nvTIZKlPjrA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=feWv+GbdqoXRxlb40FKN7ey+pcKIxAunXKLRx9IOt3hGxo7wdTNXr0t5h/HkgDYQD eQReTEmpRpNPA1b3yYYkLa3B1nRVg16Xm+LHk2EgMXlPTc2xtaVA9F1ADA9N7Mpby2 HggVB6+gM2D8GKtBqBUXORFxUCgkytaZsqf1O9BbXe8Ts6DKZgpQBuK8uRwsesvk6D HGCVThfIFx84aCOZqJ+0fDZIutyaBogpxVVX5GUxUKfLPncRM7ENOARytYc9ndT7Bg i8PbOcz7EJnTwGFqsWY3EaBF52LojzUNQMTjMAmTfupxkaRwU9ojYqQh1uPD0FR5Vz Ea8TXgXsrIUpQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 51/55] clk: mediatek: mt8135: Properly use CLK_IS_CRITICAL flag Date: Mon, 20 Feb 2023 16:01:07 +0100 Message-Id: <20230220150111.77897-52-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: a8aede794843 ("clk: mediatek: Add basic clocks for Mediatek MT8135.") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8135.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 2a9405b552c6..1c76c0003f99 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -2,6 +2,8 @@ /* * Copyright (c) 2014 MediaTek Inc. * Author: James Liao + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno */ =20 #include @@ -390,7 +392,7 @@ static const struct mtk_composite top_muxes[] __initcon= st =3D { MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), /* CLK_CFG_9 */ MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), - MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15), + MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15,= CLK_IS_CRITICAL), MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24,= 2, 31), }; @@ -404,6 +406,10 @@ static const struct mtk_gate_regs infra_cg_regs =3D { #define GATE_ICG(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 +#define GATE_ICG_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) + static const struct mtk_gate infra_clks[] __initconst =3D { GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), @@ -411,7 +417,7 @@ static const struct mtk_gate infra_clks[] __initconst = =3D { GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), - GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), + GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), @@ -534,8 +540,6 @@ static void __init mtk_topckgen_init(struct device_node= *node) ARRAY_SIZE(top_muxes), base, &mt8135_clk_lock, clk_data); =20 - clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk); - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", @@ -553,8 +557,6 @@ static void __init mtk_infrasys_init(struct device_node= *node) mtk_clk_register_gates(NULL, node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); =20 - clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk); - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8CA5C64ED9 for ; Mon, 20 Feb 2023 15:06:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232922AbjBTPGK (ORCPT ); Mon, 20 Feb 2023 10:06:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232969AbjBTPFw (ORCPT ); Mon, 20 Feb 2023 10:05:52 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E04C81DB9F; Mon, 20 Feb 2023 07:04:11 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1D52A6602169; Mon, 20 Feb 2023 15:02:28 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905349; bh=M5hdGMuzmKCUIv2g12dDgcyuK136Nce3uLfpDQsboOQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aaVL1z4+bFi5k5Pm92LtPA2oZYmKSVXIi3EpYw3kN79tgEJDKZQpUPOZMXcx/gGFe QrxLcIQqhx+lUCUjuA4FYxZT5+sUJjV76Ydum6eJOXq7xNCXInW04Go9fZDJmIUuxK MI2i4Wg+35RAQ9aDRns6YEC2T1n+JH/xjybUtH78yuDtMWRLf3F3NimAk6/Pg88PX4 2nDq4p0k8jhdpkGZwyRVupxsZZpFaVRHkz4PNLyn76mrOG3o2jqzWihjmY5Lh01KdS cvQFE447RQXMyaf1zDnKPv/Sja6+JIz3YeGWFdBu2H+rFx4tKoJC344SNSMwEshH44 ggLC9Nmgl5VIQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 52/55] clk: mediatek: mt8135-apmixedsys: Convert to platform_driver and module Date: Mon, 20 Feb 2023 16:01:08 +0100 Message-Id: <20230220150111.77897-53-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert apmixedsys clocks to be a platform driver; while at it, also add necessary error handling to the probe function, add a remove callback and provide a MODULE_DESCRIPTION(). This driver is now compatible with an eventual module build. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8135-apmixedsys.c | 53 ++++++++++++++++++-- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8135-apmixedsys.c index 2b4d379300fc..744aae092281 100644 --- a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c @@ -47,16 +47,59 @@ static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b= 0, 6, 0x0, 0x308, 0), }; =20 -static void __init mtk_apmixedsys_init(struct device_node *node) +static int clk_mt8135_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; + struct device_node *node =3D pdev->dev.of_node; + int ret; =20 clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) - return; + return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_plls; + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static int clk_mt8135_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; } -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", - mtk_apmixedsys_init); + +static const struct of_device_id of_match_clk_mt8135_apmixed[] =3D { + { .compatible =3D "mediatek,mt8135-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8135_apmixed); + +static struct platform_driver clk_mt8135_apmixed_drv =3D { + .probe =3D clk_mt8135_apmixed_probe, + .remove =3D clk_mt8135_apmixed_remove, + .driver =3D { + .name =3D "clk-mt8135-apmixed", + .of_match_table =3D of_match_clk_mt8135_apmixed, + }, +}; +module_platform_driver(clk_mt8135_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT8135 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24889C05027 for ; Mon, 20 Feb 2023 15:05:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232991AbjBTPFR (ORCPT ); Mon, 20 Feb 2023 10:05:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232678AbjBTPEl (ORCPT ); Mon, 20 Feb 2023 10:04:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5884E7EC3; Mon, 20 Feb 2023 07:02:55 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 78B23660216A; Mon, 20 Feb 2023 15:02:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905350; bh=xEzNnjlrGCa8nDnkjYmWB7XHA1caeWO11UfF0hFXRg4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nWovtCCRi06sL5fIm5639Dw16mBs8mH8fSte1LynwbJu4Tad7oP/fmdgnf2z6avWX SAGCGk3ty7SU7tjwb/1mYJ7HAwhyVvWLRAFvjFTwxyKrHVxgUpOsLMSjUmr5Wvj4SJ 28eHvUTS/SHrH9MnPRN79btSbmdoLuXmyriVR+Li2ZD3EhAEYAbqEgf6bQyd2pE/Pc IndX9wVzPM8QaG4vkdxoysmsbbNnAbrcvKO7RObtt1f+3hvw2hy8u5pwN+ZtWEEe/8 lkBFyaqjhwlB1SrPX6mPQA3s6M+GtaPJ6kr3H9OE7eWrcpjC4ig/M86PMkFUBq/KcN 89IA7XYACZ4CQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 53/55] clk: mediatek: mt8135: Join root_clk_alias and top_divs arrays Date: Mon, 20 Feb 2023 16:01:09 +0100 Message-Id: <20230220150111.77897-54-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for converting this driver to the common simple probe mechanism, join the root_clk_alias and top_divs mtk_fixed_factor arrays. This commit brings no functional change. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8135.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 1c76c0003f99..8785d58cb3a5 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -2,8 +2,6 @@ /* * Copyright (c) 2014 MediaTek Inc. * Author: James Liao - * Copyright (c) 2023 Collabora, Ltd. - * AngeloGioacchino Del Regno */ =20 #include @@ -19,14 +17,12 @@ =20 static DEFINE_SPINLOCK(mt8135_clk_lock); =20 -static const struct mtk_fixed_factor root_clk_alias[] __initconst =3D { +static const struct mtk_fixed_factor top_divs[] __initconst =3D { FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), -}; =20 -static const struct mtk_fixed_factor top_divs[] __initconst =3D { FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2), FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3), FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5), @@ -534,7 +530,6 @@ static void __init mtk_topckgen_init(struct device_node= *node) =20 clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); =20 - mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_= data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(NULL, top_muxes, ARRAY_SIZE(top_muxes), base, --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE97DC64EC4 for ; Mon, 20 Feb 2023 15:05:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232279AbjBTPFO (ORCPT ); Mon, 20 Feb 2023 10:05:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232869AbjBTPEl (ORCPT ); Mon, 20 Feb 2023 10:04:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F4771D913; Mon, 20 Feb 2023 07:02:55 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D9F2F6602136; Mon, 20 Feb 2023 15:02:30 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905352; bh=h+DBC5isCqQIqQmrUysGMFQN8g+3IzpdI5PPG7viLGE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A2ceCJbfBSKEmQFDH+EWebqM9Cc93iP8qNiN0OkED5GaFGGa5zicJcBmk5rOr4Sth TlijcFbIjwCDa8v23aV3eZwwFU1HWYcHoPacf4v8AWwDecyw3MlwAJdnP0mAKvFmrj SO5pZz8tqTcs4Sn3W0arqz3zcP77Czj3DcFybzy1gyjxIcXJYdKfB0X1/863VC+L+p LWrXjRJ+MfVn7d+tLjpzCmW2aIoAhSn0y7hcAaqNi4uwJtVoGZnLeTC/SbT/b9Er5C F0IPJrEdpP1x4LXObTojyNundP0m/fugvq97mxTyw8tZYWBl7CC+kwMgxSGrGSnFyM JGpSg3Am/BxUw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 54/55] clk: mediatek: mt8135: Convert to simple probe and enable module build Date: Mon, 20 Feb 2023 16:01:10 +0100 Message-Id: <20230220150111.77897-55-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the MT8135 clock drivers to platform_driver using the common simple probe mechanism. Now that all of the MT8135 clock drivers (including apmixedsys) can be compiled as modules, change the COMMON_CLK_MT8135 configuration option to tristate to enable module build. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 2 +- drivers/clk/mediatek/clk-mt8135.c | 110 ++++++++++++------------------ 2 files changed, 43 insertions(+), 69 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 90691261cddb..a15fbdfd3a53 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -423,7 +423,7 @@ config COMMON_CLK_MT7986_ETHSYS required on MediaTek MT7986 SoC. =20 config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" + tristate "Clock driver for MediaTek MT8135" depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 8785d58cb3a5..39fd919900e5 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -5,8 +5,10 @@ */ =20 #include +#include #include #include +#include #include #include #include @@ -18,6 +20,7 @@ static DEFINE_SPINLOCK(mt8135_clk_lock); =20 static const struct mtk_fixed_factor top_divs[] __initconst =3D { + FACTOR(CLK_DUMMY, "top_divs_dummy", "clk_null", 1, 1), FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), @@ -407,6 +410,7 @@ static const struct mtk_gate_regs infra_cg_regs =3D { &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) =20 static const struct mtk_gate infra_clks[] __initconst =3D { + GATE_DUMMY(CLK_DUMMY, "infra_dummy"), GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21), @@ -441,6 +445,7 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 static const struct mtk_gate peri_gates[] __initconst =3D { + GATE_DUMMY(CLK_DUMMY, "peri_dummy"), /* PERI0 */ GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30), @@ -516,77 +521,46 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = =3D { } }; =20 -static void __init mtk_topckgen_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .rst_desc =3D &clk_rst_desc[0], +}; =20 - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(NULL, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8135_clk_lock, clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init= ); - -static void __init mtk_infrasys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(NULL, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller(node, &clk_rst_desc[0]); -} -CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init= ); - -static void __init mtk_pericfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } +static const struct mtk_clk_desc peri_desc =3D { + .clks =3D peri_gates, + .num_clks =3D ARRAY_SIZE(peri_gates), + .composite_clks =3D peri_clks, + .num_composite_clks =3D ARRAY_SIZE(peri_clks), + .clk_lock =3D &mt8135_clk_lock, + .rst_desc =3D &clk_rst_desc[1], +}; =20 - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); +static const struct mtk_clk_desc topck_desc =3D { + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .clk_lock =3D &mt8135_clk_lock, +}; =20 - mtk_clk_register_gates(NULL, node, peri_gates, - ARRAY_SIZE(peri_gates), clk_data); - mtk_clk_register_composites(NULL, peri_clks, - ARRAY_SIZE(peri_clks), base, - &mt8135_clk_lock, clk_data); +static const struct of_device_id of_match_clk_mt8135[] =3D { + { .compatible =3D "mediatek,mt8135-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt8135-pericfg", .data =3D &peri_desc }, + { .compatible =3D "mediatek,mt8135-topckgen", .data =3D &topck_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8135); =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static struct platform_driver clk_mt8135_drv =3D { + .driver =3D { + .name =3D "clk-mt8135", + .of_match_table =3D of_match_clk_mt8135, + }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt8135_drv); =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); -} -CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); +MODULE_DESCRIPTION("MediaTek MT8135 clocks driver"); MODULE_LICENSE("GPL"); --=20 2.39.1 From nobody Thu Nov 14 07:15:32 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 861E6C05027 for ; Mon, 20 Feb 2023 15:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232678AbjBTPGY (ORCPT ); Mon, 20 Feb 2023 10:06:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231740AbjBTPGB (ORCPT ); Mon, 20 Feb 2023 10:06:01 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D184211F6; Mon, 20 Feb 2023 07:04:26 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 466F366021CF; Mon, 20 Feb 2023 15:02:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905353; bh=x3v3ueWOU/hk/L+2Q5luAzeuPeuM010GE3F0ZFfFFVw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mv9A/Ypm8oMn5cGlIzlxk2pQ3vQl8a5YX3ccuOzMB8J7GMT4vveUHDKNW6nU+ARhD ldBtEX/7H/VngcWNl7JslMrn0eW3RrOwmEXakaYo++Ry7fejlj6yYZ2aT/SBBnYA3b ehKOUTMpt8pmo8kLNO12heQ6Kov4LjWPL9cuV7ZPU749vlf20EEd+9MXlNCtgTDUbt e+29rQ58KauRWFcXtAiIkzyH24En+GXAp0sV+R2xBiuQS5/v4aBqWHgTOB8A7g6wZI aRqTQxumsclX8LpB/T9WHI6gr+MziEcjsFBI91t8xNcr52iQgACypZFOkyRWVOhUqi pHlSh5ITisuOA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 55/55] clk: mediatek: mt8135: Remove __initconst annotation from clock arrays Date: Mon, 20 Feb 2023 16:01:11 +0100 Message-Id: <20230220150111.77897-56-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Being this a platform driver, these arrays are not only used during init anymore, but also during runtime: remove the __initconst annotation from all of them. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8135.c | 66 +++++++++++++++---------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 39fd919900e5..084e48a554c2 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -19,7 +19,7 @@ =20 static DEFINE_SPINLOCK(mt8135_clk_lock); =20 -static const struct mtk_fixed_factor top_divs[] __initconst =3D { +static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_DUMMY, "top_divs_dummy", "clk_null", 1, 1), FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), @@ -101,7 +101,7 @@ static const struct mtk_fixed_factor top_divs[] __initc= onst =3D { FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), }; =20 -static const char * const axi_parents[] __initconst =3D { +static const char * const axi_parents[] =3D { "clk26m", "syspll_d3", "syspll_d4", @@ -111,7 +111,7 @@ static const char * const axi_parents[] __initconst =3D= { "syspll_d3p5" }; =20 -static const char * const smi_parents[] __initconst =3D { +static const char * const smi_parents[] =3D { "clk26m", "clkph_mck", "syspll_d2p5", @@ -129,7 +129,7 @@ static const char * const smi_parents[] __initconst =3D= { "lvdspll" }; =20 -static const char * const mfg_parents[] __initconst =3D { +static const char * const mfg_parents[] =3D { "clk26m", "univpll1_d4", "syspll_d2", @@ -145,13 +145,13 @@ static const char * const mfg_parents[] __initconst = =3D { "mmpll_d7" }; =20 -static const char * const irda_parents[] __initconst =3D { +static const char * const irda_parents[] =3D { "clk26m", "univpll2_d8", "univpll1_d6" }; =20 -static const char * const cam_parents[] __initconst =3D { +static const char * const cam_parents[] =3D { "clk26m", "syspll_d3", "syspll_d3p5", @@ -162,13 +162,13 @@ static const char * const cam_parents[] __initconst = =3D { "univpll1_d4" }; =20 -static const char * const aud_intbus_parents[] __initconst =3D { +static const char * const aud_intbus_parents[] =3D { "clk26m", "syspll_d6", "univpll_d10" }; =20 -static const char * const jpg_parents[] __initconst =3D { +static const char * const jpg_parents[] =3D { "clk26m", "syspll_d5", "syspll_d4", @@ -178,7 +178,7 @@ static const char * const jpg_parents[] __initconst =3D= { "univpll_d5" }; =20 -static const char * const disp_parents[] __initconst =3D { +static const char * const disp_parents[] =3D { "clk26m", "syspll_d3p5", "syspll_d3", @@ -189,7 +189,7 @@ static const char * const disp_parents[] __initconst = =3D { "vdecpll" }; =20 -static const char * const msdc30_parents[] __initconst =3D { +static const char * const msdc30_parents[] =3D { "clk26m", "syspll_d6", "syspll_d5", @@ -198,13 +198,13 @@ static const char * const msdc30_parents[] __initcons= t =3D { "msdcpll" }; =20 -static const char * const usb20_parents[] __initconst =3D { +static const char * const usb20_parents[] =3D { "clk26m", "univpll2_d6", "univpll1_d10" }; =20 -static const char * const venc_parents[] __initconst =3D { +static const char * const venc_parents[] =3D { "clk26m", "syspll_d3", "syspll_d8", @@ -215,7 +215,7 @@ static const char * const venc_parents[] __initconst = =3D { "mmpll_d6" }; =20 -static const char * const spi_parents[] __initconst =3D { +static const char * const spi_parents[] =3D { "clk26m", "syspll_d6", "syspll_d8", @@ -224,17 +224,17 @@ static const char * const spi_parents[] __initconst = =3D { "univpll1_d8" }; =20 -static const char * const uart_parents[] __initconst =3D { +static const char * const uart_parents[] =3D { "clk26m", "univpll2_d8" }; =20 -static const char * const mem_parents[] __initconst =3D { +static const char * const mem_parents[] =3D { "clk26m", "clkph_mck" }; =20 -static const char * const camtg_parents[] __initconst =3D { +static const char * const camtg_parents[] =3D { "clk26m", "univpll_d26", "univpll1_d6", @@ -242,12 +242,12 @@ static const char * const camtg_parents[] __initconst= =3D { "syspll_d8" }; =20 -static const char * const audio_parents[] __initconst =3D { +static const char * const audio_parents[] =3D { "clk26m", "syspll_d24" }; =20 -static const char * const fix_parents[] __initconst =3D { +static const char * const fix_parents[] =3D { "rtc32k", "clk26m", "univpll_d5", @@ -258,7 +258,7 @@ static const char * const fix_parents[] __initconst =3D= { "univpll1_d8" }; =20 -static const char * const vdec_parents[] __initconst =3D { +static const char * const vdec_parents[] =3D { "clk26m", "vdecpll", "clkph_mck", @@ -277,13 +277,13 @@ static const char * const vdec_parents[] __initconst = =3D { "lvdspll" }; =20 -static const char * const ddrphycfg_parents[] __initconst =3D { +static const char * const ddrphycfg_parents[] =3D { "clk26m", "axi_sel", "syspll_d12" }; =20 -static const char * const dpilvds_parents[] __initconst =3D { +static const char * const dpilvds_parents[] =3D { "clk26m", "lvdspll", "lvdspll_d2", @@ -291,7 +291,7 @@ static const char * const dpilvds_parents[] __initconst= =3D { "lvdspll_d8" }; =20 -static const char * const pmicspi_parents[] __initconst =3D { +static const char * const pmicspi_parents[] =3D { "clk26m", "univpll2_d6", "syspll_d8", @@ -302,14 +302,14 @@ static const char * const pmicspi_parents[] __initcon= st =3D { "syspll_d24" }; =20 -static const char * const smi_mfg_as_parents[] __initconst =3D { +static const char * const smi_mfg_as_parents[] =3D { "clk26m", "smi_sel", "mfg_sel", "mem_sel" }; =20 -static const char * const gcpu_parents[] __initconst =3D { +static const char * const gcpu_parents[] =3D { "clk26m", "syspll_d4", "univpll_d7", @@ -317,14 +317,14 @@ static const char * const gcpu_parents[] __initconst = =3D { "syspll_d6" }; =20 -static const char * const dpi1_parents[] __initconst =3D { +static const char * const dpi1_parents[] =3D { "clk26m", "tvhdmi_h_ck", "tvhdmi_d2", "tvhdmi_d4" }; =20 -static const char * const cci_parents[] __initconst =3D { +static const char * const cci_parents[] =3D { "clk26m", "mainpll_537p3m", "univpll_d3", @@ -333,7 +333,7 @@ static const char * const cci_parents[] __initconst =3D= { "syspll_d5" }; =20 -static const char * const apll_parents[] __initconst =3D { +static const char * const apll_parents[] =3D { "clk26m", "apll_ck", "apll_d4", @@ -342,14 +342,14 @@ static const char * const apll_parents[] __initconst = =3D { "apll_d24" }; =20 -static const char * const hdmipll_parents[] __initconst =3D { +static const char * const hdmipll_parents[] =3D { "clk26m", "hdmitx_clkdig_cts", "hdmitx_clkdig_d2", "hdmitx_clkdig_d3" }; =20 -static const struct mtk_composite top_muxes[] __initconst =3D { +static const struct mtk_composite top_muxes[] =3D { /* CLK_CFG_0 */ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0140, 0, 3, INVALID_MUX_GATE_BIT), @@ -409,7 +409,7 @@ static const struct mtk_gate_regs infra_cg_regs =3D { GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \ &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) =20 -static const struct mtk_gate infra_clks[] __initconst =3D { +static const struct mtk_gate infra_clks[] =3D { GATE_DUMMY(CLK_DUMMY, "infra_dummy"), GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), @@ -444,7 +444,7 @@ static const struct mtk_gate_regs peri1_cg_regs =3D { #define GATE_PERI1(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_s= etclr) =20 -static const struct mtk_gate peri_gates[] __initconst =3D { +static const struct mtk_gate peri_gates[] =3D { GATE_DUMMY(CLK_DUMMY, "peri_dummy"), /* PERI0 */ GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), @@ -491,12 +491,12 @@ static const struct mtk_gate peri_gates[] __initconst= =3D { GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0), }; =20 -static const char * const uart_ck_sel_parents[] __initconst =3D { +static const char * const uart_ck_sel_parents[] =3D { "clk26m", "uart_sel", }; =20 -static const struct mtk_composite peri_clks[] __initconst =3D { +static const struct mtk_composite peri_clks[] =3D { MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), --=20 2.39.1