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[94.197.187.145]) by smtp.gmail.com with ESMTPSA id d21-20020a05600c34d500b003daffc2ecdesm6794420wmq.13.2023.02.16.14.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 14:22:41 -0800 (PST) From: Aidan MacDonald To: agross@kernel.org, andersson@kernel.org, lee@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/4] mfd: qcom-pm8008: Fix swapped mask/unmask in irq chip Date: Thu, 16 Feb 2023 22:22:11 +0000 Message-Id: <20230216222214.138671-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> References: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The usual behavior of mask registers is writing a '1' bit to disable (mask) an interrupt; similarly, writing a '1' bit to an unmask register enables (unmasks) an interrupt. Due to a longstanding issue in regmap-irq, mask and unmask registers were inverted when both kinds of registers were present on the same chip, ie. regmap-irq actually wrote '1's to the mask register to enable an IRQ and '1's to the unmask register to disable an IRQ. This was fixed by commit e8ffb12e7f06 ("regmap-irq: Fix inverted handling of unmask registers") but the fix is opt-in via mask_unmask_non_inverted =3D true because it requires manual changes for each affected driver. The new behavior will become the default once all drivers have been updated. The PM8008 appears to rely on the inverted behavior. It has separate set & clear registers for a register called INT_EN, which presumably enables interrupts by writing '1's. Opt in to the new non-inverted behavior & swap mask_base/unmask_base. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 9f3c4a01b4c1..39fd2a792e73 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -45,8 +45,8 @@ enum { #define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE =20 #define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET) -#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) -#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) +#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) +#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) #define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET) #define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET) #define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSE= T) @@ -131,6 +131,7 @@ static struct regmap_irq_chip pm8008_irq_chip =3D { .status_base =3D PM8008_STATUS_BASE, .mask_base =3D PM8008_MASK_BASE, .unmask_base =3D PM8008_UNMASK_BASE, + .mask_unmask_non_inverted =3D true, .type_base =3D PM8008_TYPE_BASE, .ack_base =3D PM8008_ACK_BASE, .virt_reg_base =3D pm8008_virt_regs, --=20 2.39.2 From nobody Thu Sep 11 18:24:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0126C61DA4 for ; Thu, 16 Feb 2023 22:22:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230319AbjBPWWs (ORCPT ); Thu, 16 Feb 2023 17:22:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230310AbjBPWWq (ORCPT ); Thu, 16 Feb 2023 17:22:46 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B7264D609; Thu, 16 Feb 2023 14:22:44 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id r2so3254229wrv.7; Thu, 16 Feb 2023 14:22:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GB5CWEtRRQ/o56HacmvmZRAx5GJevROntZ+kKSL5iO8=; b=qqpYGGbA3EK1W5Gn54tb5U1zMHyUnfj31FQuJHudxn4854XyLZriOeJ1t97uCJHcP+ L8xpEUipLf4aBaZVgV23BKnZbRab0PQpwBFfAoQun0I08i27RUDWgT2oOBj9FE6kuOl3 F6pJA/FeI3vorwgxysyKO57pgmDIrauAORmoF6dToTufJK2RCTZPYOr+iXlzT6QIVrP8 JZ/H4YLrAqSldVW0Ohf/F6CrcZ9xPzMltAszQdAJStD7Xw71/RzXAPXaxf2kZQnEPK4e aEs7EloXSLlQnESijedLzjrpiiUxLHs1UOJEGwCd98zaaAm00FdTzSzeW7hhIukifYtK 6GaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GB5CWEtRRQ/o56HacmvmZRAx5GJevROntZ+kKSL5iO8=; b=gqD7vbmMD6QABouhdqiGzcHLdBFGqbfYhq8jYYaT1x2friU2R9t6D0u4EfwTBIr9Vz 68iVVtEZO8uIeYB9zloExk4XA5/bmLX1xFKsOTswKunugPvGNHY7jDJTYjiZCkfp5KSM 6zQKBDW41N1VgzIVlfvRyuRIbxxCXBxZRdjXrRfzp0IkTNgXZNUiYjlvql8AF8rrIqJ5 lnCVGcbGnfUpzyRWxZKMVbUZX3sE2iEDe5vq9CiUko6BIYoMYaAmh3vr8Kng/KeNQz5F yNqLO5EkWWdY07kYY2X3nsAKDhuhpI4Ni1xh5r4Pl9WUtvw4yfErsU8tZ6RJv1e/BidO SR5Q== X-Gm-Message-State: AO0yUKX6zButRkT2LkIAMsmM8+5PWbhmjRHhT0gpzzcycYKL7QPgCrs/ 5fO8Uj4XMSZ0koBa9DJUSy0= X-Google-Smtp-Source: AK7set+7cVcdAirTc/5V4kqJRyZ7voG6Az/Vfp2AlmRKd++HwB6Y88P3QPkCxy51b3BLsEi58oqmdA== X-Received: by 2002:a5d:574a:0:b0:2c5:582b:bad1 with SMTP id q10-20020a5d574a000000b002c5582bbad1mr6336974wrw.30.1676586163058; Thu, 16 Feb 2023 14:22:43 -0800 (PST) Received: from localhost (94.197.187.145.threembb.co.uk. [94.197.187.145]) by smtp.gmail.com with ESMTPSA id g9-20020adff3c9000000b002c54d8b89efsm2696211wrp.26.2023.02.16.14.22.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 14:22:42 -0800 (PST) From: Aidan MacDonald To: agross@kernel.org, andersson@kernel.org, lee@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/4] mfd: qcom-pm8008: Convert irq chip to config regs Date: Thu, 16 Feb 2023 22:22:12 +0000 Message-Id: <20230216222214.138671-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> References: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace type and virtual registers, which are both deprecated, with config registers. This also simplifies the driver because IRQ types are set in one place, the set_type_config() callback. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 50 +++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 39fd2a792e73..2b6763605cd7 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -66,15 +66,16 @@ static struct regmap_irq_sub_irq_map pm8008_sub_reg_off= sets[] =3D { REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs), }; =20 -static unsigned int pm8008_virt_regs[] =3D { - PM8008_POLARITY_HI_BASE, - PM8008_POLARITY_LO_BASE, -}; - enum { + SET_TYPE_INDEX, POLARITY_HI_INDEX, POLARITY_LO_INDEX, - PM8008_NUM_VIRT_REGS, +}; + +static unsigned int pm8008_config_regs[] =3D { + PM8008_TYPE_BASE, + PM8008_POLARITY_HI_BASE, + PM8008_POLARITY_LO_BASE, }; =20 static struct regmap_irq pm8008_irqs[] =3D { @@ -88,32 +89,36 @@ static struct regmap_irq pm8008_irqs[] =3D { REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)), }; =20 -static int pm8008_set_type_virt(unsigned int **virt_buf, - unsigned int type, unsigned long hwirq, - int reg) +static int pm8008_set_type_config(unsigned int **buf, unsigned int type, + const struct regmap_irq *irq_data, int idx) { switch (type) { case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: - virt_buf[POLARITY_HI_INDEX][reg] &=3D ~pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] |=3D pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] &=3D ~irq_data->mask; + buf[POLARITY_LO_INDEX][idx] |=3D irq_data->mask; break; =20 case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: - virt_buf[POLARITY_HI_INDEX][reg] |=3D pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] &=3D ~pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] |=3D irq_data->mask; + buf[POLARITY_LO_INDEX][idx] &=3D ~irq_data->mask; break; =20 case IRQ_TYPE_EDGE_BOTH: - virt_buf[POLARITY_HI_INDEX][reg] |=3D pm8008_irqs[hwirq].mask; - virt_buf[POLARITY_LO_INDEX][reg] |=3D pm8008_irqs[hwirq].mask; + buf[POLARITY_HI_INDEX][idx] |=3D irq_data->mask; + buf[POLARITY_LO_INDEX][idx] |=3D irq_data->mask; break; =20 default: return -EINVAL; } =20 + if (type & IRQ_TYPE_EDGE_BOTH) + buf[SET_TYPE_INDEX][idx] |=3D irq_data->mask; + else + buf[SET_TYPE_INDEX][idx] &=3D ~irq_data->mask; + return 0; } =20 @@ -121,21 +126,20 @@ static struct regmap_irq_chip pm8008_irq_chip =3D { .name =3D "pm8008_irq", .main_status =3D I2C_INTR_STATUS_BASE, .num_main_regs =3D 1, - .num_virt_regs =3D PM8008_NUM_VIRT_REGS, .irqs =3D pm8008_irqs, .num_irqs =3D ARRAY_SIZE(pm8008_irqs), .num_regs =3D PM8008_NUM_PERIPHS, .not_fixed_stride =3D true, .sub_reg_offsets =3D pm8008_sub_reg_offsets, - .set_type_virt =3D pm8008_set_type_virt, .status_base =3D PM8008_STATUS_BASE, .mask_base =3D PM8008_MASK_BASE, .unmask_base =3D PM8008_UNMASK_BASE, .mask_unmask_non_inverted =3D true, - .type_base =3D PM8008_TYPE_BASE, .ack_base =3D PM8008_ACK_BASE, - .virt_reg_base =3D pm8008_virt_regs, - .num_type_reg =3D PM8008_NUM_PERIPHS, + .config_base =3D pm8008_config_regs, + .num_config_bases =3D ARRAY_SIZE(pm8008_config_regs), + .num_config_regs =3D PM8008_NUM_PERIPHS, + .set_type_config =3D pm8008_set_type_config, }; =20 static struct regmap_config qcom_mfd_regmap_cfg =3D { @@ -185,11 +189,7 @@ static int pm8008_probe_irq_peripherals(struct device = *dev, for (i =3D 0; i < ARRAY_SIZE(pm8008_irqs); i++) { type =3D &pm8008_irqs[i].type; =20 - type->type_reg_offset =3D pm8008_irqs[i].reg_offset; - type->type_rising_val =3D pm8008_irqs[i].mask; - type->type_falling_val =3D pm8008_irqs[i].mask; - type->type_level_high_val =3D 0; - type->type_level_low_val =3D 0; + type->type_reg_offset =3D pm8008_irqs[i].reg_offset; =20 if (type->type_reg_offset =3D=3D PM8008_MISC) type->types_supported =3D IRQ_TYPE_EDGE_RISING; --=20 2.39.2 From nobody Thu Sep 11 18:24:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E29E0C636D7 for ; Thu, 16 Feb 2023 22:22:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230334AbjBPWWu (ORCPT ); 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[94.197.187.145]) by smtp.gmail.com with ESMTPSA id t15-20020a1c770f000000b003dc3f195abesm2894346wmi.39.2023.02.16.14.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 14:22:44 -0800 (PST) From: Aidan MacDonald To: agross@kernel.org, andersson@kernel.org, lee@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/4] mfd: qcom-pm8008: Use .get_irq_reg() for irq chip Date: Thu, 16 Feb 2023 22:22:13 +0000 Message-Id: <20230216222214.138671-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> References: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Replace the deprecated not_fixed_stride flag and the associated hierarchy of offsets with a .get_irq_reg() callback. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 56 +++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 31 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 2b6763605cd7..4bcdf0e50c40 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -44,28 +44,6 @@ enum { #define PM8008_GPIO1_ADDR PM8008_PERIPH_2_BASE #define PM8008_GPIO2_ADDR PM8008_PERIPH_3_BASE =20 -#define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET) -#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET) -#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET) -#define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET) -#define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET) -#define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSE= T) -#define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET) - -#define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE) - -static unsigned int p0_offs[] =3D {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BA= SE)}; -static unsigned int p1_offs[] =3D {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BA= SE)}; -static unsigned int p2_offs[] =3D {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BA= SE)}; -static unsigned int p3_offs[] =3D {PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BA= SE)}; - -static struct regmap_irq_sub_irq_map pm8008_sub_reg_offsets[] =3D { - REGMAP_IRQ_MAIN_REG_OFFSET(p0_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p1_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p2_offs), - REGMAP_IRQ_MAIN_REG_OFFSET(p3_offs), -}; - enum { SET_TYPE_INDEX, POLARITY_HI_INDEX, @@ -73,9 +51,9 @@ enum { }; =20 static unsigned int pm8008_config_regs[] =3D { - PM8008_TYPE_BASE, - PM8008_POLARITY_HI_BASE, - PM8008_POLARITY_LO_BASE, + INT_SET_TYPE_OFFSET, + INT_POL_HIGH_OFFSET, + INT_POL_LOW_OFFSET, }; =20 static struct regmap_irq pm8008_irqs[] =3D { @@ -89,6 +67,23 @@ static struct regmap_irq pm8008_irqs[] =3D { REGMAP_IRQ_REG(PM8008_IRQ_GPIO2, PM8008_GPIO2, BIT(0)), }; =20 +static const unsigned int pm8008_periph_base[] =3D { + PM8008_PERIPH_0_BASE, + PM8008_PERIPH_1_BASE, + PM8008_PERIPH_2_BASE, + PM8008_PERIPH_3_BASE, +}; + +static unsigned int pm8008_get_irq_reg(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + /* Simple linear addressing for the main status register */ + if (base =3D=3D I2C_INTR_STATUS_BASE) + return base + index; + + return pm8008_periph_base[index] + base; +} + static int pm8008_set_type_config(unsigned int **buf, unsigned int type, const struct regmap_irq *irq_data, int idx) { @@ -129,17 +124,16 @@ static struct regmap_irq_chip pm8008_irq_chip =3D { .irqs =3D pm8008_irqs, .num_irqs =3D ARRAY_SIZE(pm8008_irqs), .num_regs =3D PM8008_NUM_PERIPHS, - .not_fixed_stride =3D true, - .sub_reg_offsets =3D pm8008_sub_reg_offsets, - .status_base =3D PM8008_STATUS_BASE, - .mask_base =3D PM8008_MASK_BASE, - .unmask_base =3D PM8008_UNMASK_BASE, + .status_base =3D INT_LATCHED_STS_OFFSET, + .mask_base =3D INT_EN_CLR_OFFSET, + .unmask_base =3D INT_EN_SET_OFFSET, .mask_unmask_non_inverted =3D true, - .ack_base =3D PM8008_ACK_BASE, + .ack_base =3D INT_LATCHED_CLR_OFFSET, .config_base =3D pm8008_config_regs, .num_config_bases =3D ARRAY_SIZE(pm8008_config_regs), .num_config_regs =3D PM8008_NUM_PERIPHS, .set_type_config =3D pm8008_set_type_config, + .get_irq_reg =3D pm8008_get_irq_reg, }; =20 static struct regmap_config qcom_mfd_regmap_cfg =3D { --=20 2.39.2 From nobody Thu Sep 11 18:24:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5B0FC64EC4 for ; Thu, 16 Feb 2023 22:22:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230351AbjBPWWw (ORCPT ); Thu, 16 Feb 2023 17:22:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230308AbjBPWWs (ORCPT ); Thu, 16 Feb 2023 17:22:48 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E6D24C3F4; Thu, 16 Feb 2023 14:22:47 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id r25so205362wrr.5; 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[94.197.187.145]) by smtp.gmail.com with ESMTPSA id q9-20020a1ce909000000b003e00c453447sm5935410wmc.48.2023.02.16.14.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 14:22:45 -0800 (PST) From: Aidan MacDonald To: agross@kernel.org, andersson@kernel.org, lee@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/4] mfd: qcom-pm8008: Remove workaround for a regmap-irq quirk Date: Thu, 16 Feb 2023 22:22:14 +0000 Message-Id: <20230216222214.138671-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> References: <20230216222214.138671-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove pm8008_init(), which according to the comments exists only as a workaround for regmap-irq's odd treatment of type registers. This workaround shouldn't be needed anymore because this driver uses config registers, which are always programmed by regmap-irq no matter what the initial register state is. Signed-off-by: Aidan MacDonald --- drivers/mfd/qcom-pm8008.c | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 4bcdf0e50c40..a33fbc42ac8e 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -142,30 +142,6 @@ static struct regmap_config qcom_mfd_regmap_cfg =3D { .max_register =3D 0xFFFF, }; =20 -static int pm8008_init(struct regmap *regmap) -{ - int rc; - - /* - * Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework - * reads this as the default value instead of zero, the HW default. - * This is required to enable the writing of TYPE registers in - * regmap_irq_sync_unlock(). - */ - rc =3D regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET= ), BIT(0)); - if (rc) - return rc; - - /* Do the same for GPIO1 and GPIO2 peripherals */ - rc =3D regmap_write(regmap, (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BI= T(0)); - if (rc) - return rc; - - rc =3D regmap_write(regmap, (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BI= T(0)); - - return rc; -} - static int pm8008_probe_irq_peripherals(struct device *dev, struct regmap *regmap, int client_irq) @@ -174,12 +150,6 @@ static int pm8008_probe_irq_peripherals(struct device = *dev, struct regmap_irq_type *type; struct regmap_irq_chip_data *irq_data; =20 - rc =3D pm8008_init(regmap); - if (rc) { - dev_err(dev, "Init failed: %d\n", rc); - return rc; - } - for (i =3D 0; i < ARRAY_SIZE(pm8008_irqs); i++) { type =3D &pm8008_irqs[i].type; =20 --=20 2.39.2