From nobody Thu Sep 11 19:21:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C524C61DA4 for ; Thu, 16 Feb 2023 13:16:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229977AbjBPNQr (ORCPT ); Thu, 16 Feb 2023 08:16:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229771AbjBPNQp (ORCPT ); Thu, 16 Feb 2023 08:16:45 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72BACE3AF for ; Thu, 16 Feb 2023 05:16:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676553404; x=1708089404; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sEeJE3lb+SBSL58VtACxqpXosFpusquhp6qgy5s/iGw=; b=T1XUAA3MWPFDgdtiknMKjYTjsN67QMu1fm75Ss7Fo18F1unez2T5iiYf 0Dwfu8Ql44DkonqeguWvUqWnsqh64swH4Lbqoj+6EK9oGdn4i/jSO7c0q qLlW4bW1Th5zV1dVi8IWmE4PtCur+a6E9QYbYBVj9WAXcGqJeb1u3XO9M TlFLt0o7weXbZ6Zz3GazEVRNySsxhnda+pXmkJ+LQwE4uKD2BUq0CeiXW JGrvwesUcJOPsrdY6fcFSsYBXZa2WjF2fMjP/bqwGV90HiyEdxMtM3XKV v9h96zAuXhT4AhhmHqxwFKkz5uZ5MWV+4ECLcrY2RZ3H5XnjxNb+tV/gG A==; X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="333883295" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="333883295" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 05:16:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="647674924" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="647674924" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga006.jf.intel.com with ESMTP; 16 Feb 2023 05:16:42 -0800 From: Lu Baolu To: Joerg Roedel Cc: Jacob Pan , Tina Zhang , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] iommu/vt-d: Fix error handling in sva enable/disable paths Date: Thu, 16 Feb 2023 21:08:13 +0800 Message-Id: <20230216130816.151824-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216130816.151824-1-baolu.lu@linux.intel.com> References: <20230216130816.151824-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Roll back all previous actions in error paths of intel_iommu_enable_sva() and intel_iommu_disable_sva(). Fixes: d5b9e4bfe0d8 ("iommu/vt-d: Report prq to io-pgfault framework") Reviewed-by: Kevin Tian Signed-off-by: Lu Baolu Link: https://lore.kernel.org/r/20230208051559.700109-1-baolu.lu@linux.inte= l.com --- drivers/iommu/intel/iommu.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 59df7e42fd53..994dffa1db57 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4642,8 +4642,12 @@ static int intel_iommu_enable_sva(struct device *dev) return -EINVAL; =20 ret =3D iopf_queue_add_device(iommu->iopf_queue, dev); - if (!ret) - ret =3D iommu_register_device_fault_handler(dev, iommu_queue_iopf, dev); + if (ret) + return ret; + + ret =3D iommu_register_device_fault_handler(dev, iommu_queue_iopf, dev); + if (ret) + iopf_queue_remove_device(iommu->iopf_queue, dev); =20 return ret; } @@ -4655,8 +4659,12 @@ static int intel_iommu_disable_sva(struct device *de= v) int ret; =20 ret =3D iommu_unregister_device_fault_handler(dev); - if (!ret) - ret =3D iopf_queue_remove_device(iommu->iopf_queue, dev); + if (ret) + return ret; + + ret =3D iopf_queue_remove_device(iommu->iopf_queue, dev); + if (ret) + iommu_register_device_fault_handler(dev, iommu_queue_iopf, dev); =20 return ret; } --=20 2.34.1 From nobody Thu Sep 11 19:21:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4056CC636CC for ; Thu, 16 Feb 2023 13:16:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230073AbjBPNQx (ORCPT ); Thu, 16 Feb 2023 08:16:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230010AbjBPNQr (ORCPT ); Thu, 16 Feb 2023 08:16:47 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C8A95354B for ; Thu, 16 Feb 2023 05:16:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676553406; x=1708089406; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q4t6DQ3FZM/W5yMNCkd2+Emh3Kq12Ff5P8dXSp0yfmQ=; b=Uxt5voOevKGx+j1MWKBGB+Vzk76dMJK2ZC3cYiZhfuSGt9hxnHEGWs0h fdhd80CKsb8n/gsRqBg+S0agLCfELy5QETMKCh2woGMQbbBz+SIOe+kv3 oNCBBIClo17qFSVmL43KlqZSK1vu9lluETe7GYGE0r51YSIq52oOSspCP YR1oOGeTWyOF6mZq/n+wRP6Gv/+rCNeaqNHZ1jaj5NR2kCkp4MkvyDRDT WlsJEHTvgdxNS1bwzcJi1DacIx0+yeZ/qHH2efBoL/84KftHFgycDV16U 9Miaj6PefBNnyxL/BOBQqb2pUjfjWLVV07uzIyPfC+z1cbk4iQ9lY88Ps Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="333883307" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="333883307" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 05:16:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="647674936" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="647674936" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga006.jf.intel.com with ESMTP; 16 Feb 2023 05:16:44 -0800 From: Lu Baolu To: Joerg Roedel Cc: Jacob Pan , Tina Zhang , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] iommu/vt-d: Avoid superfluous IOTLB tracking in lazy mode Date: Thu, 16 Feb 2023 21:08:14 +0800 Message-Id: <20230216130816.151824-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216130816.151824-1-baolu.lu@linux.intel.com> References: <20230216130816.151824-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jacob Pan Intel IOMMU driver implements IOTLB flush queue with domain selective or PASID selective invalidations. In this case there's no need to track IOVA page range and sync IOTLBs, which may cause significant performance hit. This patch adds a check to avoid IOVA gather page and IOTLB sync for the lazy path. The performance difference on Sapphire Rapids 100Gb NIC is improved by the following (as measured by iperf send): w/o this fix~48 Gbits/s. with this fix ~54 Gbits/s Cc: Fixes: 2a2b8eaa5b25 ("iommu: Handle freelists when using deferred flushing = in iommu drivers") Reviewed-by: Robin Murphy Reviewed-by: Kevin Tian Tested-by: Sanjay Kumar Signed-off-by: Sanjay Kumar Signed-off-by: Jacob Pan Link: https://lore.kernel.org/r/20230209175330.1783556-1-jacob.jun.pan@linu= x.intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 994dffa1db57..ce36a16efc97 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4346,7 +4346,12 @@ static size_t intel_iommu_unmap(struct iommu_domain = *domain, if (dmar_domain->max_addr =3D=3D iova + size) dmar_domain->max_addr =3D iova; =20 - iommu_iotlb_gather_add_page(domain, gather, iova, size); + /* + * We do not use page-selective IOTLB invalidation in flush queue, + * so there is no need to track page and sync iotlb. + */ + if (!iommu_iotlb_gather_queued(gather)) + iommu_iotlb_gather_add_page(domain, gather, iova, size); =20 return size; } --=20 2.34.1 From nobody Thu Sep 11 19:21:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DBF6C636CC for ; Thu, 16 Feb 2023 13:16:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230168AbjBPNQz (ORCPT ); Thu, 16 Feb 2023 08:16:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230116AbjBPNQv (ORCPT ); Thu, 16 Feb 2023 08:16:51 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E65D54575 for ; Thu, 16 Feb 2023 05:16:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676553408; x=1708089408; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JjSVq1WVeCrfaYihL0lX05Q/SUamFWX/MkV36WR1wlU=; b=Fw9FVcslDK49cdJS1G4dKSpMVOIHYoYykDAYWWopuDvqQzXJsDlZFCxt aVKIgiy2lZDTp+/SWUxqorwj19B+h0EG9lxTwKKCshNXKN0aPuPNlrE18 In+LmYLgb/OiaAOYWBHrgqXWz+IrjhIIqsXd6qtaSmwS+DZhPmjk+hMJ0 6cWIbhikVsR3fmeZOV2KplH1gZHBHFqCIItpelMwzLhuRiMhW3ppkSjOk pt2OT6XmxDbG2vyL8qGb8vy7/djjy98Wi3Dlrs+O5kcSruE6MlIGPbm0N R7tbKeTNGyhi5R18NSYbB2CwdL7leKinvOiMN80bUKKlGVmEKxcvfD/2K A==; X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="333883313" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="333883313" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 05:16:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="647674949" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="647674949" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga006.jf.intel.com with ESMTP; 16 Feb 2023 05:16:46 -0800 From: Lu Baolu To: Joerg Roedel Cc: Jacob Pan , Tina Zhang , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] iommu/vt-d: Fix PASID directory pointer coherency Date: Thu, 16 Feb 2023 21:08:15 +0800 Message-Id: <20230216130816.151824-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216130816.151824-1-baolu.lu@linux.intel.com> References: <20230216130816.151824-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jacob Pan On platforms that do not support IOMMU Extended capability bit 0 Page-walk Coherency, CPU caches are not snooped when IOMMU is accessing any translation structures. IOMMU access goes only directly to memory. Intel IOMMU code was missing a flush for the PASID table directory that resulted in the unrecoverable fault as shown below. This patch adds clflush calls whenever allocating and updating a PASID table directory to ensure cache coherency. On the reverse direction, there's no need to clflush the PASID directory pointer when we deactivate a context entry in that IOMMU hardware will not see the old PASID directory pointer after we clear the context entry. PASID directory entries are also never freed once allocated. DMAR: DRHD: handling fault status reg 3 DMAR: [DMA Read NO_PASID] Request device [00:0d.2] fault addr 0x1026a4000 [fault reason 0x51] SM: Present bit in Directory Entry is clear DMAR: Dump dmar1 table entries for IOVA 0x1026a4000 DMAR: scalable mode root entry: hi 0x0000000102448001, low 0x0000000101b3e= 001 DMAR: context entry: hi 0x0000000000000000, low 0x0000000101b4d401 DMAR: pasid dir entry: 0x0000000101b4e001 DMAR: pasid table entry[0]: 0x0000000000000109 DMAR: pasid table entry[1]: 0x0000000000000001 DMAR: pasid table entry[2]: 0x0000000000000000 DMAR: pasid table entry[3]: 0x0000000000000000 DMAR: pasid table entry[4]: 0x0000000000000000 DMAR: pasid table entry[5]: 0x0000000000000000 DMAR: pasid table entry[6]: 0x0000000000000000 DMAR: pasid table entry[7]: 0x0000000000000000 DMAR: PTE not present at level 4 Cc: Fixes: 0bbeb01a4faf ("iommu/vt-d: Manage scalalble mode PASID tables") Reviewed-by: Kevin Tian Reported-by: Sukumar Ghorai Signed-off-by: Ashok Raj Signed-off-by: Jacob Pan Link: https://lore.kernel.org/r/20230209212843.1788125-1-jacob.jun.pan@linu= x.intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/pasid.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index fb3c7020028d..979f796175b1 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -128,6 +128,9 @@ int intel_pasid_alloc_table(struct device *dev) pasid_table->max_pasid =3D 1 << (order + PAGE_SHIFT + 3); info->pasid_table =3D pasid_table; =20 + if (!ecap_coherent(info->iommu->ecap)) + clflush_cache_range(pasid_table->table, size); + return 0; } =20 @@ -215,6 +218,10 @@ static struct pasid_entry *intel_pasid_get_entry(struc= t device *dev, u32 pasid) free_pgtable_page(entries); goto retry; } + if (!ecap_coherent(info->iommu->ecap)) { + clflush_cache_range(entries, VTD_PAGE_SIZE); + clflush_cache_range(&dir[dir_index].val, sizeof(*dir)); + } } =20 return &entries[index]; --=20 2.34.1 From nobody Thu Sep 11 19:21:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4282C61DA4 for ; Thu, 16 Feb 2023 13:17:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbjBPNQ7 (ORCPT ); Thu, 16 Feb 2023 08:16:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbjBPNQz (ORCPT ); Thu, 16 Feb 2023 08:16:55 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87DA9552A5 for ; Thu, 16 Feb 2023 05:16:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676553410; x=1708089410; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NCCqLc87j+n2TX4S0I5r808qPN4XxFBlCpxujEbhTfo=; b=YulFT56SjFb5xcJNjrsTMZ61tm+hAGXJ9iPgi0ZhYio+YWJwEUbuuVGA 9Uo+c907ZmoKXoyiPi5IVCEy/MSjZHcmgWLAHJJTmJtQsp8EK6q7MtUe2 2Y2sm8fQ2H2k1Qb1M3x2ysEisQWaorJ1/yPLfmtoxg9HDb8BdhUg/S6Vd GLh6Y9hlIy2urMQgdF+gUtYT4feIurXh+SKQPxmPWp/uwaOjm+BsVozPP 1LLKHOg5vQ3JdNfvKvw1uPo4OuOspiAjqwyN7d4zrvxwcl88ftTcsxu3W mAxVH1eHcGxjL734ennk1/9UIUwfGHfP/K7DW8+v8XZUSbBEIzb+0TgLI Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="333883331" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="333883331" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2023 05:16:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10623"; a="647674974" X-IronPort-AV: E=Sophos;i="5.97,302,1669104000"; d="scan'208";a="647674974" Received: from allen-box.sh.intel.com ([10.239.159.48]) by orsmga006.jf.intel.com with ESMTP; 16 Feb 2023 05:16:48 -0800 From: Lu Baolu To: Joerg Roedel Cc: Jacob Pan , Tina Zhang , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] iommu/vt-d: Allow to use flush-queue when first level is default Date: Thu, 16 Feb 2023 21:08:16 +0800 Message-Id: <20230216130816.151824-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216130816.151824-1-baolu.lu@linux.intel.com> References: <20230216130816.151824-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tina Zhang Commit 29b32839725f ("iommu/vt-d: Do not use flush-queue when caching-mode is on") forced default domains to be strict mode as long as IOMMU caching-mode is flagged. The reason for doing this is that when vIOMMU uses VT-d caching mode to synchronize shadowing page tables, the strict mode shows better performance. However, this optimization is orthogonal to the first-level page table because the Intel VT-d architecture does not define the caching mode of the first-level page table. Refer to VT-d spec, section 6.1, "When the CM field is reported as Set, any software updates to remapping structures other than first-stage mapping (including updates to not- present entries or present entries whose programming resulted in translation faults) requires explicit invalidation of the caches." Exclude the first-level page table from this optimization. Generally using first-stage translation in vIOMMU implies nested translation enabled in the physical IOMMU. In this case the first-stage page table is wholly captured by the guest. The vIOMMU only needs to transfer the cache invalidations on vIOMMU to the physical IOMMU. Forcing the default domain to strict mode will cause more frequent cache invalidations, resulting in performance degradation. In a real performance benchmark test measured by iperf receive, the performance result on Sapphire Rapids 100Gb NIC shows: w/ this fix ~51 Gbits/s, w/o this fix ~39.3 Gbits/s. Theoretically a first-stage IOMMU page table can still be shadowed in absence of the caching mode, e.g. with host write-protecting guest IOMMU page table to synchronize changed PTEs with the physical IOMMU page table. In this case the shadowing overhead is decoupled from emulating IOTLB invalidation then the overhead of the latter part is solely decided by the frequency of IOTLB invalidations. Hence allowing guest default dma domain to be lazy can also benefit the overall performance by reducing the total VM-exit numbers. Fixes: 29b32839725f ("iommu/vt-d: Do not use flush-queue when caching-mode = is on") Reported-by: Sanjay Kumar Suggested-by: Sanjay Kumar Signed-off-by: Tina Zhang Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20230214025618.2292889-1-tina.zhang@intel.c= om Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index ce36a16efc97..52afcdaf7c7f 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4005,7 +4005,8 @@ int __init intel_iommu_init(void) * is likely to be much lower than the overhead of synchronizing * the virtual and physical IOMMU page-tables. */ - if (cap_caching_mode(iommu->cap)) { + if (cap_caching_mode(iommu->cap) && + !first_level_by_default(IOMMU_DOMAIN_DMA)) { pr_info_once("IOMMU batching disallowed due to virtualization\n"); iommu_set_dma_strict(); } --=20 2.34.1