From nobody Thu Sep 11 21:20:52 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F179C61DA4 for ; Thu, 16 Feb 2023 12:53:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229700AbjBPMxc (ORCPT ); Thu, 16 Feb 2023 07:53:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230460AbjBPMxN (ORCPT ); Thu, 16 Feb 2023 07:53:13 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB91A48E22 for ; Thu, 16 Feb 2023 04:53:09 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id o15so1728421wrc.9 for ; Thu, 16 Feb 2023 04:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zth4LRDzQbzOroJaQCO7UI7/ks7eZuvwOmU1RK0/21g=; b=zAvknU9k6u2pR7ZjnkDBa/R1INvpIk0qOu1+HQwUk+7py9mm1U261lNQm6m6vvjFxJ 63yxVpuk60+ogoQ3Pdel4iWc+Vx6NxFpQo6lBs9U4vrgRDB+dBbQLCtcDwDkhcngf8qw otb6cGMp0SrU2dXE1K8a7JoR3yYwr6sxc/cGYqHRE9SqEDpGa1sxNlVAhS3x3f1UDJCw fdmfgnu9Vx4SlWftXPcPqzBwmi8nYhjLnbssRjeLUAOOEgqrfLEzaQfPEOiEyJAjVXiM vrPqXg7mh4dhrtTsdZIBRUUWOr9QMHixBRh8wdMZgt2df/6kMmttN7bnm9jOiV2VXDF6 Jj5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zth4LRDzQbzOroJaQCO7UI7/ks7eZuvwOmU1RK0/21g=; b=vkr397HBTAJxQ/52QrZ01BhHIf66UJxisNkH38j97gqFNYkBSRbfTyD9KCZQDFuILj CRgitKFJ7pBtGX226gQ6ouxSADnZWZmXDRqdJWTF3XIe+9HMIdBTJ2/D57YiZER1Nv/n FVnpr7nS3nnrSNwAloTcbN/65Ez3kz8mtNVAFtgIXJb4sv8xf39tWaEBMXRu/bwf+YCC oDYNeCs47Jl1ckjOisQPmUxC1H4U3mp8W8c2FXdy2cwX6kTTsdrHSlGSvl0Teijom/Hj RiOluiANUBA5IxqBAjXY18HVzQstt4Wjn6Hv5AWzK3UUUBjH+5TUehbqet60rvfQ9fT9 DY8g== X-Gm-Message-State: AO0yUKWdpHUL5IsYFc82V88ciWQ18+fWzt58138WmHshGyq/rX2/8jaR zaYkGvrIDDMF4BpXuVSNHKCZzA== X-Google-Smtp-Source: AK7set+3ocTCALrHUmoHGw7XzcAcSr/5r/EjM8fRD8BZvx3A+PFAYc7MLMfJfJSGOKaQQqDKBW4XPQ== X-Received: by 2002:adf:dec1:0:b0:2c5:5454:22f5 with SMTP id i1-20020adfdec1000000b002c5545422f5mr4333579wrn.54.1676551988447; Thu, 16 Feb 2023 04:53:08 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:7c5b:1160:db5d:72da]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b002be5bdbe40csm1453292wrs.27.2023.02.16.04.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Feb 2023 04:53:08 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v3 8/9] arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port Date: Thu, 16 Feb 2023 13:52:56 +0100 Message-Id: <20230216125257.112300-9-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230216125257.112300-1-brgl@bgdev.pl> References: <20230216125257.112300-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8775p-ride.dts index d01ca3a9ee37..6f96907b335c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -13,6 +13,7 @@ / { =20 aliases { serial0 =3D &uart10; + serial1 =3D &uart12; i2c18 =3D &i2c18; spi16 =3D &spi16; }; @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state { drive-strength =3D <2>; bias-pull-up; }; + + qup_uart12_cts: qup-uart12-cts-state { + pins =3D "gpio52"; + function =3D "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup-uart12-rts-state { + pins =3D "gpio53"; + function =3D "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup-uart12-tx-state { + pins =3D "gpio54"; + function =3D "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup-uart12-rx-state { + pins =3D "gpio55"; + function =3D "qup1_se5"; + bias-pull-down; + }; }; =20 &uart10 { @@ -75,6 +100,15 @@ &uart10 { status =3D "okay"; }; =20 +&uart12 { + pinctrl-0 =3D <&qup_uart12_cts>, + <&qup_uart12_rts>, + <&qup_uart12_tx>, + <&qup_uart12_rx>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &xo_board_clk { clock-frequency =3D <38400000>; }; --=20 2.37.2