From nobody Thu Nov 14 06:45:57 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 511FDC61DA4 for ; Thu, 16 Feb 2023 05:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229861AbjBPFfP (ORCPT ); Thu, 16 Feb 2023 00:35:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229804AbjBPFfN (ORCPT ); Thu, 16 Feb 2023 00:35:13 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 100EB43934; Wed, 15 Feb 2023 21:35:00 -0800 (PST) X-UUID: 9f1cb0d6adbb11ed945fc101203acc17-20230216 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/Zi22MlhDfgZRKY7KceH6BXJiR9zbMqeP3EwFPtiwp8=; b=cO4SInqT6Nc92ZxerlAOtsPnf6aCysIFVBQrz1I7lOJE1/PhHghijz2QiJdd8GkMecjWnOgagtj03T+VIJ8AqZdCEk8Lfv5FSnJEyj19J0k/jlYt7ncYVMIUw48FP+FvWLLKIeGSVtBcn+n8E0K5UIymX+UBQcVYIh3WEyhGgLU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:21e0ddfb-51a5-4cf1-8fc9-557fd115523b,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.19,REQID:21e0ddfb-51a5-4cf1-8fc9-557fd115523b,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:885ddb2,CLOUDID:c46b29f3-ddba-41c3-91d9-10eeade8eac7,B ulkID:230216133446NQNYVJGD,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 9f1cb0d6adbb11ed945fc101203acc17-20230216 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 461768073; Thu, 16 Feb 2023 13:34:45 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 16 Feb 2023 13:34:44 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 16 Feb 2023 13:34:43 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , Rob Herring , Matthias Brugger CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , , , Subject: [PATCH v7 5/6] iommu/mediatek: Add MT8188 IOMMU Support Date: Thu, 16 Feb 2023 13:33:21 +0800 Message-ID: <20230216053322.11596-6-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230216053322.11596-1-yong.wu@mediatek.com> References: <20230216053322.11596-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Chengci.Xu" MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other is for vpp. and 1 INFRA IOMMU. Signed-off-by: Chengci.Xu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 49 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index afd690da61e3..a3012fdc8f61 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -170,6 +170,7 @@ enum mtk_iommu_plat { M4U_MT8173, M4U_MT8183, M4U_MT8186, + M4U_MT8188, M4U_MT8192, M4U_MT8195, M4U_MT8365, @@ -1582,6 +1583,51 @@ static const struct mtk_iommu_plat_data mt8186_data_= mm =3D { .iova_region_larb_msk =3D mt8186_larb_region_msk, }; =20 +static const struct mtk_iommu_plat_data mt8188_data_infra =3D { + .m4u_plat =3D M4U_MT8188, + .flags =3D WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_A= O | + MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT | + PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, + .iova_region =3D single_domain, + .iova_region_nr =3D ARRAY_SIZE(single_domain), +}; + +static const struct mtk_iommu_plat_data mt8188_data_vdo =3D { + .m4u_plat =3D M4U_MT8188, + .flags =3D HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, + .hw_list =3D &m4ulist, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, + .iova_region =3D mt8192_multi_dom, + .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), + .larbid_remap =3D {{2}, {0}, {21}, {0}, {19}, {9, 10, + 11 /* 11a */, 25 /* 11c */}, + {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}}, +}; + +static const struct mtk_iommu_plat_data mt8188_data_vpp =3D { + .m4u_plat =3D M4U_MT8188, + .flags =3D HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM, + .hw_list =3D &m4ulist, + .inv_sel_reg =3D REG_MMU_INV_SEL_GEN2, + .banks_num =3D 1, + .banks_enable =3D {true}, + .iova_region =3D mt8192_multi_dom, + .iova_region_nr =3D ARRAY_SIZE(mt8192_multi_dom), + .larbid_remap =3D {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID}, + {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID, + 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID, + 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}}, +}; + static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MA= X][MTK_LARB_NR_MAX] =3D { [0] =3D {~0, ~0}, /* Region0: larb0/1 */ [1] =3D {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */ @@ -1690,6 +1736,9 @@ static const struct of_device_id mtk_iommu_of_ids[] = =3D { { .compatible =3D "mediatek,mt8173-m4u", .data =3D &mt8173_data}, { .compatible =3D "mediatek,mt8183-m4u", .data =3D &mt8183_data}, { .compatible =3D "mediatek,mt8186-iommu-mm", .data =3D &mt8186_data_m= m}, /* mm: m4u */ + { .compatible =3D "mediatek,mt8188-iommu-infra", .data =3D &mt8188_data_i= nfra}, + { .compatible =3D "mediatek,mt8188-iommu-vdo", .data =3D &mt8188_data_v= do}, + { .compatible =3D "mediatek,mt8188-iommu-vpp", .data =3D &mt8188_data_v= pp}, { .compatible =3D "mediatek,mt8192-m4u", .data =3D &mt8192_data}, { .compatible =3D "mediatek,mt8195-iommu-infra", .data =3D &mt8195_data_i= nfra}, { .compatible =3D "mediatek,mt8195-iommu-vdo", .data =3D &mt8195_data_v= do}, --=20 2.18.0