From nobody Thu Nov 14 06:39:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99A7EC61DA4 for ; Thu, 16 Feb 2023 05:34:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229854AbjBPFey (ORCPT ); Thu, 16 Feb 2023 00:34:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229804AbjBPFeq (ORCPT ); Thu, 16 Feb 2023 00:34:46 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 368A41F4A7; Wed, 15 Feb 2023 21:34:32 -0800 (PST) X-UUID: 936b07f6adbb11eda06fc9ecc4dadd91-20230216 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dWfIz34xFa8rsTqcM+DuJzOUxjArc0XiYv7GHdeGn1c=; b=S3/pf7GK4BoC7lW4XbMSYOzavVjLZgXZXf9qkvM7HhFA48v3H/FDB7sLujRMITlq0mNBiTEjWEpNIqI8sWDzwQGJDjR8M/xGFqcrSsSFCYOlhlKZdNZRlAkTf73vwjDsf+NviU5VfY5EpsuS9TcUFKwbH0R4oAQAHfAbZqa1ua8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:85967b62-f5f0-47a0-a621-7382ec13e7ef,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:885ddb2,CLOUDID:a7009cb0-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 936b07f6adbb11eda06fc9ecc4dadd91-20230216 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 104247891; Thu, 16 Feb 2023 13:34:26 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 16 Feb 2023 13:34:24 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 16 Feb 2023 13:34:24 +0800 From: Yong Wu To: Joerg Roedel , Will Deacon , Rob Herring , Matthias Brugger CC: Robin Murphy , Krzysztof Kozlowski , Yong Wu , AngeloGioacchino Del Regno , , , , , , , , , , Subject: [PATCH v7 4/6] iommu/mediatek: Add enable IOMMU SMC command for INFRA master Date: Thu, 16 Feb 2023 13:33:20 +0800 Message-ID: <20230216053322.11596-5-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230216053322.11596-1-yong.wu@mediatek.com> References: <20230216053322.11596-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Chengci.Xu" The register which can enable IOMMU for INFRA master should be setted in secure world for security concerns. Therefore, we add a SMC command for INFRA master to enable/disable INFRA IOMMU in ATF. This function is prepared for MT8188. Signed-off-by: Chengci.Xu Reviewed-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 32 ++++++++++++++++++++++---------- include/soc/mediatek/smi.h | 1 + 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7ba05fa58c20..afd690da61e3 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -3,6 +3,7 @@ * Copyright (c) 2015-2016 MediaTek Inc. * Author: Yong Wu */ +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include #include #include =20 @@ -143,6 +145,7 @@ #define PGTABLE_PA_35_EN BIT(17) #define TF_PORT_TO_ADDR_MT8173 BIT(18) #define INT_ID_PORT_WIDTH_6 BIT(19) +#define CFG_IFA_MASTER_IN_ATF BIT(20) =20 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) =3D=3D (_x)) @@ -584,6 +587,7 @@ static int mtk_iommu_config(struct mtk_iommu_data *data= , struct device *dev, struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); const struct mtk_iommu_iova_region *region; unsigned long portid_msk =3D 0; + struct arm_smccc_res res; int i, ret =3D 0; =20 for (i =3D 0; i < fwspec->num_ids; ++i) { @@ -609,17 +613,24 @@ static int mtk_iommu_config(struct mtk_iommu_data *da= ta, struct device *dev, else larb_mmu->mmu &=3D ~portid_msk; } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { - /* PCI dev has only one output id, enable the next writing bit for PCIe = */ - if (dev_is_pci(dev)) { - if (fwspec->num_ids !=3D 1) { - dev_err(dev, "PCI dev can only have one port.\n"); - return -ENODEV; + if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { + arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, + IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, + portid_msk, enable, 0, 0, 0, 0, &res); + ret =3D res.a0; + } else { + /* PCI dev has only one output id, enable the next writing bit for PCIe= */ + if (dev_is_pci(dev)) { + if (fwspec->num_ids !=3D 1) { + dev_err(dev, "PCI dev can only have one port.\n"); + return -ENODEV; + } + portid_msk |=3D BIT(portid + 1); } - portid_msk |=3D BIT(portid + 1); - } =20 - ret =3D regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, - (u32)portid_msk, enable ? (u32)portid_msk : 0); + ret =3D regmap_update_bits(data->pericfg, PERICFG_IOMMU_1, + (u32)portid_msk, enable ? (u32)portid_msk : 0); + } if (ret) dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n", enable ? "enable" : "disable", @@ -1317,7 +1328,8 @@ static int mtk_iommu_probe(struct platform_device *pd= ev) dev_err_probe(dev, ret, "mm dts parse fail\n"); goto out_runtime_disable; } - } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) { + } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) && + !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) { p =3D data->plat_data->pericfg_comp_str; data->pericfg =3D syscon_regmap_lookup_by_compatible(p); if (IS_ERR(data->pericfg)) { diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h index dfd8efca5e60..000eb1cf68b7 100644 --- a/include/soc/mediatek/smi.h +++ b/include/soc/mediatek/smi.h @@ -13,6 +13,7 @@ =20 enum iommu_atf_cmd { IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */ + IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */ IOMMU_ATF_CMD_MAX, }; =20 --=20 2.18.0