From nobody Fri Apr 10 08:16:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B86B2C636CC for ; Wed, 15 Feb 2023 19:54:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229537AbjBOTyD (ORCPT ); Wed, 15 Feb 2023 14:54:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229550AbjBOTyA (ORCPT ); Wed, 15 Feb 2023 14:54:00 -0500 Received: from mail-io1-xd35.google.com (mail-io1-xd35.google.com [IPv6:2607:f8b0:4864:20::d35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3317C76A5 for ; Wed, 15 Feb 2023 11:53:58 -0800 (PST) Received: by mail-io1-xd35.google.com with SMTP id 65so7565786iou.3 for ; Wed, 15 Feb 2023 11:53:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YbMLPKGF7WhK7cdDBBY2la/NoWBzR8bhvPOtNAmLCnQ=; b=JauapKQSc+yTYJuA2tbKx2MyJ6hDWbl0keveabfqq02FTqMpXAiVK5PYexk4tHBhVZ v3YcU3RbguraYhH3HiM9ELy/vyA5Mp+I2/gcR6WO5jSp6hKm0zjRnk3b5TE5EWFdhfv3 5b/NTlDWhiu22+YOJwfxocQuxQHfTXp/2lAvm+UN+BYktqRYufuGgGqUOPMJcpRZ4MVk AM5JTKGdmwJew8zNOjfTOI8OTpcgNoL0ASeKXpdbX8YFPfOVh0wPkEh9i/LIlxX1y3b1 VTPW4e02pEVfu3Tz4pqhbpnnRiY0SxbOjRXsB93cwh6Q0RpIq0N1a7On7JNfW5RJC4XH Pm7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YbMLPKGF7WhK7cdDBBY2la/NoWBzR8bhvPOtNAmLCnQ=; b=pBk+Px7pqfSD4pkVxQsPQbsWpcwK5pAJN1hFhq7FOndNCW+IeZVbfeYwkmvdjakdkS I0TixIEJtuNU3u4TkNyDSLhe4tk+QNe9FUEGhbOc/3yXhnW2Lv+2e3sKWEEmRMR2U6hZ E36kYIeK5At0dGLvQgCd8NMrYCw00BwDTfRyKi+wrzIt3KDvgUKXs96xTzZ5PBZxqCHr n+nXDMPS4ljHo5YF5FtJJ8mNF7qByCnvs11wRjxzqApmp3bdnHCMnAS6Th2eF3g2KjW+ MMwI2AS6ILPS8BddgvdnU322czzfKGQFwgK2nUmSHCttT2keL591BE7Weddd0DVJsEZf 2CdA== X-Gm-Message-State: AO0yUKXw6IeP/ld3+HsjXw6rTStXlFTvUE9mKyQRxN6eIkM75kzJ9He3 4FiqVytlgXmWjF8uwxgPKRuPCw== X-Google-Smtp-Source: AK7set/FFZNXp/mkKAuWlNfVUSDHbzd3XSCgK30Giq5p1EZGcNegbcehzTMalw8ddLkmXdwJmPIVXw== X-Received: by 2002:a5d:8048:0:b0:71a:b85c:2995 with SMTP id b8-20020a5d8048000000b0071ab85c2995mr2416487ior.15.1676490837532; Wed, 15 Feb 2023 11:53:57 -0800 (PST) Received: from presto.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id n10-20020a5ed90a000000b0073a312aaae5sm6291847iop.36.2023.02.15.11.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 11:53:57 -0800 (PST) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: caleb.connolly@linaro.org, mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/6] net: ipa: fix an incorrect assignment Date: Wed, 15 Feb 2023 13:53:47 -0600 Message-Id: <20230215195352.755744-2-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230215195352.755744-1-elder@linaro.org> References: <20230215195352.755744-1-elder@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" I spotted an error in a patch posted this week, unfortunately just after it got accepted. The effect of the bug is that time-based interrupt moderation is disabled. This is not technically a bug, but it is not what is intended. The problem is that a |=3D assignment got implemented as a simple assignment, so the previously assigned value was ignored. Fixes: edc6158b18af ("net: ipa: define fields for event-ring related regist= ers") Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index f44d2d843de12..05ea2502201da 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -762,7 +762,7 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 e= vt_ring_id) /* Enable interrupt moderation by setting the moderation delay */ reg =3D gsi_reg(gsi, EV_CH_E_CNTXT_8); val =3D reg_encode(reg, EV_MODT, GSI_EVT_RING_INT_MODT); - val =3D reg_encode(reg, EV_MODC, 1); /* comes from channel */ + val |=3D reg_encode(reg, EV_MODC, 1); /* comes from channel */ /* EV_MOD_CNT is 0 (no counter-based interrupt coalescing) */ iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); =20 --=20 2.34.1 From nobody Fri Apr 10 08:16:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46C44C64EC4 for ; Wed, 15 Feb 2023 19:54:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229909AbjBOTyP (ORCPT ); Wed, 15 Feb 2023 14:54:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229709AbjBOTyE (ORCPT ); Wed, 15 Feb 2023 14:54:04 -0500 Received: from mail-io1-xd30.google.com (mail-io1-xd30.google.com [IPv6:2607:f8b0:4864:20::d30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CEE483F8 for ; Wed, 15 Feb 2023 11:53:59 -0800 (PST) Received: by mail-io1-xd30.google.com with SMTP id r6so7568672ioj.5 for ; Wed, 15 Feb 2023 11:53:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JkFe6uhk5ONIFKOjCNIRbQcHGkvQiSGhIiuc4gXX3aI=; b=pDO9ZJlYzKICmrvTZajRUBxqUwY+6g0fd1N5olNvj54UeDb1SXNYaR4WjEBy/J3tCI f53AyIHwN7cqZs1HdkR9o8/rnzLGMGBwMzG+jUMAOOUKyNQYNcl3wfyn/MSey/LTJ9yM VexnOU4mHrlD00+xXeVjsJQEoLxtadnXu3Rc8WqocO2t9l/abJ6gH7Jcv8YV7KvVOj6a oJ0c4Sx+o8xYnQV3NkDO3RhBmKFyyZKsK1Oy/Y7shvcuRg8qZmlThvUy1SJQ4aHj6alP dryGnCBle5bHGDOF+0NC+D11BMpxWrYfF7VudfDYsLZtpOxd/S8CfixYtKQAnHEAk4Ar wtgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JkFe6uhk5ONIFKOjCNIRbQcHGkvQiSGhIiuc4gXX3aI=; b=mvcztEyM+cc7biB4KgIenUtfaTXYe4FyP3ghFTHQzjCdc2m88swfr3Viuicygx6R3b Dt0bM0iQIMTXgzZIL03vdRdraMLGEHBGBjR2WpgH6c65O6KBa4O0fxXU6G5cVCl9oPKm sZgtboIfoWvILtgYqXh4KkDo3jppbVmguorBxw8MIKMuKKj0el+vc44KgpE69NEZpqG6 6MbiwujRZNELnhVJwwFgTdYpDF/+h+haRuCCfJP4IMXrJ9qExdWTdPjVpvFzsgjIU1oP KqIf/Ef/9s+fuKGkyd/t4reHJBAQLNYXvUP2iHE7cGUKlZVGqjsC70nP3s3FdSNBlzk7 9oyw== X-Gm-Message-State: AO0yUKXr3S/BQ60SruSeORQ19hUuZBN4Zf/ihdPb+Ov0nl85drjnd/gR vksGYbV8F/fVLBThEgfKjv5Waw== X-Google-Smtp-Source: AK7set9nu1OYd931TxWDPuVHbhAYLpb8q3ldejqRSGI0xkz5AXra4p0bZQp+bJo8aRNQFBjPj/Mhvg== X-Received: by 2002:a05:6602:14ca:b0:71e:d132:d08f with SMTP id b10-20020a05660214ca00b0071ed132d08fmr326265iow.9.1676490838762; Wed, 15 Feb 2023 11:53:58 -0800 (PST) Received: from presto.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id n10-20020a5ed90a000000b0073a312aaae5sm6291847iop.36.2023.02.15.11.53.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 11:53:58 -0800 (PST) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: caleb.connolly@linaro.org, mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/6] net: ipa: kill gsi->virt_raw Date: Wed, 15 Feb 2023 13:53:48 -0600 Message-Id: <20230215195352.755744-3-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230215195352.755744-1-elder@linaro.org> References: <20230215195352.755744-1-elder@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting at IPA v4.5, almost all GSI registers had their offsets changed by a fixed amount (shifted downward by 0xd000). Rather than defining offsets for all those registers dependent on version, an adjustment was applied for most register accesses. This was implemented in commit cdeee49f3ef7f ("net: ipa: adjust GSI register addresses"). It was later modified to be a bit more obvious about the adjusment, in commit 571b1e7e58ad3 ("net: ipa: use a separate pointer for adjusted GSI memory"). We now are able to define every GSI register with its own offset, so there's no need to implement this special adjustment. So get rid of the "virt_raw" pointer, and just maintain "virt" as the (non-adjusted) base address of I/O mapped GSI register memory. Redefine the offsets of all GSI registers (other than the INTER_EE ones, which were not subject to the adjustment) for IPA v4.5+, subtracting 0xd000 from their defined offsets instead. Move the ERROR_LOG and ERROR_LOG_CLR definitions further down in the register definition files so all registers are defined in order of their offset. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 5 +- drivers/net/ipa/gsi.h | 3 +- drivers/net/ipa/gsi_reg.c | 35 ++------- drivers/net/ipa/gsi_reg.h | 3 +- drivers/net/ipa/reg/gsi_reg-v3.1.c | 14 ++-- drivers/net/ipa/reg/gsi_reg-v3.5.1.c | 14 ++-- drivers/net/ipa/reg/gsi_reg-v4.0.c | 14 ++-- drivers/net/ipa/reg/gsi_reg-v4.11.c | 110 +++++++++++++-------------- drivers/net/ipa/reg/gsi_reg-v4.5.c | 58 +++++++------- drivers/net/ipa/reg/gsi_reg-v4.9.c | 66 ++++++++-------- 10 files changed, 141 insertions(+), 181 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 05ea2502201da..2ef5509e3c836 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -1999,12 +1999,11 @@ static int gsi_irq_setup(struct gsi *gsi) =20 /* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */ if (gsi->version > IPA_VERSION_3_1) { - /* These registers are in the non-adjusted address range */ reg =3D gsi_reg(gsi, INTER_EE_SRC_CH_IRQ_MSK); - iowrite32(0, gsi->virt_raw + reg_offset(reg)); + iowrite32(0, gsi->virt + reg_offset(reg)); =20 reg =3D gsi_reg(gsi, INTER_EE_SRC_EV_CH_IRQ_MSK); - iowrite32(0, gsi->virt_raw + reg_offset(reg)); + iowrite32(0, gsi->virt + reg_offset(reg)); } =20 reg =3D gsi_reg(gsi, CNTXT_GSI_IRQ_EN); diff --git a/drivers/net/ipa/gsi.h b/drivers/net/ipa/gsi.h index bc5ff617341a7..50bc80cb167c3 100644 --- a/drivers/net/ipa/gsi.h +++ b/drivers/net/ipa/gsi.h @@ -140,8 +140,7 @@ struct gsi_evt_ring { struct gsi { struct device *dev; /* Same as IPA device */ enum ipa_version version; - void __iomem *virt_raw; /* I/O mapped address range */ - void __iomem *virt; /* Adjusted for most registers */ + void __iomem *virt; /* I/O mapped registers */ const struct regs *regs; =20 u32 irq; diff --git a/drivers/net/ipa/gsi_reg.c b/drivers/net/ipa/gsi_reg.c index 0bb70a7ef4e65..1412b67304c8e 100644 --- a/drivers/net/ipa/gsi_reg.c +++ b/drivers/net/ipa/gsi_reg.c @@ -9,20 +9,6 @@ #include "reg.h" #include "gsi_reg.h" =20 -/* GSI EE registers as a group are shifted downward by a fixed constant am= ount - * for IPA versions 4.5 and beyond. This applies to all GSI registers we = use - * *except* the ones that disable inter-EE interrupts for channels and eve= nt - * channels. - * - * The "raw" (not adjusted) GSI register range is mapped, and a pointer to - * the mapped range is held in gsi->virt_raw. The inter-EE interrupt - * registers are accessed using that pointer. - * - * Most registers are accessed using gsi->virt, which is a copy of the "ra= w" - * pointer, adjusted downward by the fixed amount. - */ -#define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ - /* Is this register ID valid for the current GSI version? */ static bool gsi_reg_id_valid(struct gsi *gsi, enum gsi_reg_id reg_id) { @@ -121,13 +107,12 @@ static const struct regs *gsi_regs(struct gsi *gsi) } } =20 -/* Sets gsi->virt_raw and gsi->virt, and I/O maps the "gsi" memory range */ +/* Sets gsi->virt and I/O maps the "gsi" memory range for registers */ int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct resource *res; resource_size_t size; - u32 adjust; =20 /* Get GSI memory range and map it */ res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsi"); @@ -142,27 +127,17 @@ int gsi_reg_init(struct gsi *gsi, struct platform_dev= ice *pdev) return -EINVAL; } =20 - /* Make sure we can make our pointer adjustment if necessary */ - adjust =3D gsi->version < IPA_VERSION_4_5 ? 0 : GSI_EE_REG_ADJUST; - if (res->start < adjust) { - dev_err(dev, "DT memory resource \"gsi\" too low (< %u)\n", - adjust); - return -EINVAL; - } - gsi->regs =3D gsi_regs(gsi); if (!gsi->regs) { dev_err(dev, "unsupported IPA version %u (?)\n", gsi->version); return -EINVAL; } =20 - gsi->virt_raw =3D ioremap(res->start, size); - if (!gsi->virt_raw) { + gsi->virt =3D ioremap(res->start, size); + if (!gsi->virt) { dev_err(dev, "unable to remap \"gsi\" memory\n"); return -ENOMEM; } - /* Most registers are accessed using an adjusted register range */ - gsi->virt =3D gsi->virt_raw - adjust; =20 return 0; } @@ -170,7 +145,7 @@ int gsi_reg_init(struct gsi *gsi, struct platform_devic= e *pdev) /* Inverse of gsi_reg_init() */ void gsi_reg_exit(struct gsi *gsi) { + iounmap(gsi->virt); gsi->virt =3D NULL; - iounmap(gsi->virt_raw); - gsi->virt_raw =3D NULL; + gsi->regs =3D NULL; } diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 5eda4def7ac40..e85765002aa41 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -351,8 +351,7 @@ const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg= _id reg_id); * @pdev: GSI (IPA) platform device * * Initialize GSI registers, including looking up and I/O mapping - * the "gsi" memory space. This function sets gsi->virt_raw and - * gsi->virt. + * the "gsi" memory space. */ int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev); =20 diff --git a/drivers/net/ipa/reg/gsi_reg-v3.1.c b/drivers/net/ipa/reg/gsi_r= eg-v3.1.c index 651c8a7ed6116..8451d3f8e421e 100644 --- a/drivers/net/ipa/reg/gsi_reg-v3.1.c +++ b/drivers/net/ipa/reg/gsi_reg-v3.1.c @@ -8,16 +8,12 @@ #include "../reg.h" #include "../gsi_reg.h" =20 -/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ - REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 0x0000c020 + 0x1000 * GSI_EE_AP); =20 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 0x0000c024 + 0x1000 * GSI_EE_AP); =20 -/* All other register offsets are relative to gsi->virt */ - static const u32 reg_ch_c_cntxt_0_fmask[] =3D { [CHTYPE_PROTOCOL] =3D GENMASK(2, 0), [CHTYPE_DIR] =3D BIT(3), @@ -66,10 +62,6 @@ static const u32 reg_error_log_fmask[] =3D { [ERR_EE] =3D GENMASK(31, 28), }; =20 -REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); - -REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); - REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); =20 @@ -152,6 +144,7 @@ REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 = * GSI_EE_AP); =20 static const u32 reg_ch_cmd_fmask[] =3D { [CH_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [CH_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -159,6 +152,7 @@ REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE= _AP); =20 static const u32 reg_ev_ch_cmd_fmask[] =3D { [EV_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [EV_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -220,6 +214,10 @@ static const u32 reg_cntxt_intset_fmask[] =3D { =20 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); =20 +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + static const u32 reg_cntxt_scratch_0_fmask[] =3D { [INTER_EE_RESULT] =3D GENMASK(2, 0), /* Bits 3-4 reserved */ diff --git a/drivers/net/ipa/reg/gsi_reg-v3.5.1.c b/drivers/net/ipa/reg/gsi= _reg-v3.5.1.c index 0b39f8374ec17..87e75cf425135 100644 --- a/drivers/net/ipa/reg/gsi_reg-v3.5.1.c +++ b/drivers/net/ipa/reg/gsi_reg-v3.5.1.c @@ -8,16 +8,12 @@ #include "../reg.h" #include "../gsi_reg.h" =20 -/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ - REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 0x0000c020 + 0x1000 * GSI_EE_AP); =20 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 0x0000c024 + 0x1000 * GSI_EE_AP); =20 -/* All other register offsets are relative to gsi->virt */ - static const u32 reg_ch_c_cntxt_0_fmask[] =3D { [CHTYPE_PROTOCOL] =3D GENMASK(2, 0), [CHTYPE_DIR] =3D BIT(3), @@ -66,10 +62,6 @@ static const u32 reg_error_log_fmask[] =3D { [ERR_EE] =3D GENMASK(31, 28), }; =20 -REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); - -REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); - REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); =20 @@ -152,6 +144,7 @@ REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 = * GSI_EE_AP); =20 static const u32 reg_ch_cmd_fmask[] =3D { [CH_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [CH_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -159,6 +152,7 @@ REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE= _AP); =20 static const u32 reg_ev_ch_cmd_fmask[] =3D { [EV_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [EV_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -231,6 +225,10 @@ static const u32 reg_cntxt_intset_fmask[] =3D { =20 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); =20 +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + static const u32 reg_cntxt_scratch_0_fmask[] =3D { [INTER_EE_RESULT] =3D GENMASK(2, 0), /* Bits 3-4 reserved */ diff --git a/drivers/net/ipa/reg/gsi_reg-v4.0.c b/drivers/net/ipa/reg/gsi_r= eg-v4.0.c index 5a979ef4caad3..048832e185091 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.0.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.0.c @@ -8,16 +8,12 @@ #include "../reg.h" #include "../gsi_reg.h" =20 -/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ - REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 0x0000c020 + 0x1000 * GSI_EE_AP); =20 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 0x0000c024 + 0x1000 * GSI_EE_AP); =20 -/* All other register offsets are relative to gsi->virt */ - static const u32 reg_ch_c_cntxt_0_fmask[] =3D { [CHTYPE_PROTOCOL] =3D GENMASK(2, 0), [CHTYPE_DIR] =3D BIT(3), @@ -67,10 +63,6 @@ static const u32 reg_error_log_fmask[] =3D { [ERR_EE] =3D GENMASK(31, 28), }; =20 -REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); - -REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); - REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); =20 @@ -153,6 +145,7 @@ REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 = * GSI_EE_AP); =20 static const u32 reg_ch_cmd_fmask[] =3D { [CH_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [CH_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -160,6 +153,7 @@ REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE= _AP); =20 static const u32 reg_ev_ch_cmd_fmask[] =3D { [EV_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [EV_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -236,6 +230,10 @@ static const u32 reg_cntxt_intset_fmask[] =3D { =20 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); =20 +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + static const u32 reg_cntxt_scratch_0_fmask[] =3D { [INTER_EE_RESULT] =3D GENMASK(2, 0), /* Bits 3-4 reserved */ diff --git a/drivers/net/ipa/reg/gsi_reg-v4.11.c b/drivers/net/ipa/reg/gsi_= reg-v4.11.c index d975973306598..ced762ca16f91 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.11.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.11.c @@ -8,16 +8,12 @@ #include "../reg.h" #include "../gsi_reg.h" =20 -/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ - REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 0x0000c020 + 0x1000 * GSI_EE_AP); =20 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 0x0000c024 + 0x1000 * GSI_EE_AP); =20 -/* All other register offsets are relative to gsi->virt */ - static const u32 reg_ch_c_cntxt_0_fmask[] =3D { [CHTYPE_PROTOCOL] =3D GENMASK(2, 0), [CHTYPE_DIR] =3D BIT(3), @@ -31,7 +27,7 @@ static const u32 reg_ch_c_cntxt_0_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, - 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80); =20 static const u32 reg_ch_c_cntxt_1_fmask[] =3D { [CH_R_LENGTH] =3D GENMASK(19, 0), @@ -39,11 +35,11 @@ static const u32 reg_ch_c_cntxt_1_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, - 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x= 80); +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x= 80); =20 -REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x= 80); +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x= 80); =20 static const u32 reg_ch_c_qos_fmask[] =3D { [WRR_WEIGHT] =3D GENMASK(3, 0), @@ -57,7 +53,7 @@ static const u32 reg_ch_c_qos_fmask[] =3D { /* Bits 25-31 reserved */ }; =20 -REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x8= 0); +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x8= 0); =20 static const u32 reg_error_log_fmask[] =3D { [ERR_ARG3] =3D GENMASK(3, 0), @@ -70,21 +66,17 @@ static const u32 reg_error_log_fmask[] =3D { [ERR_EE] =3D GENMASK(31, 28), }; =20 -REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); - -REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); - REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, - 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, - 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, - 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, - 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80); =20 static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { [EV_CHTYPE] =3D GENMASK(3, 0), @@ -97,19 +89,19 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, - 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010000 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, - 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010008 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, - 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); + 0x0001000c + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, - 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010010 + 0x4000 * GSI_EE_AP, 0x80); =20 static const u32 reg_ev_ch_e_cntxt_8_fmask[] =3D { [EV_MODT] =3D GENMASK(15, 0), @@ -118,55 +110,57 @@ static const u32 reg_ev_ch_e_cntxt_8_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, - 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010020 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, - 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010024 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, - 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010028 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, - 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); + 0x0001002c + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, - 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010030 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, - 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010034 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, - 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010048 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, - 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); + 0x0001004c + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, - 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); + 0x00011000 + 0x4000 * GSI_EE_AP, 0x08); =20 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, - 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); + 0x00011100 + 0x4000 * GSI_EE_AP, 0x08); =20 static const u32 reg_gsi_status_fmask[] =3D { [ENABLED] =3D BIT(0), /* Bits 1-31 reserved */ }; =20 -REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); +REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_ch_cmd_fmask[] =3D { [CH_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [CH_OPCODE] =3D GENMASK(31, 24), }; =20 -REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); +REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_ev_ch_cmd_fmask[] =3D { [EV_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [EV_OPCODE] =3D GENMASK(31, 24), }; =20 -REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_generic_cmd_fmask[] =3D { [GENERIC_OPCODE] =3D GENMASK(4, 0), @@ -176,7 +170,7 @@ static const u32 reg_generic_cmd_fmask[] =3D { [GENERIC_PARAMS] =3D GENMASK(31, 24), }; =20 -REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_hw_param_2_fmask[] =3D { [IRAM_SIZE] =3D GENMASK(2, 0), @@ -192,54 +186,58 @@ static const u32 reg_hw_param_2_fmask[] =3D { [GSI_USE_INTER_EE] =3D BIT(31), }; =20 -REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP); +REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_A= P); =20 -REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE= _AP); +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE= _AP); =20 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, - 0x0001f098 + 0x4000 * GSI_EE_AP); + 0x00012098 + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, - 0x0001f09c + 0x4000 * GSI_EE_AP); + 0x0001209c + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, - 0x0001f0a0 + 0x4000 * GSI_EE_AP); + 0x000120a0 + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, - 0x0001f0a4 + 0x4000 * GSI_EE_AP); + 0x000120a4 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_A= P); =20 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, - 0x0001f0b8 + 0x4000 * GSI_EE_AP); + 0x000120b8 + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, - 0x0001f0c0 + 0x4000 * GSI_EE_AP); + 0x000120c0 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE= _AP); +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE= _AP); =20 -REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_A= P); =20 -REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_A= P); =20 -REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_cntxt_intset_fmask[] =3D { [INTYPE] =3D BIT(0) /* Bits 1-31 reserved */ }; =20 -REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_cntxt_scratch_0_fmask[] =3D { [INTER_EE_RESULT] =3D GENMASK(2, 0), @@ -248,7 +246,7 @@ static const u32 reg_cntxt_scratch_0_fmask[] =3D { /* Bits 8-31 reserved */ }; =20 -REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_= AP); +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_= AP); =20 static const struct reg *reg_array[] =3D { [INTER_EE_SRC_CH_IRQ_MSK] =3D ®_inter_ee_src_ch_irq_msk, diff --git a/drivers/net/ipa/reg/gsi_reg-v4.5.c b/drivers/net/ipa/reg/gsi_r= eg-v4.5.c index 13c66b29840ee..1ede8276824d7 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.5.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.5.c @@ -8,16 +8,12 @@ #include "../reg.h" #include "../gsi_reg.h" =20 -/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ - REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 0x0000c020 + 0x1000 * GSI_EE_AP); =20 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 0x0000c024 + 0x1000 * GSI_EE_AP); =20 -/* All other register offsets are relative to gsi->virt */ - static const u32 reg_ch_c_cntxt_0_fmask[] =3D { [CHTYPE_PROTOCOL] =3D GENMASK(2, 0), [CHTYPE_DIR] =3D BIT(3), @@ -31,7 +27,7 @@ static const u32 reg_ch_c_cntxt_0_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, - 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80); =20 static const u32 reg_ch_c_cntxt_1_fmask[] =3D { [CH_R_LENGTH] =3D GENMASK(15, 0), @@ -39,11 +35,11 @@ static const u32 reg_ch_c_cntxt_1_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, - 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x= 80); +REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x= 80); =20 -REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x= 80); +REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x= 80); =20 static const u32 reg_ch_c_qos_fmask[] =3D { [WRR_WEIGHT] =3D GENMASK(3, 0), @@ -56,7 +52,7 @@ static const u32 reg_ch_c_qos_fmask[] =3D { /* Bits 24-31 reserved */ }; =20 -REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x8= 0); +REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x8= 0); =20 static const u32 reg_error_log_fmask[] =3D { [ERR_ARG3] =3D GENMASK(3, 0), @@ -69,21 +65,17 @@ static const u32 reg_error_log_fmask[] =3D { [ERR_EE] =3D GENMASK(31, 28), }; =20 -REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); - -REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); - REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, - 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, - 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, - 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, - 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); + 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80); =20 static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { [EV_CHTYPE] =3D GENMASK(3, 0), @@ -96,19 +88,19 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, - 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010000 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, - 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010008 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, - 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); + 0x0001000c + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, - 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010010 + 0x4000 * GSI_EE_AP, 0x80); =20 static const u32 reg_ev_ch_e_cntxt_8_fmask[] =3D { [EV_MODT] =3D GENMASK(15, 0), @@ -117,28 +109,28 @@ static const u32 reg_ev_ch_e_cntxt_8_fmask[] =3D { }; =20 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, - 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010020 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, - 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010024 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, - 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010028 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, - 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); + 0x0001002c + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, - 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010030 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, - 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010034 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, - 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); + 0x00010048 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, - 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); + 0x0001004c + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); @@ -155,6 +147,7 @@ REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 = * GSI_EE_AP); =20 static const u32 reg_ch_cmd_fmask[] =3D { [CH_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [CH_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -162,6 +155,7 @@ REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE= _AP); =20 static const u32 reg_ev_ch_cmd_fmask[] =3D { [EV_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [EV_OPCODE] =3D GENMASK(31, 24), }; =20 @@ -239,6 +233,10 @@ static const u32 reg_cntxt_intset_fmask[] =3D { =20 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); =20 +REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); + static const u32 reg_cntxt_scratch_0_fmask[] =3D { [INTER_EE_RESULT] =3D GENMASK(2, 0), /* Bits 3-4 reserved */ diff --git a/drivers/net/ipa/reg/gsi_reg-v4.9.c b/drivers/net/ipa/reg/gsi_r= eg-v4.9.c index a7d5732b72e90..9374c89609d9a 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.9.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.9.c @@ -8,16 +8,12 @@ #include "../reg.h" #include "../gsi_reg.h" =20 -/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ - REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, 0x0000c020 + 0x1000 * GSI_EE_AP); =20 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, 0x0000c024 + 0x1000 * GSI_EE_AP); =20 -/* All other register offsets are relative to gsi->virt */ - static const u32 reg_ch_c_cntxt_0_fmask[] =3D { [CHTYPE_PROTOCOL] =3D GENMASK(2, 0), [CHTYPE_DIR] =3D BIT(3), @@ -70,10 +66,6 @@ static const u32 reg_error_log_fmask[] =3D { [ERR_EE] =3D GENMASK(31, 28), }; =20 -REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); - -REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); - REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); =20 @@ -142,31 +134,33 @@ REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, - 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); + 0x00011000 + 0x4000 * GSI_EE_AP, 0x08); =20 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, - 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); + 0x00011100 + 0x4000 * GSI_EE_AP, 0x08); =20 static const u32 reg_gsi_status_fmask[] =3D { [ENABLED] =3D BIT(0), /* Bits 1-31 reserved */ }; =20 -REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); +REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_ch_cmd_fmask[] =3D { [CH_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [CH_OPCODE] =3D GENMASK(31, 24), }; =20 -REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); +REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_ev_ch_cmd_fmask[] =3D { [EV_CHID] =3D GENMASK(7, 0), + /* Bits 8-23 reserved */ [EV_OPCODE] =3D GENMASK(31, 24), }; =20 -REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); +REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_generic_cmd_fmask[] =3D { [GENERIC_OPCODE] =3D GENMASK(4, 0), @@ -175,7 +169,7 @@ static const u32 reg_generic_cmd_fmask[] =3D { /* Bits 14-31 reserved */ }; =20 -REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); +REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_hw_param_2_fmask[] =3D { [IRAM_SIZE] =3D GENMASK(2, 0), @@ -191,54 +185,58 @@ static const u32 reg_hw_param_2_fmask[] =3D { [GSI_USE_INTER_EE] =3D BIT(31), }; =20 -REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP); +REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); +REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_A= P); =20 -REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); +REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE= _AP); +REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE= _AP); =20 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, - 0x0001f098 + 0x4000 * GSI_EE_AP); + 0x00012098 + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, - 0x0001f09c + 0x4000 * GSI_EE_AP); + 0x0001209c + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, - 0x0001f0a0 + 0x4000 * GSI_EE_AP); + 0x000120a0 + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, - 0x0001f0a4 + 0x4000 * GSI_EE_AP); + 0x000120a4 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_A= P); =20 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, - 0x0001f0b8 + 0x4000 * GSI_EE_AP); + 0x000120b8 + 0x4000 * GSI_EE_AP); =20 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, - 0x0001f0c0 + 0x4000 * GSI_EE_AP); + 0x000120c0 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE= _AP); +REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE= _AP); =20 -REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); +REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_A= P); =20 -REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_A= P); +REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_A= P); =20 -REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); +REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP); =20 -REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); +REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_cntxt_intset_fmask[] =3D { [INTYPE] =3D BIT(0) /* Bits 1-31 reserved */ }; =20 -REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); +REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP); + +REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP); + +REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP); =20 static const u32 reg_cntxt_scratch_0_fmask[] =3D { [INTER_EE_RESULT] =3D GENMASK(2, 0), @@ -247,7 +245,7 @@ static const u32 reg_cntxt_scratch_0_fmask[] =3D { /* Bits 8-31 reserved */ }; =20 -REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_= AP); +REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_= AP); =20 static const struct reg *reg_array[] =3D { [INTER_EE_SRC_CH_IRQ_MSK] =3D ®_inter_ee_src_ch_irq_msk, --=20 2.34.1 From nobody Fri Apr 10 08:16:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D5AC64ED6 for ; Wed, 15 Feb 2023 19:54:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229570AbjBOTyT (ORCPT ); Wed, 15 Feb 2023 14:54:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229820AbjBOTyM (ORCPT ); Wed, 15 Feb 2023 14:54:12 -0500 Received: from mail-io1-xd36.google.com (mail-io1-xd36.google.com [IPv6:2607:f8b0:4864:20::d36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D4FF3D0A2 for ; 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charset="utf-8" Now that we explicitly define each register field width there is no need to have a special encoding function for the event ring length. Add a field for this to the EV_CH_E_CNTXT_1 GSI register, and use it in place of ev_ch_e_cntxt_1_length_encode() (which can be removed). Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 15 +-------------- drivers/net/ipa/gsi_reg.h | 6 ++++++ drivers/net/ipa/reg/gsi_reg-v3.1.c | 8 ++++++-- drivers/net/ipa/reg/gsi_reg-v3.5.1.c | 8 ++++++-- drivers/net/ipa/reg/gsi_reg-v4.0.c | 8 ++++++-- drivers/net/ipa/reg/gsi_reg-v4.11.c | 8 ++++++-- drivers/net/ipa/reg/gsi_reg-v4.5.c | 8 ++++++-- drivers/net/ipa/reg/gsi_reg-v4.9.c | 8 ++++++-- 8 files changed, 43 insertions(+), 26 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 2ef5509e3c836..0e6f679f71a8c 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -193,17 +193,6 @@ static u32 ch_c_cntxt_0_type_encode(enum ipa_version v= ersion, return val | reg_encode(reg, CHTYPE_PROTOCOL_MSB, type); } =20 -/* Encode the length of the event channel ring buffer for the - * EV_CH_E_CNTXT_1 register. - */ -static u32 ev_ch_e_cntxt_1_length_encode(enum ipa_version version, u32 len= gth) -{ - if (version < IPA_VERSION_4_9) - return u32_encode_bits(length, GENMASK(15, 0)); - - return u32_encode_bits(length, GENMASK(19, 0)); -} - /* Update the GSI IRQ type register with the cached value */ static void gsi_irq_type_update(struct gsi *gsi, u32 val) { @@ -731,7 +720,6 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 e= vt_ring_id) struct gsi_evt_ring *evt_ring =3D &gsi->evt_ring[evt_ring_id]; struct gsi_ring *ring =3D &evt_ring->ring; const struct reg *reg; - size_t size; u32 val; =20 reg =3D gsi_reg(gsi, EV_CH_E_CNTXT_0); @@ -743,8 +731,7 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 e= vt_ring_id) iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); =20 reg =3D gsi_reg(gsi, EV_CH_E_CNTXT_1); - size =3D ring->count * GSI_RING_ELEMENT_SIZE; - val =3D ev_ch_e_cntxt_1_length_encode(gsi->version, size); + val =3D reg_encode(reg, R_LENGTH, ring->count * GSI_RING_ELEMENT_SIZE); iowrite32(val, gsi->virt + reg_n_offset(reg, evt_ring_id)); =20 /* The context 2 and 3 registers store the low-order and diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index e85765002aa41..a0b7ff0dcdfda 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -135,6 +135,7 @@ enum gsi_reg_ch_c_qos_field_id { PREFETCH_MODE, /* IPA v4.5+ */ EMPTY_LVL_THRSHOLD, /* IPA v4.5+ */ DB_IN_BYTES, /* IPA v4.9+ */ + LOW_LATENCY_EN, /* IPA v5.0+ */ }; =20 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ @@ -155,6 +156,11 @@ enum gsi_reg_ch_c_ev_ch_e_cntxt_0_field_id { EV_ELEMENT_SIZE, }; =20 +/* EV_CH_E_CNTXT_1 register */ +enum gsi_reg_ev_ch_c_cntxt_1_field_id { + R_LENGTH, +}; + /* EV_CH_E_CNTXT_8 register */ enum gsi_reg_ch_c_ev_ch_e_cntxt_8_field_id { EV_MODT, diff --git a/drivers/net/ipa/reg/gsi_reg-v3.1.c b/drivers/net/ipa/reg/gsi_r= eg-v3.1.c index 8451d3f8e421e..e036805a78824 100644 --- a/drivers/net/ipa/reg/gsi_reg-v3.1.c +++ b/drivers/net/ipa/reg/gsi_reg-v3.1.c @@ -87,8 +87,12 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); +static const u32 reg_ev_ch_e_cntxt_1_fmask[] =3D { + [R_LENGTH] =3D GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); diff --git a/drivers/net/ipa/reg/gsi_reg-v3.5.1.c b/drivers/net/ipa/reg/gsi= _reg-v3.5.1.c index 87e75cf425135..8c3ab3a5288e6 100644 --- a/drivers/net/ipa/reg/gsi_reg-v3.5.1.c +++ b/drivers/net/ipa/reg/gsi_reg-v3.5.1.c @@ -87,8 +87,12 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); +static const u32 reg_ev_ch_e_cntxt_1_fmask[] =3D { + [R_LENGTH] =3D GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); diff --git a/drivers/net/ipa/reg/gsi_reg-v4.0.c b/drivers/net/ipa/reg/gsi_r= eg-v4.0.c index 048832e185091..7cc7a21d07f90 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.0.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.0.c @@ -88,8 +88,12 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); +static const u32 reg_ev_ch_e_cntxt_1_fmask[] =3D { + [R_LENGTH] =3D GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); diff --git a/drivers/net/ipa/reg/gsi_reg-v4.11.c b/drivers/net/ipa/reg/gsi_= reg-v4.11.c index ced762ca16f91..01696519032fa 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.11.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.11.c @@ -91,8 +91,12 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 0x00010000 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); +static const u32 reg_ev_ch_e_cntxt_1_fmask[] =3D { + [R_LENGTH] =3D GENMASK(19, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 0x00010008 + 0x4000 * GSI_EE_AP, 0x80); diff --git a/drivers/net/ipa/reg/gsi_reg-v4.5.c b/drivers/net/ipa/reg/gsi_r= eg-v4.5.c index 1ede8276824d7..648b51b88d4e8 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.5.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.5.c @@ -90,8 +90,12 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 0x00010000 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); +static const u32 reg_ev_ch_e_cntxt_1_fmask[] =3D { + [R_LENGTH] =3D GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x00010004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 0x00010008 + 0x4000 * GSI_EE_AP, 0x80); diff --git a/drivers/net/ipa/reg/gsi_reg-v4.9.c b/drivers/net/ipa/reg/gsi_r= eg-v4.9.c index 9374c89609d9a..4bf45d264d6b9 100644 --- a/drivers/net/ipa/reg/gsi_reg-v4.9.c +++ b/drivers/net/ipa/reg/gsi_reg-v4.9.c @@ -91,8 +91,12 @@ static const u32 reg_ev_ch_e_cntxt_0_fmask[] =3D { REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); =20 -REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, - 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); +static const u32 reg_ev_ch_e_cntxt_1_fmask[] =3D { + [R_LENGTH] =3D GENMASK(15, 0), +}; + +REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, + 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); =20 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); --=20 2.34.1 From nobody Fri Apr 10 08:16:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E12C636D4 for ; Wed, 15 Feb 2023 19:54:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229867AbjBOTyV (ORCPT ); Wed, 15 Feb 2023 14:54:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229817AbjBOTyM (ORCPT ); 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Wed, 15 Feb 2023 11:54:00 -0800 (PST) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: caleb.connolly@linaro.org, mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/6] net: ipa: avoid setting an undefined field Date: Wed, 15 Feb 2023 13:53:50 -0600 Message-Id: <20230215195352.755744-5-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230215195352.755744-1-elder@linaro.org> References: <20230215195352.755744-1-elder@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The GSI channel protocol field in the CH_C_CNTXT_0 GSI register is widened starting IPA v5.0, making the CHTYPE_PROTOCOL_MSB field added in IPA v4.5 unnecessary. Update the code to reflect this. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 2 +- drivers/net/ipa/gsi_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 0e6f679f71a8c..88279956194a9 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -185,7 +185,7 @@ static u32 ch_c_cntxt_0_type_encode(enum ipa_version ve= rsion, u32 val; =20 val =3D reg_encode(reg, CHTYPE_PROTOCOL, type); - if (version < IPA_VERSION_4_5) + if (version < IPA_VERSION_4_5 || version >=3D IPA_VERSION_5_0) return val; =20 type >>=3D hweight32(reg_fmask(reg, CHTYPE_PROTOCOL)); diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index a0b7ff0dcdfda..52520cd44c3e1 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -101,7 +101,7 @@ enum gsi_reg_ch_c_cntxt_0_field_id { CHTYPE_DIR, CH_EE, CHID, - CHTYPE_PROTOCOL_MSB, /* IPA v4.9+ */ + CHTYPE_PROTOCOL_MSB, /* IPA v4.5-4.11 */ ERINDEX, CHSTATE, ELEMENT_SIZE, --=20 2.34.1 From nobody Fri Apr 10 08:16:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A6A1C636D4 for ; Wed, 15 Feb 2023 19:54:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229595AbjBOTyZ (ORCPT ); Wed, 15 Feb 2023 14:54:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229851AbjBOTyM (ORCPT ); Wed, 15 Feb 2023 14:54:12 -0500 Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C25613E0BB for ; Wed, 15 Feb 2023 11:54:02 -0800 (PST) Received: by mail-io1-xd2f.google.com with SMTP id l128so7573229iof.2 for ; Wed, 15 Feb 2023 11:54:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=55iMl67tczsHAriI/5ivr6yqGDBI3afdu3qz4PSaV8E=; b=r95+Yi3ZQYV06bxV2XGdq+pI+dROE3kraQJxFy36hyF2kZf3qwVRNdeXalqw7npB7+ F9nVAN/YGf35TkVigA5agOCI2UcK7xgxJhx6DasaNKKv/QDb+nPHpE4KzTalA2fuK6cD haV/45wSAqBwZEe4FboXThoOwDC7Gw6M8j6tPxlS9CbB2K2RulBCHJAVEuHnscEXT7iY YxqWzSwguyWx/utxw6jCYraaVAwtKUbla/78RoYlKzVyz7pzfMB+BaKmdLVJyopkh+Hc yUCwY9mFhuWlEpeU+rxytxI6caoVaEU0dWdwjVdDagGclrg3dq6CoM+l+v5m39ORSst4 uRuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=55iMl67tczsHAriI/5ivr6yqGDBI3afdu3qz4PSaV8E=; b=Hz39AySK86vB3RxBOwUndhq+o12EQG1OBwMu0+jjXoCciuHZ4leNMk69tHAWaEWKDr QRAOmDe4ufYCBfyl67scBD/e5VkliiCjlw0fFJgqR727dtOwYmixvSEII5blW7/kO7ol /58unuo8r+3RGCgFwMfF6KBB2IoLI/THiHNPEMlmeNiS6W28DdgmHd8PhQXOTD1NfedS E/ARgRPIV3Mip4+Bvbc0B4mDTQ+GoldRkmaO5FA7QScINr8dgKUUiFZjFrEnyMfabrnC UlZUC5jbvnYd4Rc11zUqE0pX4cOlyVJSOh6cqxh91qvgGC+pLkrgs9JTSyiabnby4N0S RlBQ== X-Gm-Message-State: AO0yUKUO/Ge49slhOagRgcXRFR7TgQOkul5hnL63Df0KQzalwIO6RUVn m8BlHArV2gHOChNyRFqN7aAxnA== X-Google-Smtp-Source: AK7set/yolWgnkr5CODPg7mXWkmCahG3Y8RDu89TwGLTMT9/2zUHTtDoF0UAhEUqjoCs+mIPKPyHfQ== X-Received: by 2002:a5e:8c14:0:b0:720:9057:a083 with SMTP id n20-20020a5e8c14000000b007209057a083mr2630676ioj.13.1676490842146; Wed, 15 Feb 2023 11:54:02 -0800 (PST) Received: from presto.localdomain ([98.61.227.136]) by smtp.gmail.com with ESMTPSA id n10-20020a5ed90a000000b0073a312aaae5sm6291847iop.36.2023.02.15.11.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 11:54:01 -0800 (PST) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: caleb.connolly@linaro.org, mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/6] net: ipa: support different event ring encoding Date: Wed, 15 Feb 2023 13:53:51 -0600 Message-Id: <20230215195352.755744-6-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230215195352.755744-1-elder@linaro.org> References: <20230215195352.755744-1-elder@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting with IPA v5.0, a channel's event ring index is encoded in a field in the CH_C_CNTXT_1 GSI register rather than CH_C_CNTXT_0. Define a new field ID for the former register and encode the event ring in the appropriate register. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 5 ++++- drivers/net/ipa/gsi_reg.h | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 88279956194a9..f128d5bd6956e 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -840,12 +840,15 @@ static void gsi_channel_program(struct gsi_channel *c= hannel, bool doorbell) val =3D ch_c_cntxt_0_type_encode(gsi->version, reg, GSI_CHANNEL_TYPE_GPI); if (channel->toward_ipa) val |=3D reg_bit(reg, CHTYPE_DIR); - val |=3D reg_encode(reg, ERINDEX, channel->evt_ring_id); + if (gsi->version < IPA_VERSION_5_0) + val |=3D reg_encode(reg, ERINDEX, channel->evt_ring_id); val |=3D reg_encode(reg, ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE); iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); =20 reg =3D gsi_reg(gsi, CH_C_CNTXT_1); val =3D reg_encode(reg, CH_R_LENGTH, size); + if (gsi->version >=3D IPA_VERSION_5_0) + val |=3D reg_encode(reg, CH_ERINDEX, channel->evt_ring_id); iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id)); =20 /* The context 2 and 3 registers store the low-order and diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 52520cd44c3e1..2a19d9e34a10a 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -102,7 +102,7 @@ enum gsi_reg_ch_c_cntxt_0_field_id { CH_EE, CHID, CHTYPE_PROTOCOL_MSB, /* IPA v4.5-4.11 */ - ERINDEX, + ERINDEX, /* Not IPA v5.0+ */ CHSTATE, ELEMENT_SIZE, }; @@ -124,6 +124,7 @@ enum gsi_channel_type { /* CH_C_CNTXT_1 register */ enum gsi_reg_ch_c_cntxt_1_field_id { CH_R_LENGTH, + CH_ERINDEX, /* IPA v5.0+ */ }; =20 /* CH_C_QOS register */ --=20 2.34.1 From nobody Fri Apr 10 08:16:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1D6CC636D4 for ; Wed, 15 Feb 2023 19:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229582AbjBOTzD (ORCPT ); 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Wed, 15 Feb 2023 11:54:02 -0800 (PST) From: Alex Elder To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: caleb.connolly@linaro.org, mka@chromium.org, evgreen@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 6/6] net: ipa: add HW_PARAM_4 GSI register Date: Wed, 15 Feb 2023 13:53:52 -0600 Message-Id: <20230215195352.755744-7-elder@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230215195352.755744-1-elder@linaro.org> References: <20230215195352.755744-1-elder@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting at IPA v5.0, the number of event rings per EE is defined in a field in a new HW_PARAM_4 GSI register rather than HW_PARAM_2. Define this new register and its fields, and update the code that checks the number of rings supported by hardware to use the proper field based on IPA version. Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 7 ++++++- drivers/net/ipa/gsi_reg.h | 9 ++++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index f128d5bd6956e..9a0b1fe4a93a8 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -2042,7 +2042,12 @@ static int gsi_ring_setup(struct gsi *gsi) } gsi->channel_count =3D count; =20 - count =3D reg_decode(reg, NUM_EV_PER_EE, val); + if (gsi->version < IPA_VERSION_5_0) { + count =3D reg_decode(reg, NUM_EV_PER_EE, val); + } else { + reg =3D gsi_reg(gsi, HW_PARAM_4); + count =3D reg_decode(reg, EV_PER_EE, val); + } if (!count) { dev_err(dev, "GSI reports zero event rings supported\n"); return -EINVAL; diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 2a19d9e34a10a..f62f0a5c653d1 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -71,6 +71,7 @@ enum gsi_reg_id { EV_CH_CMD, GENERIC_CMD, HW_PARAM_2, /* IPA v3.5.1+ */ + HW_PARAM_4, /* IPA v5.0+ */ CNTXT_TYPE_IRQ, CNTXT_TYPE_IRQ_MSK, CNTXT_SRC_CH_IRQ, @@ -224,7 +225,7 @@ enum gsi_generic_cmd_opcode { enum gsi_hw_param_2_field_id { IRAM_SIZE, NUM_CH_PER_EE, - NUM_EV_PER_EE, + NUM_EV_PER_EE, /* Not IPA v5.0+ */ GSI_CH_PEND_TRANSLATE, GSI_CH_FULL_LOGIC, GSI_USE_SDMA, /* IPA v4.0+ */ @@ -247,6 +248,12 @@ enum gsi_iram_size { IRAM_SIZE_FOUR_KB =3D 0x5, }; =20 +/* HW_PARAM_4 register */ /* IPA v5.0+ */ +enum gsi_hw_param_4_field_id { + EV_PER_EE, + IRAM_PROTOCOL_COUNT, +}; + /** * enum gsi_irq_type_id: GSI IRQ types * @GSI_CH_CTRL: Channel allocation, deallocation, etc. --=20 2.34.1