From nobody Fri Sep 12 00:07:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB8EFC61DA4 for ; Tue, 14 Feb 2023 23:34:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233009AbjBNXek (ORCPT ); Tue, 14 Feb 2023 18:34:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232909AbjBNXeh (ORCPT ); Tue, 14 Feb 2023 18:34:37 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CC4130E90 for ; Tue, 14 Feb 2023 15:34:35 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id gd1so5812837pjb.1 for ; Tue, 14 Feb 2023 15:34:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=48thYLKBHK3Dz7aYi+ob8EdMN1A5iezy1Q0AVsszte8=; b=Jn/v41TrSgPi7e6JR9bOENXFzhjgLtpC2WLsnLwNjTW2sA+9kmuoLM1lFDzBGeJrxU QS5/MJsMtiR1g6oDcEwRP40IExUIYh9rqMGhye9XxKjX8cWpNFtYCJXWrbTzECRzC9QY hP9K2FhnVeWtagHz3/MhR4vQN6SV0o0tNZj1Oh+DKIIZmrY8smcrIfxUlW2cwIgvu5pv 6lONBp53gmw0hZUKyR5Er/HruRiIhjJZk5bS3nkXwDe2n4XD/iBFH4TP2zhLxAN5Zcfm axGca2beR+bZrCa09YrfKHnHMM/erjZhqStBRfsDE1j9ltSpmIlYbNNa84dhif6gDJbT Ur2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=48thYLKBHK3Dz7aYi+ob8EdMN1A5iezy1Q0AVsszte8=; b=okqmVH2gI+ELuUHgcxOVk4cJ9gZQzDPhvx0S/VlhMbOat34dbZM34mn2LOKFyhVD5I wprF0f6odoqy6GWiwhdUnNYUGUHJHl2GrVFC29Tq8NlQyKp7lJelU9aKjLerFQa6I5Tz ARRXOV2pKzYoP1LSiPpvfQ+LwXI0QA8OWN3qlONDolZDi9iZCTPdwk9167DNmSbHSJ44 CsmhfJtTUQcnah7Jml6bYhlC+UQPKjnjPGhiF/1yp7V84POtrqKrY/ldosKC2KcDK/we 1OaeGF1EYEclzCRocrJsjdDJoGDy1ocwz1Ndf+eqsgSGI2GipWF8W2dAPXOU9veQjhgD ZVKQ== X-Gm-Message-State: AO0yUKVYbleYYbyrJ/z6GL0GPrnqies4HZXZvcVIGHaKpChea2mEiAhY G/15bYeT0JkFmtJxu2PG2U9YrbwrYABlcw== X-Google-Smtp-Source: AK7set9J0o/k+q+LqmlDnLvl6JXhdjpU7GwKbLxhJj0CWsSB8aVXZPThklfApiP6i4PsSc4kiu5oBg== X-Received: by 2002:a17:902:fb10:b0:19a:a5c4:afe9 with SMTP id le16-20020a170902fb1000b0019aa5c4afe9mr357460plb.31.1676417674730; Tue, 14 Feb 2023 15:34:34 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id f12-20020a170902684c00b001963a178dfcsm9434801pln.244.2023.02.14.15.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 15:34:33 -0800 (PST) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Cc: Florian Fainelli , Thomas Gleixner , Marc Zyngier , Oliver Upton , linux-kernel@vger.kernel.org (open list:IRQCHIP DRIVERS), Sudeep Holla , Broadcom internal kernel review list Subject: [PATCH 1/3] irqchip/gic-v3: Use switch/case statements in gic_cpu_pm_notifier Date: Tue, 14 Feb 2023 15:34:24 -0800 Message-Id: <20230214233426.2994501-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214233426.2994501-1-f.fainelli@gmail.com> References: <20230214233426.2994501-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" No functional change, but facilitates adding new states in subsequent changes. Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-gic-v3.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index bb57ab8bff6a..b60fadb7eb44 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1374,14 +1374,20 @@ static int gic_retrigger(struct irq_data *data) static int gic_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v) { - if (cmd =3D=3D CPU_PM_EXIT) { + switch (cmd) { + case CPU_PM_ENTER: + if (gic_dist_security_disabled()) { + gic_write_grpen1(0); + gic_enable_redist(false); + } + break; + case CPU_PM_EXIT: if (gic_dist_security_disabled()) gic_enable_redist(true); gic_cpu_sys_reg_init(); - } else if (cmd =3D=3D CPU_PM_ENTER && gic_dist_security_disabled()) { - gic_write_grpen1(0); - gic_enable_redist(false); + break; } + return NOTIFY_OK; } =20 --=20 2.34.1 From nobody Fri Sep 12 00:07:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 935BCC05027 for ; Tue, 14 Feb 2023 23:34:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233058AbjBNXen (ORCPT ); Tue, 14 Feb 2023 18:34:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233007AbjBNXek (ORCPT ); Tue, 14 Feb 2023 18:34:40 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00FC52B62F for ; Tue, 14 Feb 2023 15:34:36 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id d2so16559458pjd.5 for ; Tue, 14 Feb 2023 15:34:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BzzlaaQdOYO3fTmzqCVpPsOeF7R3YhY93EWeKNyYWH0=; b=IvW9sTrlPHiPPsZF8G2ve15uZyWaqOq/XVQXgfm/1diVn880slPNVRXM/r5KyifoEw PFZHYp5GVsGjLRZYEW+DZ8tZH8YeB80OJ1wJyo3pnyAlLFrkS6zQccV6L169volamnTO RNN/u6ka4ced0ycGXrHT0zf4251gNi5GQUYwFCtdoIE9KDp3glryKVq2NXHu0TlgR7eA j7jSF8fPFADaLnq8PCqbkHHBtPUP2EGf3fAIbP3CrH0ut0Vs4N6qEUqQcOCTPt+8GehG QMNatjojvfyUmBR0HHRiXIgZSDQBC1wbADkhzxPcSP8RBQPDVQIkS+bsXRBD1gHRg1nu mrXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BzzlaaQdOYO3fTmzqCVpPsOeF7R3YhY93EWeKNyYWH0=; b=rnGVdlBZ0mEqvJsBP57oJmkPmSuvx3hvsL5fSRdQFv6GDfoj7Ng2xhCqhqv2JTiIrq vbTfMY6/fABuD6L7uzZElCz9TyxiJ0AiJkS5H17z7RtMU1yjVGpTADE4O8AMl7xl5lQ5 73wiI7Vkn7HEnG0+8YOtt/pfoTWUfF3lyjZAAiZe3Lr7X85vN+AGWhl0qMYSYmdxl5Nl ZLY2IKRpfJujCID6nNxEucA635hyHDz1Z46HS43K2o6YavzHPbfvpfYI+3cJIVdhR7Gv xLCcE+AGNSTl6vx7xuhPb7Q6FgRSBQ0wgk+F0yjYCflsiGamwYKn11Y5oY+o2l5LlDXV /HIQ== X-Gm-Message-State: AO0yUKVYOA9hp26MiTLhlhkOZ5ptoa6spHICCjqyxLikyq7ebuTf1QPt gRYQty3rPJtlLoQ+C1zio+0= X-Google-Smtp-Source: AK7set9BGTlGDBkqA2RV3+Mzj3CGt3c9d1uqr420mbrkrYo47vCblWNGUgNZOkPfJepFh/G4XgnSsA== X-Received: by 2002:a17:902:e750:b0:199:1682:9175 with SMTP id p16-20020a170902e75000b0019916829175mr536755plf.8.1676417676473; Tue, 14 Feb 2023 15:34:36 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id f12-20020a170902684c00b001963a178dfcsm9434801pln.244.2023.02.14.15.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 15:34:35 -0800 (PST) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Cc: Florian Fainelli , Thomas Gleixner , Marc Zyngier , Oliver Upton , linux-kernel@vger.kernel.org (open list:IRQCHIP DRIVERS), Sudeep Holla , Broadcom internal kernel review list Subject: [PATCH 2/3] irqchip/gic-v3: Propagate gic_cpu_pm_init() return code Date: Tue, 14 Feb 2023 15:34:25 -0800 Message-Id: <20230214233426.2994501-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214233426.2994501-1-f.fainelli@gmail.com> References: <20230214233426.2994501-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for allocating memory which may fail, propagate the return code from gic_cpu_pm_init(). Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-gic-v3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index b60fadb7eb44..48b0e9aba27c 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1395,9 +1395,11 @@ static struct notifier_block gic_cpu_pm_notifier_blo= ck =3D { .notifier_call =3D gic_cpu_pm_notifier, }; =20 -static void gic_cpu_pm_init(void) +static int gic_cpu_pm_init(void) { cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); + + return 0; } =20 #else @@ -1891,7 +1893,9 @@ static int __init gic_init_bases(void __iomem *dist_b= ase, gic_dist_init(); gic_cpu_init(); gic_smp_init(); - gic_cpu_pm_init(); + err =3D gic_cpu_pm_init(); + if (err) + goto out_set_handle; =20 if (gic_dist_supports_lpis()) { its_init(handle, &gic_data.rdists, gic_data.domain); @@ -1906,6 +1910,8 @@ static int __init gic_init_bases(void __iomem *dist_b= ase, =20 return 0; =20 +out_set_handle: + set_handle_irq(NULL); out_free: if (gic_data.domain) irq_domain_remove(gic_data.domain); --=20 2.34.1 From nobody Fri Sep 12 00:07:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA18CC05027 for ; Tue, 14 Feb 2023 23:34:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233013AbjBNXeu (ORCPT ); Tue, 14 Feb 2023 18:34:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232963AbjBNXel (ORCPT ); Tue, 14 Feb 2023 18:34:41 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7E2130EBD for ; Tue, 14 Feb 2023 15:34:38 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id w14-20020a17090a5e0e00b00233d3b9650eso340952pjf.4 for ; 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Tue, 14 Feb 2023 15:34:38 -0800 (PST) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id f12-20020a170902684c00b001963a178dfcsm9434801pln.244.2023.02.14.15.34.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 15:34:37 -0800 (PST) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Cc: Florian Fainelli , Thomas Gleixner , Marc Zyngier , Oliver Upton , linux-kernel@vger.kernel.org (open list:IRQCHIP DRIVERS), Sudeep Holla , Broadcom internal kernel review list Subject: [PATCH 3/3] irqchip/gic-v3: Save and restore distributor and re-distributor Date: Tue, 14 Feb 2023 15:34:26 -0800 Message-Id: <20230214233426.2994501-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214233426.2994501-1-f.fainelli@gmail.com> References: <20230214233426.2994501-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On platforms implementing Suspend to RAM where the GIC loses power, we are not properly saving and restoring the GIC distributor and re-distributor registers thus leading to the system resuming without any functional interrupts. Add support for saving and restoring the GIC distributor and re-distributor in order to properly suspend and resume with a functional system. Signed-off-by: Florian Fainelli --- drivers/irqchip/irq-gic-v3.c | 258 +++++++++++++++++++++++++++++ include/linux/irqchip/arm-gic-v3.h | 4 + 2 files changed, 262 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 48b0e9aba27c..4caab61268d0 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,25 @@ struct gic_chip_data { bool has_rss; unsigned int ppi_nr; struct partition_desc **ppi_descs; +#ifdef CONFIG_CPU_PM + u32 *saved_spi_conf; + u64 *saved_spi_target; + u32 *saved_spi_enable; + u32 *saved_spi_active; + + u32 *saved_espi_conf; + u64 *saved_espi_target; + u32 *saved_espi_enable; + u32 *saved_espi_active; + + u32 saved_ppi_conf; + u32 saved_ppi_enable; + u32 saved_ppi_active; + + u32 *saved_eppi_conf; + u32 *saved_eppi_enable; + u32 *saved_eppi_active; +#endif }; =20 static struct gic_chip_data gic_data __read_mostly; @@ -1371,6 +1391,143 @@ static int gic_retrigger(struct irq_data *data) } =20 #ifdef CONFIG_CPU_PM +static void gic_rdist_save(void) +{ + struct gic_chip_data *gic =3D &gic_data; + void __iomem *rbase =3D gic_data_rdist_sgi_base(); + unsigned int i; + + gic->saved_ppi_conf =3D readl_relaxed(rbase + GICR_ICFGR0 + 4); + gic->saved_ppi_enable =3D readl_relaxed(rbase + GICR_ISENABLER0); + gic->saved_ppi_active =3D readl_relaxed(rbase + GICR_ICACTIVER0); + + for (i =3D 0; i < DIV_ROUND_UP(gic->ppi_nr - 16, 32); i++) { + gic->saved_eppi_conf[i] =3D + readl_relaxed(rbase + GICR_ICFGRnE + i * 4); + gic->saved_eppi_enable[i] =3D + readl_relaxed(rbase + GICR_ISENABLERnE + i * 4); + gic->saved_eppi_active[i] =3D + readl_relaxed(rbase + GICR_ICACTIVERnE + i * 4); + } +} + +static void gic_dist_save(void) +{ + struct gic_chip_data *gic =3D &gic_data; + void __iomem *base =3D gic_data.dist_base; + unsigned int i; + + /* Save the SPIs first */ + for (i =3D 2; i < DIV_ROUND_UP(GIC_LINE_NR, 16); i++) + gic->saved_spi_conf[i] =3D + readl_relaxed(base + GICD_ICFGR + i * 4); + + for (i =3D 32; i < GIC_LINE_NR; i++) + gic->saved_spi_target[i] =3D + readq_relaxed(base + GICD_IROUTER + i * 8); + + for (i =3D 1; i < DIV_ROUND_UP(GIC_LINE_NR, 32); i++) { + gic->saved_spi_enable[i] =3D + readl_relaxed(base + GICD_ISENABLER + i * 4); + gic->saved_spi_active[i] =3D + readl_relaxed(base + GICD_ISACTIVER + i * 4); + } + + /* Save the EPIs next */ + for (i =3D 0; i < DIV_ROUND_UP(GIC_ESPI_NR, 16); i++) + gic->saved_espi_conf[i] =3D + readl_relaxed(base + GICD_ICFGRnE + i * 4); + + for (i =3D 0; i < GIC_ESPI_NR; i++) + gic->saved_espi_target[i] =3D + readq_relaxed(base + GICD_IROUTERnE + i * 8); + + for (i =3D 0; i < DIV_ROUND_UP(GIC_ESPI_NR, 32); i++) { + gic->saved_espi_enable[i] =3D + readl_relaxed(base + GICD_ISENABLERnE + i * 4); + gic->saved_espi_active[i] =3D + readl_relaxed(base + GICD_ISACTIVERnE + i * 4); + } +} + +static void gic_rdist_restore(void) +{ + struct gic_chip_data *gic =3D &gic_data; + void __iomem *rbase =3D gic_data_rdist_sgi_base(); + unsigned int i; + + writel_relaxed(gic->saved_ppi_conf, rbase + GICR_ICFGR0 + 4); + writel_relaxed(gic->saved_ppi_enable, rbase + GICR_ISENABLER0); + writel_relaxed(gic->saved_ppi_active, rbase + GICR_ICACTIVER0); + + for (i =3D 0; i < DIV_ROUND_UP(gic->ppi_nr - 16, 32); i++) { + writel_relaxed(gic->saved_eppi_conf[i], + rbase + GICR_ICFGRnE + i * 4); + writel_relaxed(gic->saved_eppi_enable[i], + rbase + GICR_ISENABLERnE + i * 4); + writel_relaxed(gic->saved_eppi_active[i], + rbase + GICR_ICACTIVERnE + i * 4); + } +} + +static void gic_dist_restore(void) +{ + struct gic_chip_data *gic =3D &gic_data; + void __iomem *base =3D gic_data.dist_base; + unsigned int i; + + /* Ensure distributor is disabled */ + writel_relaxed(0, base + GICD_CTLR); + gic_dist_wait_for_rwp(); + + /* Configure SPIs as non-secure Group-1. */ + for (i =3D 32; i < GIC_LINE_NR; i +=3D 32) + writel_relaxed(~0, base + GICD_IGROUPR + i / 8); + + /* Restore the SPIs */ + for (i =3D 2; i < DIV_ROUND_UP(GIC_LINE_NR, 16); i++) + writel_relaxed(gic->saved_spi_conf[i], + base + GICD_ICFGR + i * 4); + + for (i =3D 32; i < GIC_LINE_NR; i++) + writel_relaxed(gic->saved_spi_target[i], + base + GICD_IROUTER + i * 8); + + for (i =3D 1; i < DIV_ROUND_UP(GIC_LINE_NR, 32); i++) { + writel_relaxed(gic->saved_spi_enable[i], + base + GICD_ISENABLER + i * 4); + writel_relaxed(gic->saved_spi_active[i], + base + GICD_ISACTIVER + i * 4); + } + + /* Configure ESPIs as non-secure Group-1. */ + for (i =3D 0; i < GIC_ESPI_NR; i +=3D 32) + writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8); + + /* Restore the ESPIs */ + for (i =3D 0; i < DIV_ROUND_UP(GIC_ESPI_NR, 16); i++) + writel_relaxed(gic->saved_espi_conf[i], + base + GICD_ICFGRnE + i * 4); + + for (i =3D 0; i < GIC_ESPI_NR; i++) + writeq_relaxed(gic->saved_espi_target[i], + base + GICD_IROUTERnE + i * 8); + + for (i =3D 0; i < DIV_ROUND_UP(GIC_ESPI_NR, 32); i++) { + writel_relaxed(gic->saved_espi_enable[i], + base + GICD_ISENABLERnE + i * 4); + writel_relaxed(gic->saved_espi_active[i], + base + GICD_ISACTIVERnE + i * 4); + } + + for (i =3D 0; i < GIC_ESPI_NR; i +=3D 4) + writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i); + + /* Enable distributor with ARE, Group1 */ + writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE= _G1, + base + GICD_CTLR); +} + static int gic_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v) { @@ -1380,12 +1537,20 @@ static int gic_cpu_pm_notifier(struct notifier_bloc= k *self, gic_write_grpen1(0); gic_enable_redist(false); } + gic_rdist_save(); + break; + case CPU_CLUSTER_PM_ENTER: + gic_dist_save(); break; case CPU_PM_EXIT: + gic_rdist_restore(); if (gic_dist_security_disabled()) gic_enable_redist(true); gic_cpu_sys_reg_init(); break; + case CPU_CLUSTER_PM_EXIT: + gic_dist_restore(); + break; } =20 return NOTIFY_OK; @@ -1397,9 +1562,102 @@ static struct notifier_block gic_cpu_pm_notifier_bl= ock =3D { =20 static int gic_cpu_pm_init(void) { + struct gic_chip_data *gic =3D &gic_data; + unsigned int spi_size =3D DIV_ROUND_UP(GIC_LINE_NR, 32); + unsigned int espi_size =3D DIV_ROUND_UP(GIC_ESPI_NR, 32); + unsigned int eppi_size =3D DIV_ROUND_UP(gic->ppi_nr - 16, 32); + + gic->saved_spi_conf =3D kcalloc(DIV_ROUND_UP(GIC_LINE_NR, 16), + sizeof(*gic->saved_spi_conf), + GFP_KERNEL); + if (WARN_ON(!gic->saved_spi_conf)) + return -ENOMEM; + + gic->saved_spi_target =3D kcalloc(GIC_LINE_NR, + sizeof(*gic->saved_spi_target), + GFP_KERNEL); + if (WARN_ON(!gic->saved_spi_target)) + goto out_free_spi_conf; + + gic->saved_spi_enable =3D kcalloc(spi_size, + sizeof(*gic->saved_spi_enable), + GFP_KERNEL); + if (WARN_ON(!gic->saved_spi_enable)) + goto out_free_spi_target; + + gic->saved_spi_active =3D kcalloc(spi_size, + sizeof(*gic->saved_spi_active), + GFP_KERNEL); + if (WARN_ON(!gic->saved_spi_active)) + goto out_free_spi_enable; + + gic->saved_espi_conf =3D kcalloc(DIV_ROUND_UP(GIC_ESPI_NR, 16), + sizeof(*gic->saved_espi_conf), + GFP_KERNEL); + if (WARN_ON(!gic->saved_espi_conf)) + goto out_free_spi_active; + + gic->saved_espi_target =3D kcalloc(GIC_ESPI_NR, + sizeof(*gic->saved_espi_target), + GFP_KERNEL); + if (WARN_ON(!gic->saved_espi_target)) + goto out_free_espi_conf; + + gic->saved_espi_enable =3D kcalloc(espi_size, + sizeof(*gic->saved_espi_enable), + GFP_KERNEL); + if (WARN_ON(!gic->saved_espi_enable)) + goto out_free_espi_target; + + gic->saved_espi_active =3D kcalloc(espi_size, + sizeof(*gic->saved_espi_active), + GFP_KERNEL); + if (WARN_ON(!gic->saved_espi_active)) + goto out_free_espi_enable; + + gic->saved_eppi_conf =3D kcalloc(DIV_ROUND_UP(gic->ppi_nr - 16, 16), + sizeof(*gic->saved_eppi_conf), + GFP_KERNEL); + if (WARN_ON(!gic->saved_eppi_conf)) + goto out_free_espi_active; + + gic->saved_eppi_enable =3D kcalloc(eppi_size, + sizeof(*gic->saved_eppi_enable), + GFP_KERNEL); + if (WARN_ON(!gic->saved_eppi_enable)) + goto out_free_eppi_conf; + + gic->saved_eppi_active =3D kcalloc(eppi_size, + sizeof(*gic->saved_eppi_active), + GFP_KERNEL); + if (WARN_ON(!gic->saved_eppi_active)) + goto out_free_eppi_enable; + cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); =20 return 0; + +out_free_eppi_enable: + kfree(gic->saved_eppi_enable); +out_free_eppi_conf: + kfree(gic->saved_eppi_conf); +out_free_espi_active: + kfree(gic->saved_espi_active); +out_free_espi_enable: + kfree(gic->saved_espi_enable); +out_free_espi_target: + kfree(gic->saved_espi_target); +out_free_espi_conf: + kfree(gic->saved_espi_conf); +out_free_spi_active: + kfree(gic->saved_spi_active); +out_free_spi_enable: + kfree(gic->saved_spi_enable); +out_free_spi_target: + kfree(gic->saved_spi_target); +out_free_spi_conf: + kfree(gic->saved_spi_conf); + return -ENOMEM; } =20 #else diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm= -gic-v3.h index 728691365464..40483530cadd 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -229,13 +229,17 @@ */ #define GICR_IGROUPR0 GICD_IGROUPR #define GICR_ISENABLER0 GICD_ISENABLER +#define GICR_ISENABLERnE GICD_ISENABLERnE #define GICR_ICENABLER0 GICD_ICENABLER #define GICR_ISPENDR0 GICD_ISPENDR #define GICR_ICPENDR0 GICD_ICPENDR #define GICR_ISACTIVER0 GICD_ISACTIVER +#define GICR_ISACTIVERnE GICD_ISACTIVERnE #define GICR_ICACTIVER0 GICD_ICACTIVER +#define GICR_ICACTIVERnE GICD_ICACTIVERnE #define GICR_IPRIORITYR0 GICD_IPRIORITYR #define GICR_ICFGR0 GICD_ICFGR +#define GICR_ICFGRnE GICD_ICFGRnE #define GICR_IGRPMODR0 GICD_IGRPMODR #define GICR_NSACR GICD_NSACR =20 --=20 2.34.1