From nobody Sat Sep 21 04:38:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB547C61DA4 for ; Tue, 14 Feb 2023 13:43:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232987AbjBNNnq (ORCPT ); Tue, 14 Feb 2023 08:43:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232859AbjBNNnD (ORCPT ); Tue, 14 Feb 2023 08:43:03 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42E90279AF; Tue, 14 Feb 2023 05:42:30 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6A0526602177; Tue, 14 Feb 2023 13:42:07 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676382128; bh=6UXjo+wpXPIAVu5a6rEsnqKlrYh5JkgGqhWW1tR0aAg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L0E9VIYXS//DCjrSHz0kYWkCAGQBv/9M88M4GZ9TtCaGy+4UxpLgRvaQrj1b9yMNr QsJ7NeVmXzWgGDXDMWsOS9cGVkYzmwDd1qjz3uXgp0f8uw62dNe55WsoO+8eXTROmw 1ZBpVMBRdGxKGQLgigCcf5bpFoEQDe4F5menno7AROpWREtDMg4IK3ZK/xGJE4v8M/ Z4h8T9G4Hdi4pTYgzDYCSgZ68/CtWAYnkOkknX4YATU6JT2mzbdw8bin1c/d/ix5R6 oBiuA6MW+7MEh52sE55AfHkxOOQ7Aw+g+5NCCISav4RSVTfJuhKOKla2vUbX66hnyu FnqXqqdhJ4K8A== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 20/47] clk: mediatek: mt8183: Convert all remaining clocks to common probe Date: Tue, 14 Feb 2023 14:41:00 +0100 Message-Id: <20230214134127.59273-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214134127.59273-1-angelogioacchino.delregno@collabora.com> References: <20230214134127.59273-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch to mtk_clk_simple_{probe,remove}() for infracfg and topckgen clocks on MT8183 to allow full module build for clock drivers. Differently from other MediaTek clock drivers, it was necessary to change the name of the `clk13m` clock, as that is already declared in the SoC's devicetree as a "fixed-factor-clock" (with the same name) and redeclaring it here would obviously fail to register the entire clock controller; this clock wasn't dropped only to retain compatibility with older devicetrees As a note, the `clk13m` clock is not mentioned in any parent names array(s) as the correct one (csw_f26m_d2) is already used in place of that. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8183.c | 166 ++++++------------------------ 1 file changed, 34 insertions(+), 132 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 9da193d7782d..02176ee97cd2 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -25,11 +25,14 @@ static const struct mtk_fixed_clk top_fixed_clks[] =3D { FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), }; =20 -static const struct mtk_fixed_factor top_early_divs[] =3D { - FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), -}; - +/* + * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M + * valid, but renamed from "clk13m" (defined as fixed clock in the new + * devicetrees) to "clk26m_d2", satisfying the older clock assignments. + * This means that on new devicetrees "clk26m_d2" is unused. + */ static const struct mtk_fixed_factor top_divs[] =3D { + FACTOR(CLK_TOP_CLK13M, "clk26m_d2", "clk26m", 1, 2), FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0), FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0), @@ -803,26 +806,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(infra_rst_ofs), }; =20 -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt8183_top_init_early(struct device_node *node) -{ - int i; - - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - for (i =3D 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); -} - -CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", - clk_mt8183_top_init_early); - /* Register mux notifier for MFG mux */ static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) { @@ -845,134 +828,53 @@ static int clk_mt8183_reg_mfg_mux_notifier(struct de= vice *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } =20 -static int clk_mt8183_top_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct device_node *node =3D pdev->dev.of_node; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - - mtk_clk_register_muxes(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), node, - &mt8183_clk_lock, top_clk_data); - - mtk_clk_register_composites(&pdev->dev, top_aud_comp, - ARRAY_SIZE(top_aud_comp), base, - &mt8183_clk_lock, top_clk_data); - - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), top_clk_data); - - ret =3D clk_mt8183_reg_mfg_mux_notifier(&pdev->dev, - top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); - if (ret) - return ret; - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - top_clk_data); -} - -static int clk_mt8183_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); - - mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt8183_clk_lock, clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static const struct of_device_id of_match_clk_mt8183[] =3D { - { - .compatible =3D "mediatek,mt8183-topckgen", - .data =3D clk_mt8183_top_probe, - }, { - .compatible =3D "mediatek,mt8183-mcucfg", - .data =3D clk_mt8183_mcu_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt8183_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe =3D of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r =3D clk_probe(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static const struct mtk_clk_desc infra_desc =3D { .clks =3D infra_clks, .num_clks =3D ARRAY_SIZE(infra_clks), .rst_desc =3D &clk_rst_desc, }; =20 +static const struct mtk_clk_desc mcu_desc =3D { + .composite_clks =3D mcu_muxes, + .num_composite_clks =3D ARRAY_SIZE(mcu_muxes), + .clk_lock =3D &mt8183_clk_lock, +}; + static const struct mtk_clk_desc peri_desc =3D { .clks =3D peri_clks, .num_clks =3D ARRAY_SIZE(peri_clks), }; =20 -static const struct of_device_id of_match_clk_mt8183_simple[] =3D { +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_muxes), + .composite_clks =3D top_aud_comp, + .num_composite_clks =3D ARRAY_SIZE(top_aud_comp), + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .clk_lock =3D &mt8183_clk_lock, + .clk_notifier_func =3D clk_mt8183_reg_mfg_mux_notifier, + .mfg_clk_idx =3D CLK_TOP_MUX_MFG, +}; + +static const struct of_device_id of_match_clk_mt8183[] =3D { { .compatible =3D "mediatek,mt8183-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt8183-mcucfg", .data =3D &mcu_desc }, { .compatible =3D "mediatek,mt8183-pericfg", .data =3D &peri_desc, }, + { .compatible =3D "mediatek,mt8183-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 -static struct platform_driver clk_mt8183_simple_drv =3D { +static struct platform_driver clk_mt8183_drv =3D { .probe =3D mtk_clk_simple_probe, .remove =3D mtk_clk_simple_remove, - .driver =3D { - .name =3D "clk-mt8183-simple", - .of_match_table =3D of_match_clk_mt8183_simple, - }, -}; - -static struct platform_driver clk_mt8183_drv =3D { - .probe =3D clk_mt8183_probe, .driver =3D { .name =3D "clk-mt8183", .of_match_table =3D of_match_clk_mt8183, }, }; - -static int __init clk_mt8183_init(void) -{ - int ret =3D platform_driver_register(&clk_mt8183_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt8183_simple_drv); -} - -arch_initcall(clk_mt8183_init); +module_platform_driver(clk_mt8183_drv) --=20 2.39.1