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Tue, 14 Feb 2023 03:55:59 -0800 From: Dipen Patel To: , , , , , , , , , CC: Dipen Patel Subject: [PATCH V2 1/6] MAINTAINERS: Add HTE/timestamp subsystem details Date: Tue, 14 Feb 2023 03:55:48 -0800 Message-ID: <20230214115553.10416-2-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214115553.10416-1-dipenp@nvidia.com> References: <20230214115553.10416-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT017:EE_|BY5PR12MB4180:EE_ X-MS-Office365-Filtering-Correlation-Id: e8151d54-2d6c-4475-eb73-08db0e827584 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UEAFDeODTnJBFAy5s87iIf2sZ6vZCw7fp/YExcwhbBWVACcF1ZbnA83JuCa5PufCOmwweyEV3eAPICsPUDign7MSywAZ0NC77hTY7E6q/yOfNJLQUv7kKDbgv/5uKkhZI5UkxoQ6G5GbTx0pKoMpcfgRywnS0FBlHn1+mltjsQ1ggSBM2OCiKC1CoOHeBKjIoTaDB5zbiEjBmi28cFVzTx999O1P7m7Da9gpgpOpDwQMStrgVnebESYmjzp3VqQMGl3fa23YTKBATRQiOMeNBRPCY1Tui+PZP/aK2OfcYaeoC2EMFHbo7eeYq9keuMKiIhahDkSmjMupg5zJkN4U6lvIXYLp8L6eas7GXDwct/GcSegayLmMB+VvUSnY+17qe0YTASmjav337+xpMIO8XKPaeKBrjxF8xxhpowL1lpe4Pnih28ubvZOBKElCvZ7fdw4cmc1JmD7yNSnpy5kBqATa32xUkUZ74objrokRw1MWly3OgrR7n6esWGqxEtkiub/B+Zwn58Jn8zbcNyIp1wq4G5qlc9bupUSkQcGdnXCu3k6aX+ZEKPaEKsB20xdZ6e14QytPF08LKVApd01tVraJoZjIv96bVW9BFOumhFqJOuFMNtt87s1fFLELaIblSdhYG/M8TGN4sATUHCIHIVK4W53qw04M45HtLDroq6yy1j5bE+/v4zmjFxuqffhlXdTH2FlatNIZU+r1Cfqs7irnwv1L7AWAj9R2WVhr++KWTynYr+64k/0/oIE+AMFlKQzo2rM/gkKqT1izhxrXqA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(376002)(136003)(346002)(39860400002)(451199018)(36840700001)(46966006)(4744005)(36860700001)(2906002)(82310400005)(86362001)(82740400003)(7636003)(336012)(47076005)(426003)(7696005)(966005)(186003)(36756003)(26005)(40480700001)(356005)(921005)(70206006)(316002)(41300700001)(6666004)(110136005)(8676002)(4326008)(1076003)(478600001)(107886003)(2616005)(8936002)(70586007)(5660300002)(83996005)(2101003);DIR:OUT;SFP:1101; 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Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415b..734c988a7f7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9533,6 +9533,9 @@ F: drivers/input/touchscreen/htcpen.c =20 HTE SUBSYSTEM M: Dipen Patel +L: timestamp@lists.linux.dev +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.= git +Q: https://patchwork.kernel.org/project/timestamp/list/ S: Maintained F: Documentation/devicetree/bindings/timestamp/ F: Documentation/driver-api/hte/ --=20 2.17.1 From nobody Fri Sep 12 02:08:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF691C05027 for ; Tue, 14 Feb 2023 11:56:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232460AbjBNL4Y (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 11:56:08.9273 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bec962f8-5d9b-4e3b-705d-08db0e8275f6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8323 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Tegra234 AON GPIO instance and LIC IRQ support HTE. For the GPIO HTE support, it requires to add mapping between GPIO and HTE framework. Signed-off-by: Dipen Patel --- v2: Changed how gpio_chip could be aquired for the mapping drivers/hte/hte-tegra194-test.c | 2 +- drivers/hte/hte-tegra194.c | 153 ++++++++++++++++++++++++++++---- 2 files changed, 139 insertions(+), 16 deletions(-) diff --git a/drivers/hte/hte-tegra194-test.c b/drivers/hte/hte-tegra194-tes= t.c index 5d776a185bd6..d79c28a80517 100644 --- a/drivers/hte/hte-tegra194-test.c +++ b/drivers/hte/hte-tegra194-test.c @@ -16,7 +16,7 @@ #include =20 /* - * This sample HTE GPIO test driver demonstrates HTE API usage by enabling + * This sample HTE test driver demonstrates HTE API usage by enabling * hardware timestamp on gpio_in and specified LIC IRQ lines. * * Note: gpio_out and gpio_in need to be shorted externally in order for t= his diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 49a27af22742..7f0d6e7efd34 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -62,6 +62,10 @@ #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 =20 #define HTE_TECTRL 0x0 #define HTE_TETSCH 0x4 @@ -114,6 +118,7 @@ struct tegra_hte_line_data { =20 struct tegra_hte_data { enum tegra_hte_type type; + u32 slices; u32 map_sz; u32 sec_map_sz; const struct tegra_hte_line_mapped *map; @@ -220,18 +225,129 @@ static const struct tegra_hte_line_mapped tegra194_a= on_gpio_sec_map[] =3D { [39] =3D {NV_AON_SLICE_INVALID, 0}, }; =20 -static const struct tegra_hte_data aon_hte =3D { +static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] =3D { + /* gpio, slice, bit_index */ + /* AA port */ + [0] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + /* CC port */ + [12] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [13] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [14] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [15] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [16] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [17] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [18] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [19] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [20] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [21] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [22] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* EE port */ + [23] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [24] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [25] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [26] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [27] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [28] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [29] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [30] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [31] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] =3D { + /* gpio, slice, bit_index */ + /* AA port */ + [0] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + [12] =3D {NV_AON_SLICE_INVALID, 0}, + [13] =3D {NV_AON_SLICE_INVALID, 0}, + [14] =3D {NV_AON_SLICE_INVALID, 0}, + [15] =3D {NV_AON_SLICE_INVALID, 0}, + /* CC port */ + [16] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [17] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [18] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [19] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [20] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [21] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [22] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [23] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [24] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [25] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [26] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + [27] =3D {NV_AON_SLICE_INVALID, 0}, + [28] =3D {NV_AON_SLICE_INVALID, 0}, + [29] =3D {NV_AON_SLICE_INVALID, 0}, + [30] =3D {NV_AON_SLICE_INVALID, 0}, + [31] =3D {NV_AON_SLICE_INVALID, 0}, + /* EE port */ + [32] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [33] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [34] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [35] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [36] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [37] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [38] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [39] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [40] =3D {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_data t194_aon_hte =3D { .map_sz =3D ARRAY_SIZE(tegra194_aon_gpio_map), .map =3D tegra194_aon_gpio_map, .sec_map_sz =3D ARRAY_SIZE(tegra194_aon_gpio_sec_map), .sec_map =3D tegra194_aon_gpio_sec_map, .type =3D HTE_TEGRA_TYPE_GPIO, + .slices =3D 3, }; =20 -static const struct tegra_hte_data lic_hte =3D { +static const struct tegra_hte_data t234_aon_hte =3D { + .map_sz =3D ARRAY_SIZE(tegra234_aon_gpio_map), + .map =3D tegra234_aon_gpio_map, + .sec_map_sz =3D ARRAY_SIZE(tegra234_aon_gpio_sec_map), + .sec_map =3D tegra234_aon_gpio_sec_map, + .type =3D HTE_TEGRA_TYPE_GPIO, + .slices =3D 3, +}; + +static const struct tegra_hte_data t194_lic_hte =3D { .map_sz =3D 0, .map =3D NULL, .type =3D HTE_TEGRA_TYPE_LIC, + .slices =3D 11, +}; + +static const struct tegra_hte_data t234_lic_hte =3D { + .map_sz =3D 0, + .map =3D NULL, + .type =3D HTE_TEGRA_TYPE_LIC, + .slices =3D 17, }; =20 static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) @@ -534,8 +650,10 @@ static bool tegra_hte_match_from_linedata(const struct= hte_chip *chip, } =20 static const struct of_device_id tegra_hte_of_match[] =3D { - { .compatible =3D "nvidia,tegra194-gte-lic", .data =3D &lic_hte}, - { .compatible =3D "nvidia,tegra194-gte-aon", .data =3D &aon_hte}, + { .compatible =3D "nvidia,tegra194-gte-lic", .data =3D &t194_lic_hte}, + { .compatible =3D "nvidia,tegra194-gte-aon", .data =3D &t194_aon_hte}, + { .compatible =3D "nvidia,tegra234-gte-lic", .data =3D &t234_lic_hte}, + { .compatible =3D "nvidia,tegra234-gte-aon", .data =3D &t234_aon_hte}, { } }; MODULE_DEVICE_TABLE(of, tegra_hte_of_match); @@ -556,9 +674,9 @@ static void tegra_gte_disable(void *data) tegra_hte_writel(gs, HTE_TECTRL, 0); } =20 -static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) +static int tegra_get_gpiochip_from_of_node(struct gpio_chip *chip, void *d= ata) { - return !strcmp(chip->label, data); + return chip->of_node =3D=3D data; } =20 static int tegra_hte_probe(struct platform_device *pdev) @@ -569,16 +687,10 @@ static int tegra_hte_probe(struct platform_device *pd= ev) struct device *dev; struct tegra_hte_soc *hte_dev; struct hte_chip *gc; + struct device_node *gpio_ctrl; =20 dev =3D &pdev->dev; =20 - ret =3D of_property_read_u32(dev->of_node, "nvidia,slices", &slices); - if (ret !=3D 0) { - dev_err(dev, "Could not read slices\n"); - return -EINVAL; - } - nlines =3D slices << 5; - hte_dev =3D devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); if (!hte_dev) return -ENOMEM; @@ -590,6 +702,9 @@ static int tegra_hte_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, hte_dev); hte_dev->prov_data =3D of_device_get_match_data(&pdev->dev); =20 + slices =3D hte_dev->prov_data->slices; + nlines =3D slices << 5; + hte_dev->regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hte_dev->regs)) return PTR_ERR(hte_dev->regs); @@ -635,8 +750,16 @@ static int tegra_hte_probe(struct platform_device *pde= v) =20 gc->match_from_linedata =3D tegra_hte_match_from_linedata; =20 - hte_dev->c =3D gpiochip_find("tegra194-gpio-aon", - tegra_get_gpiochip_from_name); + gpio_ctrl =3D of_parse_phandle(dev->of_node, + "nvidia,gpio-controller", 0); + if (!gpio_ctrl) { + dev_err(dev, "gpio controller node not found\n"); + return -ENODEV; + } + + hte_dev->c =3D gpiochip_find(gpio_ctrl, + tegra_get_gpiochip_from_of_node); + of_node_put(gpio_ctrl); if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, "wait for gpio controller\n"); --=20 2.17.1 From nobody Fri Sep 12 02:08:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C148C05027 for ; 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Tue, 14 Feb 2023 03:56:00 -0800 From: Dipen Patel To: , , , , , , , , , CC: Dipen Patel Subject: [PATCH V2 3/6] gpio: tegra186: Add Tegra234 hte support Date: Tue, 14 Feb 2023 03:55:50 -0800 Message-ID: <20230214115553.10416-4-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214115553.10416-1-dipenp@nvidia.com> References: <20230214115553.10416-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT104:EE_|MN0PR12MB6078:EE_ X-MS-Office365-Filtering-Correlation-Id: fcf88f89-4cac-4d94-c66a-08db0e827699 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yShKT+axflnAwJPVpybzSsKiTFB0rTmZRo5aXdlL2eW0xBEDa1MklGJY8qCV0JtDdfsgB8UfbVL0wDECHh0qU3xgA7w3rE9jcFmgnyswOXLzFgwuKRzJTVprwVZ9IS5udO48keGWpj4ueMbC2mjUcTIGWKrcpQktS2pe23K/GQ2mi2q0C4zv1GTVEyFg5wD9+zHfJHMVm9sxmz6+axGrDB86ZjjrmXiyCv483GEEtOEruQqDRKksZrGRE2VBraR395cWw8ndThOr0y7vmqcBuU6mMvBi8gIpFeXadocxqVGUoPm6Gp83cLkJW/2NT/sTJOQYJvd/J36HfvsP5999gsR8KI3VuB3ZflqQL4vuF8ZzL1UlxqNbTPryoM1JOh4TwuRq7QbXOQaGYqhq7uK4+zWmz6F2QQtDCG1XZAzzqJyLN45Q6kIDDVxwx3fem5scpjySnyFcU7Tid/plwaeECB8yN144ptY6ZPu0/kg1DebZLmb8KBWE0RU9hT+dsPSX1FO7D03ImndJC2xmyg7EJju1NRJFHUFZoqrMTSx6H5y9i9k7SyDj6fWM7pWi7AHqLjBY+lV9YXQT5n+7Zg03kF5Zjg/nOlZO1N7XbvI1FaTebk9yhoDFogWF9BZvQ4CT5ayEHQ4f3nrBbJNaBeXdvPtDuOKeoqC19tqRa9nSeA/2/9+tuU8EbKeTN7eTYxlkh3UKqEqAuIh2Q0w5a39H8ofvOudtU0kBa7jyRAwE6je/npuey3ucCG+VOhIT4fKdY08KECf9ZLXh/JjFTjieLQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199018)(36840700001)(46966006)(40470700004)(40460700003)(921005)(356005)(86362001)(36756003)(70206006)(8676002)(70586007)(478600001)(4326008)(7696005)(6666004)(82310400005)(110136005)(41300700001)(8936002)(2906002)(40480700001)(36860700001)(4744005)(83380400001)(7636003)(5660300002)(186003)(26005)(316002)(47076005)(1076003)(426003)(82740400003)(2616005)(107886003)(336012)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 11:56:10.0133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fcf88f89-4cac-4d94-c66a-08db0e827699 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT104.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6078 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To enable timestamp support for the Tegra234, has_gte variable needs to be set true. Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- drivers/gpio/gpio-tegra186.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index fdc5bdcd5638..58346c3ff18d 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1137,6 +1137,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = =3D { .name =3D "tegra234-gpio-aon", .instance =3D 1, .num_irqs_per_bank =3D 8, + .has_gte =3D true, }; =20 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ --=20 2.17.1 From nobody Fri Sep 12 02:08:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 049B7C05027 for ; Tue, 14 Feb 2023 11:56:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232658AbjBNL41 (ORCPT ); Tue, 14 Feb 2023 06:56:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232288AbjBNL4N (ORCPT ); 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Tue, 14 Feb 2023 03:56:01 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 03:56:01 -0800 Received: from dipenp.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Tue, 14 Feb 2023 03:56:01 -0800 From: Dipen Patel To: , , , , , , , , , CC: Dipen Patel Subject: [PATCH V2 4/6] dt-bindings: timestamp: Add Tegra234 support Date: Tue, 14 Feb 2023 03:55:51 -0800 Message-ID: <20230214115553.10416-5-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214115553.10416-1-dipenp@nvidia.com> References: <20230214115553.10416-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT060:EE_|CH3PR12MB8725:EE_ X-MS-Office365-Filtering-Correlation-Id: af894e40-d107-416d-e17c-08db0e82768e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 11:56:09.9107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af894e40-d107-416d-e17c-08db0e82768e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8725 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Added timestamp provider support for the Tegra234 in devicetree bindings. Signed-off-by: Dipen Patel --- v2: - Removed nvidia,slices property - Added nvidia,gpio-controller based on review comments from Thierry, this will help simplify the hte provider driver. .../timestamp/nvidia,tegra194-hte.yaml | 30 ++++++++++++------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-ht= e.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.ya= ml index c31e207d1652..d0f4ed75baee 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Tegra194 on chip generic hardware timestamping engine (HTE) +title: Tegra on chip generic hardware timestamping engine (HTE) provider =20 maintainers: - Dipen Patel @@ -23,6 +23,8 @@ properties: enum: - nvidia,tegra194-gte-aon - nvidia,tegra194-gte-lic + - nvidia,tegra234-gte-aon + - nvidia,tegra234-gte-lic =20 reg: maxItems: 1 @@ -38,14 +40,11 @@ properties: minimum: 1 maximum: 256 =20 - nvidia,slices: - $ref: /schemas/types.yaml#/definitions/uint32 + nvidia,gpio-controller: + $ref: /schemas/types.yaml#/definitions/phandle description: - HTE lines are arranged in 32 bit slice where each bit represents dif= ferent - line/signal that it can enable/configure for the timestamp. It is u32 - property and depends on the HTE instance in the chip. The value 3 is= for - GPIO GTE and 11 for IRQ GTE. - enum: [3, 11] + The phandle to AON gpio controller instance. This is required to han= dle + namespace conversion between GPIO and GTE. =20 '#timestamp-cells': description: @@ -55,11 +54,21 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 =20 +if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-aon + - nvidia,tegra234-gte-aon +then: + required: + - nvidia,gpio-controller + required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" =20 additionalProperties: false @@ -71,7 +80,7 @@ examples: reg =3D <0xc1e0000 0x10000>; interrupts =3D <0 13 0x4>; nvidia,int-threshold =3D <1>; - nvidia,slices =3D <3>; + nvidia,gpio-controller =3D <&gpio_aon>; #timestamp-cells =3D <1>; }; =20 @@ -81,7 +90,6 @@ examples: reg =3D <0x3aa0000 0x10000>; interrupts =3D <0 11 0x4>; nvidia,int-threshold =3D <1>; - nvidia,slices =3D <11>; #timestamp-cells =3D <1>; }; =20 --=20 2.17.1 From nobody Fri Sep 12 02:08:08 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19212C61DA4 for ; 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Tue, 14 Feb 2023 03:56:01 -0800 From: Dipen Patel To: , , , , , , , , , CC: Dipen Patel Subject: [PATCH V2 5/6] hte: Re-phrase tegra API document Date: Tue, 14 Feb 2023 03:55:52 -0800 Message-ID: <20230214115553.10416-6-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214115553.10416-1-dipenp@nvidia.com> References: <20230214115553.10416-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT105:EE_|DM4PR12MB5168:EE_ X-MS-Office365-Filtering-Correlation-Id: 14095c0c-91a8-475c-42fe-08db0e827795 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: l89zkOHBunfXkZwSAgs/a/iQURIPauYvpbBIusexhwcZUbZShPIcLTKrTdgpZxhSvhrvDYZOvAvxPYvXv+0na6nboBVJD0fqqDlLyYji0sHF7M6pv6Q3Kp9kvsOVkwucZc+QOPIP14NqCDz8ASBHZZJB+ysCaZl/Z4qL0fWgJKotwkZYdWNtCnRWsiz18WEEuOFX+R59XrVrq4NefqxL4lEt0omqMn5VcRz4f+nvoteZS3hTsYZkr76y0vwxClTKZCIYgpIOWcje274a7iUwJ9+6tqG+2fafNwAPKmx+SeTQoAZEl+dQvAXmONEBDSCcjGfuaOpLDbNIAg2ojojg/6vTPAtuqcZg2IuiTixkpITWgxB0ObaXkMLt44KDjyX4JkQTwILZq71YjXOIt5ActCTmNGmgnkneuMZTDQZUSOKjpFz5zCgqtas9CWLCvrGY4mZQtj4PqKM9MZT7P/4ykcRGy6T3m0unLsz2DrUzRX5MWaVy5SDI2MSNrU8Dz2qdNAtxAURScIMVIPqmovkZwj680sSzzxnbR5o5t5hjKafQS5AGQPiDZtjXDY+oVntiyyeehfr5cD1DcJM+slk5pAUrlKYVy6giCeYBOTkCakPKfwVcTdXg7ee7CSs7HE/aj9E7r8MGBL8na8QJM97d36jDztjf+frJawO0cufLDH5chn5F03SXwG0N+qcfJm1d6/GljZgvzugfX/KjB/ByUaTPWnj2ptQ4RJLnP4JfXklRXP1Vir7GJz6m6BQKX0Dm X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(346002)(396003)(39860400002)(451199018)(40470700004)(36840700001)(46966006)(26005)(186003)(2616005)(478600001)(41300700001)(40480700001)(107886003)(6666004)(336012)(7696005)(1076003)(110136005)(316002)(83380400001)(4326008)(356005)(8676002)(40460700003)(70206006)(921005)(8936002)(70586007)(7636003)(36756003)(426003)(47076005)(82740400003)(86362001)(5660300002)(2906002)(36860700001)(82310400005)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 11:56:11.6459 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14095c0c-91a8-475c-42fe-08db0e827795 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5168 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make Tegra194 API document generic to make it applicable for current and future tegra hte providers. Signed-off-by: Dipen Patel --- Documentation/driver-api/hte/tegra194-hte.rst | 33 +++++++++---------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/Documentation/driver-api/hte/tegra194-hte.rst b/Documentation/= driver-api/hte/tegra194-hte.rst index f2d617265546..85e654772782 100644 --- a/Documentation/driver-api/hte/tegra194-hte.rst +++ b/Documentation/driver-api/hte/tegra194-hte.rst @@ -5,25 +5,25 @@ HTE Kernel provider driver =20 Description ----------- -The Nvidia tegra194 HTE provider driver implements two GTE -(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC -(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the -timestamp from the system counter TSC which has 31.25MHz clock rate, and t= he -driver converts clock tick rate to nanoseconds before storing it as timest= amp -value. +The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engi= ne) +driver implements two GTE instances: 1) GPIO GTE and 2) LIC +(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp +from the system counter TSC which has 31.25MHz clock rate, and the driver +converts clock tick rate to nanoseconds before storing it as timestamp val= ue. =20 GPIO GTE -------- =20 This GTE instance timestamps GPIO in real time. For that to happen GPIO -needs to be configured as input. The always on (AON) GPIO controller insta= nce -supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPI= O GTE -and AON GPIO controller are tightly coupled as it requires very specific b= its -to be set in GPIO config register before GPIO GTE can be used, for that GP= IOLIB -adds two optional APIs as below. The GPIO GTE code supports both kernel -and userspace consumers. The kernel space consumers can directly talk to H= TE -subsystem while userspace consumers timestamp requests go through GPIOLIB = CDEV -framework to HTE subsystem. +needs to be configured as input. Only the always on (AON) GPIO controller +instance supports timestamping GPIOs in real time as it is tightly coupled= with +the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned +below. The GPIO GTE code supports both kernel and userspace consumers. The +kernel space consumers can directly talk to HTE subsystem while userspace +consumers timestamp requests go through GPIOLIB CDEV framework to HTE +subsystem. The hte devicetree binding described at +``Documentation/devicetree/bindings/timestamp`` provides an example of how= a +consumer can request an GPIO line. =20 See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns(). =20 @@ -34,9 +34,8 @@ returns the timestamp in nanoseconds. LIC (Legacy Interrupt Controller) IRQ GTE ----------------------------------------- =20 -This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ -lines which this instance can add timestamps to in real time. The hte -devicetree binding described at ``Documentation/devicetree/bindings/timest= amp`` +This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree +binding described at ``Documentation/devicetree/bindings/timestamp`` provides an example of how a consumer can request an IRQ line. Since it is= a one-to-one mapping with IRQ GTE provider, consumers can simply specify the= IRQ number that they are interested in. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 11:56:11.8168 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: deed0e13-8fde-46c9-bc6f-08db0e8277b1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7413 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add GTE nodes for the tegra234. Also modify AON GTE nodes for the tegra194 to remove nvidia,slice property and add nvidia,gpio-controller propertyto specify AON GPIO controller node so that GTE driver can do namespace conversion between GPIO lines provided by the gpiolib framework and hardware timestamping engine subsystem. Signed-off-by: Dipen Patel --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 3 +-- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index 4afcbd60e144..4c92850b1ec4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1363,7 +1363,6 @@ reg =3D <0x3aa0000 0x10000>; interrupts =3D ; nvidia,int-threshold =3D <1>; - nvidia,slices =3D <11>; #timestamp-cells =3D <1>; status =3D "okay"; }; @@ -1586,7 +1585,7 @@ reg =3D <0xc1e0000 0x10000>; interrupts =3D ; nvidia,int-threshold =3D <1>; - nvidia,slices =3D <3>; + nvidia,gpio-controller =3D <&gpio_aon>; #timestamp-cells =3D <1>; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index eaf05ee9acd1..4a87490c5fd4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1086,6 +1086,15 @@ clock-names =3D "fuse"; }; =20 + hte_lic: hardware-timestamp@3aa0000 { + compatible =3D "nvidia,tegra234-gte-lic"; + reg =3D <0x3aa0000 0x10000>; + interrupts =3D ; + nvidia,int-threshold =3D <1>; + #timestamp-cells =3D <1>; + status =3D "okay"; + }; + hsp_top0: hsp@3c00000 { compatible =3D "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg =3D <0x03c00000 0xa0000>; @@ -1603,6 +1612,16 @@ #mbox-cells =3D <2>; }; =20 + hte_aon: hardware-timestamp@c1e0000 { + compatible =3D "nvidia,tegra234-gte-aon"; + reg =3D <0xc1e0000 0x10000>; + interrupts =3D ; + nvidia,int-threshold =3D <1>; + nvidia,gpio-controller =3D <&gpio_aon>; + #timestamp-cells =3D <1>; + status =3D "okay"; + }; + gen2_i2c: i2c@c240000 { compatible =3D "nvidia,tegra194-i2c"; reg =3D <0xc240000 0x100>; --=20 2.17.1