From nobody Fri Sep 12 04:28:05 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26E7BC05027 for ; Tue, 14 Feb 2023 10:42:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231992AbjBNKm0 (ORCPT ); Tue, 14 Feb 2023 05:42:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232733AbjBNKlp (ORCPT ); Tue, 14 Feb 2023 05:41:45 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 352E9265B8; Tue, 14 Feb 2023 02:41:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1676371283; x=1707907283; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=agk284JXCde2I3EYUJysAECUhHtTiAFct0qFKTqHM1g=; b=LLKjl1t54greaOa5NVMgh5P2MGnm34LfPON4zy873TUN+qwnLce7ftw7 G5sDYa9t4QKX2tJhBlSFUtdisvbyRUNW7TRc5SC0lr7AFbD+7CzyFGlLn BdY0VkDkj74MHz+97LaoQkmFXL8Aoobhxg+z/dh+qY7rTRcjDVtcGQVQy KISVOo/dr4uc+lCXyAnLaWa7XOnn0woR/zaonmoyGqEKHYFtIghADfyzH NOYdsK0unkZut9EmoWdCm6I/H8WgPEQKRQVYG5c5uGlCvzuIvtmiSDQug 2hPuz84iEGrx8WIPtaMQy6muHB3yrx4owu3zzauemejIRthJRo0Mx1dFP Q==; X-IronPort-AV: E=Sophos;i="5.97,296,1669100400"; d="scan'208";a="200856784" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2023 03:41:19 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 14 Feb 2023 03:41:18 -0700 Received: from den-dk-m31857.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 14 Feb 2023 03:41:14 -0700 From: Steen Hegelund To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni CC: Steen Hegelund , , Randy Dunlap , "Casper Andersson" , Russell King , Wan Jiabing , "Nathan Huckleberry" , , , , "Steen Hegelund" , Daniel Machon , Horatiu Vultur , Lars Povlsen , Dan Carpenter , Michael Walle Subject: [PATCH net-next v2 06/10] net: microchip: sparx5: Add ES0 VCAP model and updated KUNIT VCAP model Date: Tue, 14 Feb 2023 11:40:45 +0100 Message-ID: <20230214104049.1553059-7-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214104049.1553059-1-steen.hegelund@microchip.com> References: <20230214104049.1553059-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This provides the VCAP model for the Sparx5 ES0 (Egress Stage 0) VCAP. This VCAP provides rewriting functionality in the egress path. Signed-off-by: Steen Hegelund --- .../microchip/sparx5/sparx5_vcap_ag_api.c | 385 +++++++++++++++++- .../net/ethernet/microchip/vcap/vcap_ag_api.h | 174 +++++++- .../microchip/vcap/vcap_api_debugfs_kunit.c | 4 +- .../microchip/vcap/vcap_model_kunit.c | 270 +++++++----- .../microchip/vcap/vcap_model_kunit.h | 10 +- 5 files changed, 721 insertions(+), 122 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c b/d= rivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c index 561001ee0516..556d6ea0acd1 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c @@ -3,8 +3,8 @@ * Microchip VCAP API */ =20 -/* This file is autogenerated by cml-utils 2023-01-17 16:55:38 +0100. - * Commit ID: cc027a9bd71002aebf074df5ad8584fe1545e05e +/* This file is autogenerated by cml-utils 2023-02-10 11:15:56 +0100. + * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada */ =20 #include @@ -1333,6 +1333,54 @@ static const struct vcap_field is2_ip_7tuple_keyfiel= d[] =3D { }, }; =20 +static const struct vcap_field es0_isdx_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_KF_IF_EGR_PORT_NO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 1, + .width =3D 7, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 8, + .width =3D 13, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 21, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 24, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 27, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 29, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 39, + .width =3D 12, + }, +}; + static const struct vcap_field es2_mac_etype_keyfield[] =3D { [VCAP_KF_TYPE] =3D { .type =3D VCAP_FIELD_U32, @@ -2283,6 +2331,14 @@ static const struct vcap_set is2_keyfield_set[] =3D { }, }; =20 +static const struct vcap_set es0_keyfield_set[] =3D { + [VCAP_KFS_ISDX] =3D { + .type_id =3D 0, + .sw_per_item =3D 1, + .sw_cnt =3D 1, + }, +}; + static const struct vcap_set es2_keyfield_set[] =3D { [VCAP_KFS_MAC_ETYPE] =3D { .type_id =3D 0, @@ -2331,6 +2387,10 @@ static const struct vcap_field *is2_keyfield_set_map= [] =3D { [VCAP_KFS_IP_7TUPLE] =3D is2_ip_7tuple_keyfield, }; =20 +static const struct vcap_field *es0_keyfield_set_map[] =3D { + [VCAP_KFS_ISDX] =3D es0_isdx_keyfield, +}; + static const struct vcap_field *es2_keyfield_set_map[] =3D { [VCAP_KFS_MAC_ETYPE] =3D es2_mac_etype_keyfield, [VCAP_KFS_ARP] =3D es2_arp_keyfield, @@ -2355,6 +2415,10 @@ static int is2_keyfield_set_map_size[] =3D { [VCAP_KFS_IP_7TUPLE] =3D ARRAY_SIZE(is2_ip_7tuple_keyfield), }; =20 +static int es0_keyfield_set_map_size[] =3D { + [VCAP_KFS_ISDX] =3D ARRAY_SIZE(es0_isdx_keyfield), +}; + static int es2_keyfield_set_map_size[] =3D { [VCAP_KFS_MAC_ETYPE] =3D ARRAY_SIZE(es2_mac_etype_keyfield), [VCAP_KFS_ARP] =3D ARRAY_SIZE(es2_arp_keyfield), @@ -2752,6 +2816,184 @@ static const struct vcap_field is2_base_type_action= field[] =3D { }, }; =20 +static const struct vcap_field es0_es0_actionfield[] =3D { + [VCAP_AF_PUSH_OUTER_TAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_AF_PUSH_INNER_TAG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_AF_TAG_A_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 3, + }, + [VCAP_AF_TAG_A_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 6, + .width =3D 2, + }, + [VCAP_AF_TAG_A_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 8, + .width =3D 3, + }, + [VCAP_AF_TAG_A_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 11, + .width =3D 3, + }, + [VCAP_AF_TAG_B_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 3, + }, + [VCAP_AF_TAG_B_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 2, + }, + [VCAP_AF_TAG_B_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 19, + .width =3D 3, + }, + [VCAP_AF_TAG_B_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 22, + .width =3D 3, + }, + [VCAP_AF_TAG_C_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 25, + .width =3D 3, + }, + [VCAP_AF_TAG_C_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 3, + }, + [VCAP_AF_TAG_C_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 31, + .width =3D 3, + }, + [VCAP_AF_VID_A_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 34, + .width =3D 12, + }, + [VCAP_AF_PCP_A_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 46, + .width =3D 3, + }, + [VCAP_AF_DEI_A_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 49, + .width =3D 1, + }, + [VCAP_AF_VID_B_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 50, + .width =3D 12, + }, + [VCAP_AF_PCP_B_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 62, + .width =3D 3, + }, + [VCAP_AF_DEI_B_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 65, + .width =3D 1, + }, + [VCAP_AF_VID_C_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 66, + .width =3D 12, + }, + [VCAP_AF_PCP_C_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 3, + }, + [VCAP_AF_DEI_C_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_AF_POP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 2, + }, + [VCAP_AF_UNTAG_VID_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_AF_PUSH_CUSTOMER_TAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 85, + .width =3D 2, + }, + [VCAP_AF_TAG_C_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 2, + }, + [VCAP_AF_DSCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 127, + .width =3D 3, + }, + [VCAP_AF_DSCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 130, + .width =3D 6, + }, + [VCAP_AF_ESDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 323, + .width =3D 13, + }, + [VCAP_AF_FWD_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 459, + .width =3D 2, + }, + [VCAP_AF_CPU_QU] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 461, + .width =3D 3, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 464, + .width =3D 2, + }, + [VCAP_AF_PIPELINE_ACT] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 466, + .width =3D 1, + }, + [VCAP_AF_SWAP_MACS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 475, + .width =3D 1, + }, + [VCAP_AF_LOOP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 476, + .width =3D 1, + }, +}; + static const struct vcap_field es2_base_type_actionfield[] =3D { [VCAP_AF_HIT_ME_ONCE] =3D { .type =3D VCAP_FIELD_BIT, @@ -2852,6 +3094,14 @@ static const struct vcap_set is2_actionfield_set[] = =3D { }, }; =20 +static const struct vcap_set es0_actionfield_set[] =3D { + [VCAP_AFS_ES0] =3D { + .type_id =3D -1, + .sw_per_item =3D 1, + .sw_cnt =3D 1, + }, +}; + static const struct vcap_set es2_actionfield_set[] =3D { [VCAP_AFS_BASE_TYPE] =3D { .type_id =3D -1, @@ -2871,6 +3121,10 @@ static const struct vcap_field *is2_actionfield_set_= map[] =3D { [VCAP_AFS_BASE_TYPE] =3D is2_base_type_actionfield, }; =20 +static const struct vcap_field *es0_actionfield_set_map[] =3D { + [VCAP_AFS_ES0] =3D es0_es0_actionfield, +}; + static const struct vcap_field *es2_actionfield_set_map[] =3D { [VCAP_AFS_BASE_TYPE] =3D es2_base_type_actionfield, }; @@ -2886,6 +3140,10 @@ static int is2_actionfield_set_map_size[] =3D { [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(is2_base_type_actionfield), }; =20 +static int es0_actionfield_set_map_size[] =3D { + [VCAP_AFS_ES0] =3D ARRAY_SIZE(es0_es0_actionfield), +}; + static int es2_actionfield_set_map_size[] =3D { [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(es2_base_type_actionfield), }; @@ -2990,10 +3248,35 @@ static const struct vcap_typegroup is0_x6_keyfield_= set_typegroups[] =3D { }; =20 static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 52, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 104, + .width =3D 2, + .value =3D 0, + }, {} }; =20 static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 52, + .width =3D 1, + .value =3D 0, + }, {} }; =20 @@ -3047,6 +3330,10 @@ static const struct vcap_typegroup is2_x1_keyfield_s= et_typegroups[] =3D { {} }; =20 +static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] =3D { + {} +}; + static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] =3D { { .offset =3D 0, @@ -3086,6 +3373,11 @@ static const struct vcap_typegroup es2_x6_keyfield_s= et_typegroups[] =3D { }; =20 static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 1, + .value =3D 1, + }, {} }; =20 @@ -3110,6 +3402,11 @@ static const struct vcap_typegroup *is2_keyfield_set= _typegroups[] =3D { [13] =3D NULL, }; =20 +static const struct vcap_typegroup *es0_keyfield_set_typegroups[] =3D { + [1] =3D es0_x1_keyfield_set_typegroups, + [2] =3D NULL, +}; + static const struct vcap_typegroup *es2_keyfield_set_typegroups[] =3D { [12] =3D es2_x12_keyfield_set_typegroups, [6] =3D es2_x6_keyfield_set_typegroups, @@ -3183,6 +3480,10 @@ static const struct vcap_typegroup is2_x1_actionfiel= d_set_typegroups[] =3D { {} }; =20 +static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] =3D= { + {} +}; + static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] =3D= { { .offset =3D 0, @@ -3219,6 +3520,11 @@ static const struct vcap_typegroup *is2_actionfield_= set_typegroups[] =3D { [13] =3D NULL, }; =20 +static const struct vcap_typegroup *es0_actionfield_set_typegroups[] =3D { + [1] =3D es0_x1_actionfield_set_typegroups, + [2] =3D NULL, +}; + static const struct vcap_typegroup *es2_actionfield_set_typegroups[] =3D { [3] =3D es2_x3_actionfield_set_typegroups, [1] =3D es2_x1_actionfield_set_typegroups, @@ -3229,18 +3535,24 @@ static const struct vcap_typegroup *es2_actionfield= _set_typegroups[] =3D { static const char * const vcap_keyfield_set_names[] =3D { [VCAP_KFS_NO_VALUE] =3D "(None)", [VCAP_KFS_ARP] =3D "VCAP_KFS_ARP", + [VCAP_KFS_ETAG] =3D "VCAP_KFS_ETAG", [VCAP_KFS_IP4_OTHER] =3D "VCAP_KFS_IP4_OTHER", [VCAP_KFS_IP4_TCP_UDP] =3D "VCAP_KFS_IP4_TCP_UDP", + [VCAP_KFS_IP4_VID] =3D "VCAP_KFS_IP4_VID", [VCAP_KFS_IP6_OTHER] =3D "VCAP_KFS_IP6_OTHER", [VCAP_KFS_IP6_STD] =3D "VCAP_KFS_IP6_STD", [VCAP_KFS_IP6_TCP_UDP] =3D "VCAP_KFS_IP6_TCP_UDP", + [VCAP_KFS_IP6_VID] =3D "VCAP_KFS_IP6_VID", [VCAP_KFS_IP_7TUPLE] =3D "VCAP_KFS_IP_7TUPLE", + [VCAP_KFS_ISDX] =3D "VCAP_KFS_ISDX", + [VCAP_KFS_LL_FULL] =3D "VCAP_KFS_LL_FULL", [VCAP_KFS_MAC_ETYPE] =3D "VCAP_KFS_MAC_ETYPE", [VCAP_KFS_MAC_LLC] =3D "VCAP_KFS_MAC_LLC", [VCAP_KFS_MAC_SNAP] =3D "VCAP_KFS_MAC_SNAP", [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D "VCAP_KFS_NORMAL_5TUPLE_IP4= ", [VCAP_KFS_NORMAL_7TUPLE] =3D "VCAP_KFS_NORMAL_7TUPLE", [VCAP_KFS_OAM] =3D "VCAP_KFS_OAM", + [VCAP_KFS_PURE_5TUPLE_IP4] =3D "VCAP_KFS_PURE_5TUPLE_IP4", [VCAP_KFS_SMAC_SIP4] =3D "VCAP_KFS_SMAC_SIP4", [VCAP_KFS_SMAC_SIP6] =3D "VCAP_KFS_SMAC_SIP6", }; @@ -3251,6 +3563,7 @@ static const char * const vcap_actionfield_set_names[= ] =3D { [VCAP_AFS_BASE_TYPE] =3D "VCAP_AFS_BASE_TYPE", [VCAP_AFS_CLASSIFICATION] =3D "VCAP_AFS_CLASSIFICATION", [VCAP_AFS_CLASS_REDUCED] =3D "VCAP_AFS_CLASS_REDUCED", + [VCAP_AFS_ES0] =3D "VCAP_AFS_ES0", [VCAP_AFS_FULL] =3D "VCAP_AFS_FULL", [VCAP_AFS_SMAC_SIP] =3D "VCAP_AFS_SMAC_SIP", }; @@ -3258,6 +3571,12 @@ static const char * const vcap_actionfield_set_names= [] =3D { /* Keyfield names */ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_NO_VALUE] =3D "(None)", + [VCAP_KF_8021BR_ECID_BASE] =3D "8021BR_ECID_BASE", + [VCAP_KF_8021BR_ECID_EXT] =3D "8021BR_ECID_EXT", + [VCAP_KF_8021BR_E_TAGGED] =3D "8021BR_E_TAGGED", + [VCAP_KF_8021BR_GRP] =3D "8021BR_GRP", + [VCAP_KF_8021BR_IGR_ECID_BASE] =3D "8021BR_IGR_ECID_BASE", + [VCAP_KF_8021BR_IGR_ECID_EXT] =3D "8021BR_IGR_ECID_EXT", [VCAP_KF_8021Q_DEI0] =3D "8021Q_DEI0", [VCAP_KF_8021Q_DEI1] =3D "8021Q_DEI1", [VCAP_KF_8021Q_DEI2] =3D "8021Q_DEI2", @@ -3266,6 +3585,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_8021Q_PCP1] =3D "8021Q_PCP1", [VCAP_KF_8021Q_PCP2] =3D "8021Q_PCP2", [VCAP_KF_8021Q_PCP_CLS] =3D "8021Q_PCP_CLS", + [VCAP_KF_8021Q_TPID] =3D "8021Q_TPID", [VCAP_KF_8021Q_TPID0] =3D "8021Q_TPID0", [VCAP_KF_8021Q_TPID1] =3D "8021Q_TPID1", [VCAP_KF_8021Q_TPID2] =3D "8021Q_TPID2", @@ -3275,6 +3595,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_8021Q_VID_CLS] =3D "8021Q_VID_CLS", [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D "8021Q_VLAN_TAGGED_IS", [VCAP_KF_8021Q_VLAN_TAGS] =3D "8021Q_VLAN_TAGS", + [VCAP_KF_ACL_GRP_ID] =3D "ACL_GRP_ID", [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D "ARP_ADDR_SPACE_OK_IS", [VCAP_KF_ARP_LEN_OK_IS] =3D "ARP_LEN_OK_IS", [VCAP_KF_ARP_OPCODE] =3D "ARP_OPCODE", @@ -3283,11 +3604,13 @@ static const char * const vcap_keyfield_names[] =3D= { [VCAP_KF_ARP_SENDER_MATCH_IS] =3D "ARP_SENDER_MATCH_IS", [VCAP_KF_ARP_TGT_MATCH_IS] =3D "ARP_TGT_MATCH_IS", [VCAP_KF_COSID_CLS] =3D "COSID_CLS", + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D "ES0_ISDX_KEY_ENA", [VCAP_KF_ETYPE] =3D "ETYPE", [VCAP_KF_ETYPE_LEN_IS] =3D "ETYPE_LEN_IS", [VCAP_KF_HOST_MATCH] =3D "HOST_MATCH", [VCAP_KF_IF_EGR_PORT_MASK] =3D "IF_EGR_PORT_MASK", [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D "IF_EGR_PORT_MASK_RNG", + [VCAP_KF_IF_EGR_PORT_NO] =3D "IF_EGR_PORT_NO", [VCAP_KF_IF_IGR_PORT] =3D "IF_IGR_PORT", [VCAP_KF_IF_IGR_PORT_MASK] =3D "IF_IGR_PORT_MASK", [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D "IF_IGR_PORT_MASK_L3", @@ -3348,6 +3671,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_LOOKUP_GEN_IDX] =3D "LOOKUP_GEN_IDX", [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D "LOOKUP_GEN_IDX_SEL", [VCAP_KF_LOOKUP_PAG] =3D "LOOKUP_PAG", + [VCAP_KF_MIRROR_PROBE] =3D "MIRROR_PROBE", [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D "OAM_CCM_CNTS_EQ0", [VCAP_KF_OAM_DETECTED] =3D "OAM_DETECTED", [VCAP_KF_OAM_FLAGS] =3D "OAM_FLAGS", @@ -3356,6 +3680,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_OAM_OPCODE] =3D "OAM_OPCODE", [VCAP_KF_OAM_VER] =3D "OAM_VER", [VCAP_KF_OAM_Y1731_IS] =3D "OAM_Y1731_IS", + [VCAP_KF_PROT_ACTIVE] =3D "PROT_ACTIVE", [VCAP_KF_TCP_IS] =3D "TCP_IS", [VCAP_KF_TCP_UDP_IS] =3D "TCP_UDP_IS", [VCAP_KF_TYPE] =3D "TYPE", @@ -3370,16 +3695,23 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_COPY_PORT_NUM] =3D "COPY_PORT_NUM", [VCAP_AF_COPY_QUEUE_NUM] =3D "COPY_QUEUE_NUM", [VCAP_AF_CPU_COPY_ENA] =3D "CPU_COPY_ENA", + [VCAP_AF_CPU_QU] =3D "CPU_QU", [VCAP_AF_CPU_QUEUE_NUM] =3D "CPU_QUEUE_NUM", + [VCAP_AF_DEI_A_VAL] =3D "DEI_A_VAL", + [VCAP_AF_DEI_B_VAL] =3D "DEI_B_VAL", + [VCAP_AF_DEI_C_VAL] =3D "DEI_C_VAL", [VCAP_AF_DEI_ENA] =3D "DEI_ENA", [VCAP_AF_DEI_VAL] =3D "DEI_VAL", [VCAP_AF_DP_ENA] =3D "DP_ENA", [VCAP_AF_DP_VAL] =3D "DP_VAL", [VCAP_AF_DSCP_ENA] =3D "DSCP_ENA", + [VCAP_AF_DSCP_SEL] =3D "DSCP_SEL", [VCAP_AF_DSCP_VAL] =3D "DSCP_VAL", [VCAP_AF_ES2_REW_CMD] =3D "ES2_REW_CMD", + [VCAP_AF_ESDX] =3D "ESDX", [VCAP_AF_FWD_KILL_ENA] =3D "FWD_KILL_ENA", [VCAP_AF_FWD_MODE] =3D "FWD_MODE", + [VCAP_AF_FWD_SEL] =3D "FWD_SEL", [VCAP_AF_HIT_ME_ONCE] =3D "HIT_ME_ONCE", [VCAP_AF_HOST_MATCH] =3D "HOST_MATCH", [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D "IGNORE_PIPELINE_CTRL", @@ -3387,6 +3719,7 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D "ISDX_ADD_REPLACE_SEL", [VCAP_AF_ISDX_ENA] =3D "ISDX_ENA", [VCAP_AF_ISDX_VAL] =3D "ISDX_VAL", + [VCAP_AF_LOOP_ENA] =3D "LOOP_ENA", [VCAP_AF_LRN_DIS] =3D "LRN_DIS", [VCAP_AF_MAP_IDX] =3D "MAP_IDX", [VCAP_AF_MAP_KEY] =3D "MAP_KEY", @@ -3401,20 +3734,45 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_NXT_IDX_CTRL] =3D "NXT_IDX_CTRL", [VCAP_AF_PAG_OVERRIDE_MASK] =3D "PAG_OVERRIDE_MASK", [VCAP_AF_PAG_VAL] =3D "PAG_VAL", + [VCAP_AF_PCP_A_VAL] =3D "PCP_A_VAL", + [VCAP_AF_PCP_B_VAL] =3D "PCP_B_VAL", + [VCAP_AF_PCP_C_VAL] =3D "PCP_C_VAL", [VCAP_AF_PCP_ENA] =3D "PCP_ENA", [VCAP_AF_PCP_VAL] =3D "PCP_VAL", + [VCAP_AF_PIPELINE_ACT] =3D "PIPELINE_ACT", [VCAP_AF_PIPELINE_FORCE_ENA] =3D "PIPELINE_FORCE_ENA", [VCAP_AF_PIPELINE_PT] =3D "PIPELINE_PT", [VCAP_AF_POLICE_ENA] =3D "POLICE_ENA", [VCAP_AF_POLICE_IDX] =3D "POLICE_IDX", [VCAP_AF_POLICE_REMARK] =3D "POLICE_REMARK", [VCAP_AF_POLICE_VCAP_ONLY] =3D "POLICE_VCAP_ONLY", + [VCAP_AF_POP_VAL] =3D "POP_VAL", [VCAP_AF_PORT_MASK] =3D "PORT_MASK", + [VCAP_AF_PUSH_CUSTOMER_TAG] =3D "PUSH_CUSTOMER_TAG", + [VCAP_AF_PUSH_INNER_TAG] =3D "PUSH_INNER_TAG", + [VCAP_AF_PUSH_OUTER_TAG] =3D "PUSH_OUTER_TAG", [VCAP_AF_QOS_ENA] =3D "QOS_ENA", [VCAP_AF_QOS_VAL] =3D "QOS_VAL", [VCAP_AF_REW_OP] =3D "REW_OP", [VCAP_AF_RT_DIS] =3D "RT_DIS", + [VCAP_AF_SWAP_MACS_ENA] =3D "SWAP_MACS_ENA", + [VCAP_AF_TAG_A_DEI_SEL] =3D "TAG_A_DEI_SEL", + [VCAP_AF_TAG_A_PCP_SEL] =3D "TAG_A_PCP_SEL", + [VCAP_AF_TAG_A_TPID_SEL] =3D "TAG_A_TPID_SEL", + [VCAP_AF_TAG_A_VID_SEL] =3D "TAG_A_VID_SEL", + [VCAP_AF_TAG_B_DEI_SEL] =3D "TAG_B_DEI_SEL", + [VCAP_AF_TAG_B_PCP_SEL] =3D "TAG_B_PCP_SEL", + [VCAP_AF_TAG_B_TPID_SEL] =3D "TAG_B_TPID_SEL", + [VCAP_AF_TAG_B_VID_SEL] =3D "TAG_B_VID_SEL", + [VCAP_AF_TAG_C_DEI_SEL] =3D "TAG_C_DEI_SEL", + [VCAP_AF_TAG_C_PCP_SEL] =3D "TAG_C_PCP_SEL", + [VCAP_AF_TAG_C_TPID_SEL] =3D "TAG_C_TPID_SEL", + [VCAP_AF_TAG_C_VID_SEL] =3D "TAG_C_VID_SEL", [VCAP_AF_TYPE] =3D "TYPE", + [VCAP_AF_UNTAG_VID_ENA] =3D "UNTAG_VID_ENA", + [VCAP_AF_VID_A_VAL] =3D "VID_A_VAL", + [VCAP_AF_VID_B_VAL] =3D "VID_B_VAL", + [VCAP_AF_VID_C_VAL] =3D "VID_C_VAL", [VCAP_AF_VID_VAL] =3D "VID_VAL", }; =20 @@ -3462,6 +3820,27 @@ const struct vcap_info sparx5_vcaps[] =3D { .keyfield_set_typegroups =3D is2_keyfield_set_typegroups, .actionfield_set_typegroups =3D is2_actionfield_set_typegroups, }, + [VCAP_TYPE_ES0] =3D { + .name =3D "es0", + .rows =3D 4096, + .sw_count =3D 1, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 489, + .default_cnt =3D 70, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D es0_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(es0_keyfield_set), + .actionfield_set =3D es0_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(es0_actionfield_set), + .keyfield_set_map =3D es0_keyfield_set_map, + .keyfield_set_map_size =3D es0_keyfield_set_map_size, + .actionfield_set_map =3D es0_actionfield_set_map, + .actionfield_set_map_size =3D es0_actionfield_set_map_size, + .keyfield_set_typegroups =3D es0_keyfield_set_typegroups, + .actionfield_set_typegroups =3D es0_actionfield_set_typegroups, + }, [VCAP_TYPE_ES2] =3D { .name =3D "es2", .rows =3D 1024, @@ -3487,7 +3866,7 @@ const struct vcap_info sparx5_vcaps[] =3D { =20 const struct vcap_statistics sparx5_vcap_stats =3D { .name =3D "sparx5", - .count =3D 3, + .count =3D 4, .keyfield_set_names =3D vcap_keyfield_set_names, .actionfield_set_names =3D vcap_actionfield_set_names, .keyfield_names =3D vcap_keyfield_names, diff --git a/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h b/drivers/ne= t/ethernet/microchip/vcap/vcap_ag_api.h index 9c6766c4b75d..0844fcaeee68 100644 --- a/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h +++ b/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h @@ -3,14 +3,15 @@ * Microchip VCAP API */ =20 -/* This file is autogenerated by cml-utils 2023-01-17 16:52:16 +0100. - * Commit ID: 229ec79be5df142c1f335a01d0e63232d4feb2ba +/* This file is autogenerated by cml-utils 2023-02-10 11:15:56 +0100. + * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada */ =20 #ifndef __VCAP_AG_API__ #define __VCAP_AG_API__ =20 enum vcap_type { + VCAP_TYPE_ES0, VCAP_TYPE_ES2, VCAP_TYPE_IS0, VCAP_TYPE_IS2, @@ -26,10 +27,11 @@ enum vcap_keyfield_set { VCAP_KFS_IP4_TCP_UDP, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 = X2 */ VCAP_KFS_IP4_VID, /* sparx5 es2 X3 */ VCAP_KFS_IP6_OTHER, /* lan966x is2 X4 */ - VCAP_KFS_IP6_STD, /* sparx5 is2 X6, lan966x is2 X2 */ + VCAP_KFS_IP6_STD, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 = X2 */ VCAP_KFS_IP6_TCP_UDP, /* lan966x is2 X4 */ VCAP_KFS_IP6_VID, /* sparx5 es2 X6 */ VCAP_KFS_IP_7TUPLE, /* sparx5 is2 X12, sparx5 es2 X12 */ + VCAP_KFS_ISDX, /* sparx5 es0 X1 */ VCAP_KFS_LL_FULL, /* sparx5 is0 X6 */ VCAP_KFS_MAC_ETYPE, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 = X2 */ VCAP_KFS_MAC_LLC, /* lan966x is2 X2 */ @@ -75,6 +77,8 @@ enum vcap_keyfield_set { * Third PCP in multiple vlan tags (not always available) * VCAP_KF_8021Q_PCP_CLS: W3, sparx5: is2/es2, lan966x: is2 * Classified PCP + * VCAP_KF_8021Q_TPID: W3, sparx5: es0 + * TPID for outer tag: 0: Customer TPID 1: Service TPID (88A8 or program= mable) * VCAP_KF_8021Q_TPID0: W3, sparx5: is0 * First TPIC in multiple vlan tags (outer tag or default port tag) * VCAP_KF_8021Q_TPID1: W3, sparx5: is0 @@ -87,7 +91,8 @@ enum vcap_keyfield_set { * Second VID in multiple vlan tags (inner tag) * VCAP_KF_8021Q_VID2: W12, sparx5: is0 * Third VID in multiple vlan tags (not always available) - * VCAP_KF_8021Q_VID_CLS: sparx5 is2 W13, sparx5 es2 W13, lan966x is2 W12 + * VCAP_KF_8021Q_VID_CLS: sparx5 is2 W13, sparx5 es0 W13, sparx5 es2 W13, + * lan966x is2 W12 * Classified VID * VCAP_KF_8021Q_VLAN_TAGGED_IS: W1, sparx5: is2/es2, lan966x: is2 * Sparx5: Set if frame was received with a VLAN tag, LAN966x: Set if fr= ame has @@ -111,7 +116,7 @@ enum vcap_keyfield_set { * Sender Hardware Address =3D SMAC (ARP) * VCAP_KF_ARP_TGT_MATCH_IS: W1, sparx5: is2/es2, lan966x: is2 * Target Hardware Address =3D SMAC (RARP) - * VCAP_KF_COSID_CLS: W3, sparx5: es2 + * VCAP_KF_COSID_CLS: W3, sparx5: es0/es2 * Class of service * VCAP_KF_ES0_ISDX_KEY_ENA: W1, sparx5: es2 * The value taken from the IFH .FWD.ES0_ISDX_KEY_ENA @@ -127,6 +132,8 @@ enum vcap_keyfield_set { * VCAP_KF_IF_EGR_PORT_MASK_RNG: W3, sparx5: es2 * Select which 32 port group is available in IF_EGR_PORT (or virtual po= rts or * CPU queue) + * VCAP_KF_IF_EGR_PORT_NO: W7, sparx5: es0 + * Egress port number * VCAP_KF_IF_IGR_PORT: sparx5 is0 W7, sparx5 es2 W9, lan966x is2 W4 * Sparx5: Logical ingress port number retrieved from * ANA_CL::PORT_ID_CFG.LPORT_NUM or ERLEG, LAN966x: ingress port nunmber @@ -154,9 +161,9 @@ enum vcap_keyfield_set { * Payload bytes after IP header * VCAP_KF_IP_SNAP_IS: W1, sparx5: is0 * Set if frame is IPv4, IPv6, or SNAP frame - * VCAP_KF_ISDX_CLS: W12, sparx5: is2/es2 + * VCAP_KF_ISDX_CLS: W12, sparx5: is2/es0/es2 * Classified ISDX - * VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2/es2, lan966x: is2 + * VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2/es0/es2, lan966x: is2 * Set if classified ISDX > 0 * VCAP_KF_L2_BC_IS: W1, sparx5: is0/is2/es2, lan966x: is2 * Set if frame's destination MAC address is the broadcast address @@ -187,7 +194,7 @@ enum vcap_keyfield_set { * SNAP header after LLC header (AA-AA-03) * VCAP_KF_L3_DIP_EQ_SIP_IS: W1, sparx5: is2/es2, lan966x: is2 * Set if Src IP matches Dst IP address - * VCAP_KF_L3_DPL_CLS: W1, sparx5: es2 + * VCAP_KF_L3_DPL_CLS: W1, sparx5: es0/es2 * The frames drop precedence level * VCAP_KF_L3_DSCP: W6, sparx5: is0 * Frame's DSCP value @@ -216,8 +223,8 @@ enum vcap_keyfield_set { * IPv4 frames: IP protocol. IPv6 frames: Next header, same as for IPV4 * VCAP_KF_L3_OPTIONS_IS: W1, sparx5: is0/is2/es2, lan966x: is2 * Set if IPv4 frame contains options (IP len > 5) - * VCAP_KF_L3_PAYLOAD: sparx5 is2 W96, sparx5 is2 W40, sparx5 es2 W96, lan= 966x - * is2 W56 + * VCAP_KF_L3_PAYLOAD: sparx5 is2 W96, sparx5 is2 W40, sparx5 es2 W96, spa= rx5 + * es2 W40, lan966x is2 W56 * Sparx5: Payload bytes after IP header. IPv4: IPv4 options are not par= sed so * payload is always taken 20 bytes after the start of the IPv4 header, = LAN966x: * Bytes 0-6 after IP header @@ -294,7 +301,7 @@ enum vcap_keyfield_set { * Frame's OAM version * VCAP_KF_OAM_Y1731_IS: W1, sparx5: is2/es2, lan966x: is2 * Set if frame's EtherType =3D 0x8902 - * VCAP_KF_PROT_ACTIVE: W1, sparx5: es2 + * VCAP_KF_PROT_ACTIVE: W1, sparx5: es0/es2 * Protection is active * VCAP_KF_TCP_IS: W1, sparx5: is0/is2/es2, lan966x: is2 * Set if frame is IPv4 TCP frame (IP protocol =3D 6) or IPv6 TCP frames= (Next @@ -303,7 +310,7 @@ enum vcap_keyfield_set { * Set if frame is IPv4/IPv6 TCP or UDP frame (IP protocol/next header e= quals 6 * or 17) * VCAP_KF_TYPE: sparx5 is0 W2, sparx5 is0 W1, sparx5 is2 W4, sparx5 is2 W= 2, - * sparx5 es2 W3, lan966x is2 W4, lan966x is2 W2 + * sparx5 es0 W1, sparx5 es2 W3, lan966x is2 W4, lan966x is2 W2 * Keyset type id - set by the API */ =20 @@ -324,6 +331,7 @@ enum vcap_key_field { VCAP_KF_8021Q_PCP1, VCAP_KF_8021Q_PCP2, VCAP_KF_8021Q_PCP_CLS, + VCAP_KF_8021Q_TPID, VCAP_KF_8021Q_TPID0, VCAP_KF_8021Q_TPID1, VCAP_KF_8021Q_TPID2, @@ -348,6 +356,7 @@ enum vcap_key_field { VCAP_KF_HOST_MATCH, VCAP_KF_IF_EGR_PORT_MASK, VCAP_KF_IF_EGR_PORT_MASK_RNG, + VCAP_KF_IF_EGR_PORT_NO, VCAP_KF_IF_IGR_PORT, VCAP_KF_IF_IGR_PORT_MASK, VCAP_KF_IF_IGR_PORT_MASK_L3, @@ -429,6 +438,7 @@ enum vcap_actionfield_set { VCAP_AFS_BASE_TYPE, /* sparx5 is2 X3, sparx5 es2 X3, lan966x is2 = X2 */ VCAP_AFS_CLASSIFICATION, /* sparx5 is0 X2 */ VCAP_AFS_CLASS_REDUCED, /* sparx5 is0 X1 */ + VCAP_AFS_ES0, /* sparx5 es0 X1 */ VCAP_AFS_FULL, /* sparx5 is0 X3 */ VCAP_AFS_SMAC_SIP, /* lan966x is2 X1 */ }; @@ -456,8 +466,16 @@ enum vcap_actionfield_set { * VCAP_AF_CPU_COPY_ENA: W1, sparx5: is2/es2, lan966x: is2 * Setting this bit to 1 causes all frames that hit this action to be co= pied to * the CPU extraction queue specified in CPU_QUEUE_NUM. + * VCAP_AF_CPU_QU: W3, sparx5: es0 + * CPU extraction queue. Used when FWD_SEL >0 and PIPELINE_ACT =3D XTR. * VCAP_AF_CPU_QUEUE_NUM: W3, sparx5: is2/es2, lan966x: is2 * CPU queue number. Used when CPU_COPY_ENA is set. + * VCAP_AF_DEI_A_VAL: W1, sparx5: es0 + * DEI used in ES0 tag A. See TAG_A_DEI_SEL. + * VCAP_AF_DEI_B_VAL: W1, sparx5: es0 + * DEI used in ES0 tag B. See TAG_B_DEI_SEL. + * VCAP_AF_DEI_C_VAL: W1, sparx5: es0 + * DEI used in ES0 tag C. See TAG_C_DEI_SEL. * VCAP_AF_DEI_ENA: W1, sparx5: is0 * If set, use DEI_VAL as classified DEI value. Otherwise, DEI from basic * classification is used @@ -471,16 +489,28 @@ enum vcap_actionfield_set { * VCAP_AF_DSCP_ENA: W1, sparx5: is0 * If set, use DSCP_VAL as classified DSCP value. Otherwise, DSCP value = from * basic classification is used. - * VCAP_AF_DSCP_VAL: W6, sparx5: is0 + * VCAP_AF_DSCP_SEL: W3, sparx5: es0 + * Selects source for DSCP. 0: Controlled by port configuration and IFH.= 1: + * Classified DSCP via IFH. 2: DSCP_VAL. 3: Reserved. 4: Mapped using ma= pping + * table 0, otherwise use DSCP_VAL. 5: Mapped using mapping table 1, oth= erwise + * use mapping table 0. 6: Mapped using mapping table 2, otherwise use D= SCP_VAL. + * 7: Mapped using mapping table 3, otherwise use mapping table 2 + * VCAP_AF_DSCP_VAL: W6, sparx5: is0/es0 * See DSCP_ENA. * VCAP_AF_ES2_REW_CMD: W3, sparx5: es2 * Command forwarded to REW: 0: No action. 1: SWAP MAC addresses. 2: Do = L2CP * DMAC translation when entering or leaving a tunnel. + * VCAP_AF_ESDX: W13, sparx5: es0 + * Egress counter index. Used to index egress counter set as defined in + * REW::STAT_CFG. * VCAP_AF_FWD_KILL_ENA: W1, lan966x: is2 * Setting this bit to 1 denies forwarding of the frame forwarding to an= y front * port. The frame can still be copied to the CPU by other actions. * VCAP_AF_FWD_MODE: W2, sparx5: es2 * Forward selector: 0: Forward. 1: Discard. 2: Redirect. 3: Copy. + * VCAP_AF_FWD_SEL: W2, sparx5: es0 + * ES0 Forward selector. 0: No action. 1: Copy to loopback interface. 2: + * Redirect to loopback interface. 3: Discard * VCAP_AF_HIT_ME_ONCE: W1, sparx5: is2/es2, lan966x: is2 * Setting this bit to 1 causes the first frame that hits this action wh= ere the * HIT_CNT counter is zero to be copied to the CPU extraction queue spec= ified in @@ -504,6 +534,8 @@ enum vcap_actionfield_set { * POLICE_IDX[8:0]. * VCAP_AF_ISDX_VAL: W12, sparx5: is0 * See isdx_add_replace_sel + * VCAP_AF_LOOP_ENA: W1, sparx5: es0 + * 0: Forward based on PIPELINE_PT and FWD_SEL * VCAP_AF_LRN_DIS: W1, sparx5: is2, lan966x: is2 * Setting this bit to 1 disables learning of frames hitting this action. * VCAP_AF_MAP_IDX: W9, sparx5: is0 @@ -549,15 +581,24 @@ enum vcap_actionfield_set { * (input) AND ~PAG_OVERRIDE_MASK) OR (PAG_VAL AND PAG_OVERRIDE_MASK) * VCAP_AF_PAG_VAL: W8, sparx5: is0 * See PAG_OVERRIDE_MASK. + * VCAP_AF_PCP_A_VAL: W3, sparx5: es0 + * PCP used in ES0 tag A. See TAG_A_PCP_SEL. + * VCAP_AF_PCP_B_VAL: W3, sparx5: es0 + * PCP used in ES0 tag B. See TAG_B_PCP_SEL. + * VCAP_AF_PCP_C_VAL: W3, sparx5: es0 + * PCP used in ES0 tag C. See TAG_C_PCP_SEL. * VCAP_AF_PCP_ENA: W1, sparx5: is0 * If set, use PCP_VAL as classified PCP value. Otherwise, PCP from basic * classification is used. * VCAP_AF_PCP_VAL: W3, sparx5: is0 * See PCP_ENA. + * VCAP_AF_PIPELINE_ACT: W1, sparx5: es0 + * Pipeline action when FWD_SEL > 0. 0: XTR. CPU_QU selects CPU extracti= on queue + * 1: LBK_ASM. * VCAP_AF_PIPELINE_FORCE_ENA: W1, sparx5: is2 * If set, use PIPELINE_PT unconditionally and set PIPELINE_ACT =3D NONE= if * PIPELINE_PT =3D=3D NONE. Overrules previous settings of pipeline poin= t. - * VCAP_AF_PIPELINE_PT: W5, sparx5: is2 + * VCAP_AF_PIPELINE_PT: sparx5 is2 W5, sparx5 es0 W2 * Pipeline point used if PIPELINE_FORCE_ENA is set * VCAP_AF_POLICE_ENA: W1, sparx5: is2/es2, lan966x: is2 * Setting this bit to 1 causes frames that hit this action to be police= d by the @@ -570,8 +611,23 @@ enum vcap_actionfield_set { * VCAP_AF_POLICE_VCAP_ONLY: W1, lan966x: is2 * Disable policing from QoS, and port policers. Only the VCAP policer s= elected * by POLICE_IDX is active. Only applies to the second lookup. + * VCAP_AF_POP_VAL: W2, sparx5: es0 + * Controls popping of Q-tags. The final number of Q-tags popped is calc= ulated + * as shown in section 4.28.7.2 VLAN Pop Decision. * VCAP_AF_PORT_MASK: sparx5 is0 W65, sparx5 is2 W68, lan966x is2 W8 * Port mask applied to the forwarding decision based on MASK_MODE. + * VCAP_AF_PUSH_CUSTOMER_TAG: W2, sparx5: es0 + * Selects tag C mode: 0: Do not push tag C. 1: Push tag C if + * IFH.VSTAX.TAG.WAS_TAGGED =3D 1. 2: Push tag C if IFH.VSTAX.TAG.WAS_TA= GGED =3D 0. + * 3: Push tag C if UNTAG_VID_ENA =3D 0 or (C-TAG.VID ! =3D VID_C_VAL). + * VCAP_AF_PUSH_INNER_TAG: W1, sparx5: es0 + * Controls inner tagging. 0: Do not push ES0 tag B as inner tag. 1: Pus= h ES0 + * tag B as inner tag. + * VCAP_AF_PUSH_OUTER_TAG: W2, sparx5: es0 + * Controls outer tagging. 0: No ES0 tag A: Port tag is allowed if enabl= ed on + * port. 1: ES0 tag A: Push ES0 tag A. No port tag. 2: Force port tag: A= lways + * push port tag. No ES0 tag A. 3: Force untag: Never push port tag or E= S0 tag + * A. * VCAP_AF_QOS_ENA: W1, sparx5: is0 * If set, use QOS_VAL as classified QoS class. Otherwise, QoS class fro= m basic * classification is used. @@ -582,8 +638,65 @@ enum vcap_actionfield_set { * VCAP_AF_RT_DIS: W1, sparx5: is2 * If set, routing is disallowed. Only applies when IS_INNER_ACL is 0. S= ee also * IGR_ACL_ENA, EGR_ACL_ENA, and RLEG_STAT_IDX. + * VCAP_AF_SWAP_MACS_ENA: W1, sparx5: es0 + * This setting is only active when FWD_SEL =3D 1 or FWD_SEL =3D 2 and P= IPELINE_ACT + * =3D LBK_ASM. 0: No action. 1: Swap MACs and clear bit 40 in new SMAC. + * VCAP_AF_TAG_A_DEI_SEL: W3, sparx5: es0 + * Selects PCP for ES0 tag A. 0: Classified DEI. 1: DEI_A_VAL. 2: DP and= QoS + * mapped to PCP (per port table). 3: DP. + * VCAP_AF_TAG_A_PCP_SEL: W3, sparx5: es0 + * Selects PCP for ES0 tag A. 0: Classified PCP. 1: PCP_A_VAL. 2: DP and= QoS + * mapped to PCP (per port table). 3: QoS class. + * VCAP_AF_TAG_A_TPID_SEL: W3, sparx5: es0 + * Selects TPID for ES0 tag A: 0: 0x8100. 1: 0x88A8. 2: Custom + * (REW:PORT:PORT_VLAN_CFG.PORT_TPID). 3: If IFH.TAG_TYPE =3D 0 then 0x8= 100 else + * custom. + * VCAP_AF_TAG_A_VID_SEL: W2, sparx5: es0 + * Selects VID for ES0 tag A. 0: Classified VID + VID_A_VAL. 1: VID_A_VA= L. + * VCAP_AF_TAG_B_DEI_SEL: W3, sparx5: es0 + * Selects PCP for ES0 tag B. 0: Classified DEI. 1: DEI_B_VAL. 2: DP and= QoS + * mapped to PCP (per port table). 3: DP. + * VCAP_AF_TAG_B_PCP_SEL: W3, sparx5: es0 + * Selects PCP for ES0 tag B. 0: Classified PCP. 1: PCP_B_VAL. 2: DP and= QoS + * mapped to PCP (per port table). 3: QoS class. + * VCAP_AF_TAG_B_TPID_SEL: W3, sparx5: es0 + * Selects TPID for ES0 tag B. 0: 0x8100. 1: 0x88A8. 2: Custom + * (REW:PORT:PORT_VLAN_CFG.PORT_TPID). 3: If IFH.TAG_TYPE =3D 0 then 0x8= 100 else + * custom. + * VCAP_AF_TAG_B_VID_SEL: W2, sparx5: es0 + * Selects VID for ES0 tag B. 0: Classified VID + VID_B_VAL. 1: VID_B_VA= L. + * VCAP_AF_TAG_C_DEI_SEL: W3, sparx5: es0 + * Selects DEI source for ES0 tag C. 0: Classified DEI. 1: DEI_C_VAL. 2: + * REW::DP_MAP.DP [IFH.VSTAX.QOS.DP]. 3: DEI of popped VLAN tag if avail= able + * (IFH.VSTAX.TAG.WAS_TAGGED =3D 1 and tot_pop_cnt>0) else DEI_C_VAL. 4:= Mapped + * using mapping table 0, otherwise use DEI_C_VAL. 5: Mapped using mappi= ng table + * 1, otherwise use mapping table 0. 6: Mapped using mapping table 2, ot= herwise + * use DEI_C_VAL. 7: Mapped using mapping table 3, otherwise use mapping= table + * 2. + * VCAP_AF_TAG_C_PCP_SEL: W3, sparx5: es0 + * Selects PCP source for ES0 tag C. 0: Classified PCP. 1: PCP_C_VAL. 2: + * Reserved. 3: PCP of popped VLAN tag if available (IFH.VSTAX.TAG.WAS_T= AGGED=3D1 + * and tot_pop_cnt>0) else PCP_C_VAL. 4: Mapped using mapping table 0, o= therwise + * use PCP_C_VAL. 5: Mapped using mapping table 1, otherwise use mapping= table + * 0. 6: Mapped using mapping table 2, otherwise use PCP_C_VAL. 7: Mappe= d using + * mapping table 3, otherwise use mapping table 2. + * VCAP_AF_TAG_C_TPID_SEL: W3, sparx5: es0 + * Selects TPID for ES0 tag C. 0: 0x8100. 1: 0x88A8. 2: Custom 1. 3: Cus= tom 2. + * 4: Custom 3. 5: See TAG_A_TPID_SEL. + * VCAP_AF_TAG_C_VID_SEL: W2, sparx5: es0 + * Selects VID for ES0 tag C. The resulting VID is termed C-TAG.VID. 0: + * Classified VID. 1: VID_C_VAL. 2: IFH.ENCAP.GVID. 3: Reserved. * VCAP_AF_TYPE: W1, sparx5: is0 * Actionset type id - Set by the API + * VCAP_AF_UNTAG_VID_ENA: W1, sparx5: es0 + * Controls insertion of tag C. Untag or insert mode can be selected. See + * PUSH_CUSTOMER_TAG. + * VCAP_AF_VID_A_VAL: W12, sparx5: es0 + * VID used in ES0 tag A. See TAG_A_VID_SEL. + * VCAP_AF_VID_B_VAL: W12, sparx5: es0 + * VID used in ES0 tag B. See TAG_B_VID_SEL. + * VCAP_AF_VID_C_VAL: W12, sparx5: es0 + * VID used in ES0 tag C. See TAG_C_VID_SEL. * VCAP_AF_VID_VAL: W13, sparx5: is0 * New VID Value */ @@ -597,16 +710,23 @@ enum vcap_action_field { VCAP_AF_COPY_PORT_NUM, VCAP_AF_COPY_QUEUE_NUM, VCAP_AF_CPU_COPY_ENA, + VCAP_AF_CPU_QU, VCAP_AF_CPU_QUEUE_NUM, + VCAP_AF_DEI_A_VAL, + VCAP_AF_DEI_B_VAL, + VCAP_AF_DEI_C_VAL, VCAP_AF_DEI_ENA, VCAP_AF_DEI_VAL, VCAP_AF_DP_ENA, VCAP_AF_DP_VAL, VCAP_AF_DSCP_ENA, + VCAP_AF_DSCP_SEL, VCAP_AF_DSCP_VAL, VCAP_AF_ES2_REW_CMD, + VCAP_AF_ESDX, VCAP_AF_FWD_KILL_ENA, VCAP_AF_FWD_MODE, + VCAP_AF_FWD_SEL, VCAP_AF_HIT_ME_ONCE, VCAP_AF_HOST_MATCH, VCAP_AF_IGNORE_PIPELINE_CTRL, @@ -614,6 +734,7 @@ enum vcap_action_field { VCAP_AF_ISDX_ADD_REPLACE_SEL, VCAP_AF_ISDX_ENA, VCAP_AF_ISDX_VAL, + VCAP_AF_LOOP_ENA, VCAP_AF_LRN_DIS, VCAP_AF_MAP_IDX, VCAP_AF_MAP_KEY, @@ -628,20 +749,45 @@ enum vcap_action_field { VCAP_AF_NXT_IDX_CTRL, VCAP_AF_PAG_OVERRIDE_MASK, VCAP_AF_PAG_VAL, + VCAP_AF_PCP_A_VAL, + VCAP_AF_PCP_B_VAL, + VCAP_AF_PCP_C_VAL, VCAP_AF_PCP_ENA, VCAP_AF_PCP_VAL, + VCAP_AF_PIPELINE_ACT, VCAP_AF_PIPELINE_FORCE_ENA, VCAP_AF_PIPELINE_PT, VCAP_AF_POLICE_ENA, VCAP_AF_POLICE_IDX, VCAP_AF_POLICE_REMARK, VCAP_AF_POLICE_VCAP_ONLY, + VCAP_AF_POP_VAL, VCAP_AF_PORT_MASK, + VCAP_AF_PUSH_CUSTOMER_TAG, + VCAP_AF_PUSH_INNER_TAG, + VCAP_AF_PUSH_OUTER_TAG, VCAP_AF_QOS_ENA, VCAP_AF_QOS_VAL, VCAP_AF_REW_OP, VCAP_AF_RT_DIS, + VCAP_AF_SWAP_MACS_ENA, + VCAP_AF_TAG_A_DEI_SEL, + VCAP_AF_TAG_A_PCP_SEL, + VCAP_AF_TAG_A_TPID_SEL, + VCAP_AF_TAG_A_VID_SEL, + VCAP_AF_TAG_B_DEI_SEL, + VCAP_AF_TAG_B_PCP_SEL, + VCAP_AF_TAG_B_TPID_SEL, + VCAP_AF_TAG_B_VID_SEL, + VCAP_AF_TAG_C_DEI_SEL, + VCAP_AF_TAG_C_PCP_SEL, + VCAP_AF_TAG_C_TPID_SEL, + VCAP_AF_TAG_C_VID_SEL, VCAP_AF_TYPE, + VCAP_AF_UNTAG_VID_ENA, + VCAP_AF_VID_A_VAL, + VCAP_AF_VID_B_VAL, + VCAP_AF_VID_C_VAL, VCAP_AF_VID_VAL, }; =20 diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api_debugfs_kunit.c b= /drivers/net/ethernet/microchip/vcap/vcap_api_debugfs_kunit.c index b9c1c9d5eee8..0de3f677135a 100644 --- a/drivers/net/ethernet/microchip/vcap/vcap_api_debugfs_kunit.c +++ b/drivers/net/ethernet/microchip/vcap/vcap_api_debugfs_kunit.c @@ -387,7 +387,7 @@ static const char * const test_admin_info_expect[] =3D { "default_cnt: 73\n", "require_cnt_dis: 0\n", "version: 1\n", - "vtype: 2\n", + "vtype: 3\n", "vinst: 0\n", "ingress: 1\n", "first_cid: 10000\n", @@ -435,7 +435,7 @@ static const char * const test_admin_expect[] =3D { "default_cnt: 73\n", "require_cnt_dis: 0\n", "version: 1\n", - "vtype: 2\n", + "vtype: 3\n", "vinst: 0\n", "ingress: 1\n", "first_cid: 8000000\n", diff --git a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c b/drive= rs/net/ethernet/microchip/vcap/vcap_model_kunit.c index 6d5d73d00562..5dbfc0d0c369 100644 --- a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c +++ b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c @@ -1,6 +1,10 @@ // SPDX-License-Identifier: BSD-3-Clause -/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. - * Microchip VCAP API Test VCAP Model Data +/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries. + * Microchip VCAP test model interface for kunit testing + */ + +/* This file is autogenerated by cml-utils 2023-02-10 11:16:00 +0100. + * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada */ =20 #include @@ -1619,16 +1623,6 @@ static const struct vcap_field es2_mac_etype_keyfiel= d[] =3D { .offset =3D 3, .width =3D 1, }, - [VCAP_KF_ACL_GRP_ID] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 4, - .width =3D 8, - }, - [VCAP_KF_PROT_ACTIVE] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 12, - .width =3D 1, - }, [VCAP_KF_L2_MC_IS] =3D { .type =3D VCAP_FIELD_BIT, .offset =3D 13, @@ -1704,16 +1698,6 @@ static const struct vcap_field es2_mac_etype_keyfiel= d[] =3D { .offset =3D 95, .width =3D 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 96, - .width =3D 1, - }, - [VCAP_KF_MIRROR_PROBE] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 97, - .width =3D 2, - }, [VCAP_KF_L2_DMAC] =3D { .type =3D VCAP_FIELD_U48, .offset =3D 99, @@ -1762,16 +1746,6 @@ static const struct vcap_field es2_arp_keyfield[] = =3D { .offset =3D 3, .width =3D 1, }, - [VCAP_KF_ACL_GRP_ID] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 4, - .width =3D 8, - }, - [VCAP_KF_PROT_ACTIVE] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 12, - .width =3D 1, - }, [VCAP_KF_L2_MC_IS] =3D { .type =3D VCAP_FIELD_BIT, .offset =3D 13, @@ -1842,16 +1816,6 @@ static const struct vcap_field es2_arp_keyfield[] = =3D { .offset =3D 94, .width =3D 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 95, - .width =3D 1, - }, - [VCAP_KF_MIRROR_PROBE] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 96, - .width =3D 2, - }, [VCAP_KF_L2_SMAC] =3D { .type =3D VCAP_FIELD_U48, .offset =3D 98, @@ -1920,16 +1884,6 @@ static const struct vcap_field es2_ip4_tcp_udp_keyfi= eld[] =3D { .offset =3D 3, .width =3D 1, }, - [VCAP_KF_ACL_GRP_ID] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 4, - .width =3D 8, - }, - [VCAP_KF_PROT_ACTIVE] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 12, - .width =3D 1, - }, [VCAP_KF_L2_MC_IS] =3D { .type =3D VCAP_FIELD_BIT, .offset =3D 13, @@ -2005,16 +1959,6 @@ static const struct vcap_field es2_ip4_tcp_udp_keyfi= eld[] =3D { .offset =3D 95, .width =3D 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 96, - .width =3D 1, - }, - [VCAP_KF_MIRROR_PROBE] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 97, - .width =3D 2, - }, [VCAP_KF_IP4_IS] =3D { .type =3D VCAP_FIELD_BIT, .offset =3D 99, @@ -2133,16 +2077,6 @@ static const struct vcap_field es2_ip4_other_keyfiel= d[] =3D { .offset =3D 3, .width =3D 1, }, - [VCAP_KF_ACL_GRP_ID] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 4, - .width =3D 8, - }, - [VCAP_KF_PROT_ACTIVE] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 12, - .width =3D 1, - }, [VCAP_KF_L2_MC_IS] =3D { .type =3D VCAP_FIELD_BIT, .offset =3D 13, @@ -2218,16 +2152,6 @@ static const struct vcap_field es2_ip4_other_keyfiel= d[] =3D { .offset =3D 95, .width =3D 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 96, - .width =3D 1, - }, - [VCAP_KF_MIRROR_PROBE] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 97, - .width =3D 2, - }, [VCAP_KF_IP4_IS] =3D { .type =3D VCAP_FIELD_BIT, .offset =3D 99, @@ -2286,16 +2210,6 @@ static const struct vcap_field es2_ip_7tuple_keyfiel= d[] =3D { .offset =3D 0, .width =3D 1, }, - [VCAP_KF_ACL_GRP_ID] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 1, - .width =3D 8, - }, - [VCAP_KF_PROT_ACTIVE] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 9, - .width =3D 1, - }, [VCAP_KF_L2_MC_IS] =3D { .type =3D VCAP_FIELD_BIT, .offset =3D 10, @@ -2371,16 +2285,6 @@ static const struct vcap_field es2_ip_7tuple_keyfiel= d[] =3D { .offset =3D 92, .width =3D 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { - .type =3D VCAP_FIELD_BIT, - .offset =3D 93, - .width =3D 1, - }, - [VCAP_KF_MIRROR_PROBE] =3D { - .type =3D VCAP_FIELD_U32, - .offset =3D 94, - .width =3D 2, - }, [VCAP_KF_L2_DMAC] =3D { .type =3D VCAP_FIELD_U48, .offset =3D 96, @@ -2493,6 +2397,124 @@ static const struct vcap_field es2_ip_7tuple_keyfie= ld[] =3D { }, }; =20 +static const struct vcap_field es2_ip6_std_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 77, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 9, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 99, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 100, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 228, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 229, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 237, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 253, + .width =3D 40, + }, +}; + static const struct vcap_field es2_ip4_vid_keyfield[] =3D { [VCAP_KF_LOOKUP_FIRST_IS] =3D { .type =3D VCAP_FIELD_BIT, @@ -2752,6 +2774,11 @@ static const struct vcap_set es2_keyfield_set[] =3D { .sw_per_item =3D 12, .sw_cnt =3D 1, }, + [VCAP_KFS_IP6_STD] =3D { + .type_id =3D 4, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, [VCAP_KFS_IP4_VID] =3D { .type_id =3D -1, .sw_per_item =3D 3, @@ -2788,6 +2815,7 @@ static const struct vcap_field *es2_keyfield_set_map[= ] =3D { [VCAP_KFS_IP4_TCP_UDP] =3D es2_ip4_tcp_udp_keyfield, [VCAP_KFS_IP4_OTHER] =3D es2_ip4_other_keyfield, [VCAP_KFS_IP_7TUPLE] =3D es2_ip_7tuple_keyfield, + [VCAP_KFS_IP6_STD] =3D es2_ip6_std_keyfield, [VCAP_KFS_IP4_VID] =3D es2_ip4_vid_keyfield, [VCAP_KFS_IP6_VID] =3D es2_ip6_vid_keyfield, }; @@ -2816,6 +2844,7 @@ static int es2_keyfield_set_map_size[] =3D { [VCAP_KFS_IP4_TCP_UDP] =3D ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), [VCAP_KFS_IP4_OTHER] =3D ARRAY_SIZE(es2_ip4_other_keyfield), [VCAP_KFS_IP_7TUPLE] =3D ARRAY_SIZE(es2_ip_7tuple_keyfield), + [VCAP_KFS_IP6_STD] =3D ARRAY_SIZE(es2_ip6_std_keyfield), [VCAP_KFS_IP4_VID] =3D ARRAY_SIZE(es2_ip4_vid_keyfield), [VCAP_KFS_IP6_VID] =3D ARRAY_SIZE(es2_ip6_vid_keyfield), }; @@ -3724,6 +3753,7 @@ static const char * const vcap_keyfield_set_names[] = =3D { [VCAP_KFS_IP6_TCP_UDP] =3D "VCAP_KFS_IP6_TCP_UDP", [VCAP_KFS_IP6_VID] =3D "VCAP_KFS_IP6_VID", [VCAP_KFS_IP_7TUPLE] =3D "VCAP_KFS_IP_7TUPLE", + [VCAP_KFS_ISDX] =3D "VCAP_KFS_ISDX", [VCAP_KFS_LL_FULL] =3D "VCAP_KFS_LL_FULL", [VCAP_KFS_MAC_ETYPE] =3D "VCAP_KFS_MAC_ETYPE", [VCAP_KFS_MAC_LLC] =3D "VCAP_KFS_MAC_LLC", @@ -3742,6 +3772,7 @@ static const char * const vcap_actionfield_set_names[= ] =3D { [VCAP_AFS_BASE_TYPE] =3D "VCAP_AFS_BASE_TYPE", [VCAP_AFS_CLASSIFICATION] =3D "VCAP_AFS_CLASSIFICATION", [VCAP_AFS_CLASS_REDUCED] =3D "VCAP_AFS_CLASS_REDUCED", + [VCAP_AFS_ES0] =3D "VCAP_AFS_ES0", [VCAP_AFS_FULL] =3D "VCAP_AFS_FULL", [VCAP_AFS_SMAC_SIP] =3D "VCAP_AFS_SMAC_SIP", }; @@ -3763,6 +3794,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_8021Q_PCP1] =3D "8021Q_PCP1", [VCAP_KF_8021Q_PCP2] =3D "8021Q_PCP2", [VCAP_KF_8021Q_PCP_CLS] =3D "8021Q_PCP_CLS", + [VCAP_KF_8021Q_TPID] =3D "8021Q_TPID", [VCAP_KF_8021Q_TPID0] =3D "8021Q_TPID0", [VCAP_KF_8021Q_TPID1] =3D "8021Q_TPID1", [VCAP_KF_8021Q_TPID2] =3D "8021Q_TPID2", @@ -3787,6 +3819,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_HOST_MATCH] =3D "HOST_MATCH", [VCAP_KF_IF_EGR_PORT_MASK] =3D "IF_EGR_PORT_MASK", [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D "IF_EGR_PORT_MASK_RNG", + [VCAP_KF_IF_EGR_PORT_NO] =3D "IF_EGR_PORT_NO", [VCAP_KF_IF_IGR_PORT] =3D "IF_IGR_PORT", [VCAP_KF_IF_IGR_PORT_MASK] =3D "IF_IGR_PORT_MASK", [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D "IF_IGR_PORT_MASK_L3", @@ -3871,16 +3904,23 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_COPY_PORT_NUM] =3D "COPY_PORT_NUM", [VCAP_AF_COPY_QUEUE_NUM] =3D "COPY_QUEUE_NUM", [VCAP_AF_CPU_COPY_ENA] =3D "CPU_COPY_ENA", + [VCAP_AF_CPU_QU] =3D "CPU_QU", [VCAP_AF_CPU_QUEUE_NUM] =3D "CPU_QUEUE_NUM", + [VCAP_AF_DEI_A_VAL] =3D "DEI_A_VAL", + [VCAP_AF_DEI_B_VAL] =3D "DEI_B_VAL", + [VCAP_AF_DEI_C_VAL] =3D "DEI_C_VAL", [VCAP_AF_DEI_ENA] =3D "DEI_ENA", [VCAP_AF_DEI_VAL] =3D "DEI_VAL", [VCAP_AF_DP_ENA] =3D "DP_ENA", [VCAP_AF_DP_VAL] =3D "DP_VAL", [VCAP_AF_DSCP_ENA] =3D "DSCP_ENA", + [VCAP_AF_DSCP_SEL] =3D "DSCP_SEL", [VCAP_AF_DSCP_VAL] =3D "DSCP_VAL", [VCAP_AF_ES2_REW_CMD] =3D "ES2_REW_CMD", + [VCAP_AF_ESDX] =3D "ESDX", [VCAP_AF_FWD_KILL_ENA] =3D "FWD_KILL_ENA", [VCAP_AF_FWD_MODE] =3D "FWD_MODE", + [VCAP_AF_FWD_SEL] =3D "FWD_SEL", [VCAP_AF_HIT_ME_ONCE] =3D "HIT_ME_ONCE", [VCAP_AF_HOST_MATCH] =3D "HOST_MATCH", [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D "IGNORE_PIPELINE_CTRL", @@ -3888,6 +3928,7 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D "ISDX_ADD_REPLACE_SEL", [VCAP_AF_ISDX_ENA] =3D "ISDX_ENA", [VCAP_AF_ISDX_VAL] =3D "ISDX_VAL", + [VCAP_AF_LOOP_ENA] =3D "LOOP_ENA", [VCAP_AF_LRN_DIS] =3D "LRN_DIS", [VCAP_AF_MAP_IDX] =3D "MAP_IDX", [VCAP_AF_MAP_KEY] =3D "MAP_KEY", @@ -3902,20 +3943,45 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_NXT_IDX_CTRL] =3D "NXT_IDX_CTRL", [VCAP_AF_PAG_OVERRIDE_MASK] =3D "PAG_OVERRIDE_MASK", [VCAP_AF_PAG_VAL] =3D "PAG_VAL", + [VCAP_AF_PCP_A_VAL] =3D "PCP_A_VAL", + [VCAP_AF_PCP_B_VAL] =3D "PCP_B_VAL", + [VCAP_AF_PCP_C_VAL] =3D "PCP_C_VAL", [VCAP_AF_PCP_ENA] =3D "PCP_ENA", [VCAP_AF_PCP_VAL] =3D "PCP_VAL", + [VCAP_AF_PIPELINE_ACT] =3D "PIPELINE_ACT", [VCAP_AF_PIPELINE_FORCE_ENA] =3D "PIPELINE_FORCE_ENA", [VCAP_AF_PIPELINE_PT] =3D "PIPELINE_PT", [VCAP_AF_POLICE_ENA] =3D "POLICE_ENA", [VCAP_AF_POLICE_IDX] =3D "POLICE_IDX", [VCAP_AF_POLICE_REMARK] =3D "POLICE_REMARK", [VCAP_AF_POLICE_VCAP_ONLY] =3D "POLICE_VCAP_ONLY", + [VCAP_AF_POP_VAL] =3D "POP_VAL", [VCAP_AF_PORT_MASK] =3D "PORT_MASK", + [VCAP_AF_PUSH_CUSTOMER_TAG] =3D "PUSH_CUSTOMER_TAG", + [VCAP_AF_PUSH_INNER_TAG] =3D "PUSH_INNER_TAG", + [VCAP_AF_PUSH_OUTER_TAG] =3D "PUSH_OUTER_TAG", [VCAP_AF_QOS_ENA] =3D "QOS_ENA", [VCAP_AF_QOS_VAL] =3D "QOS_VAL", [VCAP_AF_REW_OP] =3D "REW_OP", [VCAP_AF_RT_DIS] =3D "RT_DIS", + [VCAP_AF_SWAP_MACS_ENA] =3D "SWAP_MACS_ENA", + [VCAP_AF_TAG_A_DEI_SEL] =3D "TAG_A_DEI_SEL", + [VCAP_AF_TAG_A_PCP_SEL] =3D "TAG_A_PCP_SEL", + [VCAP_AF_TAG_A_TPID_SEL] =3D "TAG_A_TPID_SEL", + [VCAP_AF_TAG_A_VID_SEL] =3D "TAG_A_VID_SEL", + [VCAP_AF_TAG_B_DEI_SEL] =3D "TAG_B_DEI_SEL", + [VCAP_AF_TAG_B_PCP_SEL] =3D "TAG_B_PCP_SEL", + [VCAP_AF_TAG_B_TPID_SEL] =3D "TAG_B_TPID_SEL", + [VCAP_AF_TAG_B_VID_SEL] =3D "TAG_B_VID_SEL", + [VCAP_AF_TAG_C_DEI_SEL] =3D "TAG_C_DEI_SEL", + [VCAP_AF_TAG_C_PCP_SEL] =3D "TAG_C_PCP_SEL", + [VCAP_AF_TAG_C_TPID_SEL] =3D "TAG_C_TPID_SEL", + [VCAP_AF_TAG_C_VID_SEL] =3D "TAG_C_VID_SEL", [VCAP_AF_TYPE] =3D "TYPE", + [VCAP_AF_UNTAG_VID_ENA] =3D "UNTAG_VID_ENA", + [VCAP_AF_VID_A_VAL] =3D "VID_A_VAL", + [VCAP_AF_VID_B_VAL] =3D "VID_B_VAL", + [VCAP_AF_VID_C_VAL] =3D "VID_C_VAL", [VCAP_AF_VID_VAL] =3D "VID_VAL", }; =20 diff --git a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.h b/drive= rs/net/ethernet/microchip/vcap/vcap_model_kunit.h index b5a74f0eef9b..55762f24e196 100644 --- a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.h +++ b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. +/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries. * Microchip VCAP test model interface for kunit testing */ =20 +/* This file is autogenerated by cml-utils 2023-02-10 11:16:00 +0100. + * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada + */ + #ifndef __VCAP_MODEL_KUNIT_H__ #define __VCAP_MODEL_KUNIT_H__ + +/* VCAPs */ extern const struct vcap_info kunit_test_vcaps[]; extern const struct vcap_statistics kunit_test_vcap_stats; + #endif /* __VCAP_MODEL_KUNIT_H__ */ + --=20 2.39.1