From nobody Fri Sep 12 02:25:16 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2AF6C61DA4 for ; Tue, 14 Feb 2023 09:28:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232427AbjBNJ2X (ORCPT ); Tue, 14 Feb 2023 04:28:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232372AbjBNJ2C (ORCPT ); Tue, 14 Feb 2023 04:28:02 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09A8825285 for ; Tue, 14 Feb 2023 01:27:24 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id r2so14914187wrv.7 for ; Tue, 14 Feb 2023 01:27:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yv8IAedTIIyQacPC2rWyTL/uMmzGJUZpAZ3MenFek+Q=; b=zn0CFKMh5UaxmMLb1+nmdeN2PG3bInGGMBh93fZjiyWsgWgTiH0ttWVR0V5kNh11TL oQnFc94MqPQVkNX9Wy9+JMARqh2lGyDpVg73a8PZ+2gvGrPeyO5XKurtu+vAtq2oDMwU ACCC6dJapGVqWkfBSsf5Obm25kUMN46SxN6RL6VwzeVF9FJ082HxKu4r4I7/LLJDqQ6V HzZp+vHkhafOx/1lweMWbP4bqGx3Y9RdlGpFW3cx22aL7B/epjmxyiyGxE3n+QMds+eg ZHOsf/qWbVQm7gI8aw8lRZlg055p7qV8eh79ir9IL5GrYu6I70EBbfeJWUjxIYdCgMSC Cxtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yv8IAedTIIyQacPC2rWyTL/uMmzGJUZpAZ3MenFek+Q=; b=qEd2QGEkSv6Fz0VC4Rs1qjs96SffZTl8c4+EB/eUVQN3xhTqR7BziM6a8ngaVmFYfD MThLqAceNlC8Bzywm1NA9dIDUKXJIcqhK0wXz3DNiNR6K4o7zBXEUHG2aqHMUdWnTduK WBZjvwMXiBpdo9xBdKzkEZbk2/hU9jmK3tWs5VszIizRHKLS3k5Ev+Tfa2vksvii/NrJ dF0Y2hWxDzidguKqgrHm3S3+H0q89fsmwjhPG34dMGC6Cw5gMZeIuBDg6Yr3xTpRzd38 mVlA2GJe5qgIF6W3Kh2uPBz9D9YlehqwtuN/nq32qEsJ9R3FfOULhJLdBTFzJUNUnhg9 GVVQ== X-Gm-Message-State: AO0yUKXvUQHfr+dzdbSoApOcTBXzvbP7eABd8w14TAc/vrnFERd3SqVd rsNPTUmfVNRM7Mt72/txCjncyA== X-Google-Smtp-Source: AK7set/fnnl30PpaLE4exuY8KzSt7RDSlzsiTwNNpEeixwCu22P3EXNtRPUNDPIorQMfdPb1+gGWpw== X-Received: by 2002:adf:cd08:0:b0:2c5:5a63:ae07 with SMTP id w8-20020adfcd08000000b002c55a63ae07mr1544475wrm.23.1676366839213; Tue, 14 Feb 2023 01:27:19 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:6e4b:bef:7edd:1af1]) by smtp.gmail.com with ESMTPSA id k2-20020a5d6d42000000b002c4061a687bsm12687602wri.31.2023.02.14.01.27.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 01:27:18 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Jassi Brar , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski , Krzysztof Kozlowski Subject: [PATCH v4 1/2] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform Date: Tue, 14 Feb 2023 10:27:12 +0100 Message-Id: <20230214092713.211054-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230214092713.211054-1-brgl@bgdev.pl> References: <20230214092713.211054-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Add a compatible for the ipcc on sa8775p platforms. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Doc= umentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index f5c73437fef4..de56640cecca 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-ipcc - qcom,sc7280-ipcc - qcom,sc8280xp-ipcc - qcom,sm6350-ipcc --=20 2.37.2 From nobody Fri Sep 12 02:25:16 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D95BC05027 for ; Tue, 14 Feb 2023 09:28:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232465AbjBNJ20 (ORCPT ); Tue, 14 Feb 2023 04:28:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232187AbjBNJ2G (ORCPT ); Tue, 14 Feb 2023 04:28:06 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD72025944 for ; Tue, 14 Feb 2023 01:27:29 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id h16so14895432wrz.12 for ; Tue, 14 Feb 2023 01:27:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OLnTx59NJ3VviyWQ3ril47MANBC6mNYC5hO8upPv+Ss=; b=BAdT2V46MOc9gi6kBVvm0e2uMkLvJYb1szloJ27GuavepQGOdYQDL9/PxaFbDk8BnQ UtvmiuEMXHWtA+0W7vUcWKS+LJ8Pstn6O46fxw50DLcxNK77Gw2RbC9xhQNb+kRaxXGp dFQ2v/ClGgFGPLqYMNQ0s6H4y7nVNVg+TAFAz7D4XIgxT5tryhVQGXEk1dp1hi6KM6ja Bu0IEarb5MlY/xYQ+x21TWq7Z+NY7hmREyYjUZjMOKmzUIMEvRGPqDH09AGS9KePCK7m O5jgzSqDwgomIV0UTSRaolgZWoBRaSDqSeENkTgBTR/lwpzgjF1gWXD0rWNxcbABwDGj 5QRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OLnTx59NJ3VviyWQ3ril47MANBC6mNYC5hO8upPv+Ss=; b=U3NtnlcBbk4INlXOUziJpAKyuQATWAp8jGy1TseIAVwAZa37uhWbURVpGlt/FGF/uI 5w79MwOrFVioLdimO1K7jcEyffqSpDHKqeV526braIUtfKstdyGCb3Ci5+5bupF3gwRz ya6cT6iIRCTnOp9QgkR8md7Tu4i5mxDj1kXGmK9wky3yhk9i/ZBebvCcN70dlCyp9CXq FDAteaALY4Pni42qUGG6yQ0ibVb+jR+OzT1nGokMBoDmdN3zetkCQ0zYWFYy5WAvdPUH Q3n/qF9ZgdD76bBI15mdGWPwiPqxm1TDg5vIipgv3D6MdAU8ycLbh0MVL0hdTWGFLWUs c3Tg== X-Gm-Message-State: AO0yUKVT3JYuIeB360Trh0UlJjBjiVt6ctPue+LsoQuoM/c9zl/dBTD0 1uclOAGp5UlThZZV4iTpLdt25A== X-Google-Smtp-Source: AK7set9nSU/zLSCQV4KdhxbL7DXRL9g5P+Zmi3gCf5QxH3ki01R3FWXOcR0DwaM//K/ViYq5fDi+aQ== X-Received: by 2002:a5d:6a0d:0:b0:2c5:519d:7993 with SMTP id m13-20020a5d6a0d000000b002c5519d7993mr1482814wru.27.1676366840132; Tue, 14 Feb 2023 01:27:20 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:6e4b:bef:7edd:1af1]) by smtp.gmail.com with ESMTPSA id k2-20020a5d6d42000000b002c4061a687bsm12687602wri.31.2023.02.14.01.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 01:27:19 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Jassi Brar , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride Date: Tue, 14 Feb 2023 10:27:13 +0100 Message-Id: <20230214092713.211054-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230214092713.211054-1-brgl@bgdev.pl> References: <20230214092713.211054-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski This adds basic support for the Qualcomm sa8775p platform and the reference board: sa8775p-ride. The dt files describe the basics of the SoC and enable booting to shell. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++ 3 files changed, 853 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 31aa54f0428c..b63cd1861e68 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8540p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8775p-ride.dts new file mode 100644 index 000000000000..3adf7349f4e5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sa8775p.dtsi" + +/ { + model =3D "Qualcomm SA8775P Ride"; + compatible =3D "qcom,sa8775p-ride", "qcom,sa8775p"; + + aliases { + serial0 =3D &uart10; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&tlmm { + qup_uart10_default: qup-uart10-state { + pins =3D "gpio46", "gpio47"; + function =3D "qup1_se3"; + }; +}; + +&uart10 { + compatible =3D "qcom,geni-debug-uart"; + pinctrl-0 =3D <&qup_uart10_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi new file mode 100644 index 000000000000..565c1376073e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -0,0 +1,805 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + L2_0: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + L3_0: l3-cache { + compatible =3D "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_1>; + L2_1: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_2>; + L2_2: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_3>; + L2_3: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_0>; + }; + }; + + CPU4: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10000>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_4>; + L2_4: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_1>; + L3_1: l3-cache { + compatible =3D "cache"; + }; + + }; + }; + + CPU5: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_5>; + L2_5: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_1>; + }; + }; + + CPU6: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10200>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_6>; + L2_6: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_1>; + }; + }; + + CPU7: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10300>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_7>; + L2_7: l2-cache { + compatible =3D "cache"; + next-level-cache =3D <&L3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&CPU4>; + }; + + core1 { + cpu =3D <&CPU5>; + }; + + core2 { + cpu =3D <&CPU6>; + }; + + core3 { + cpu =3D <&CPU7>; + }; + }; + }; + }; + + firmware { + scm { + compatible =3D "qcom,scm-sa8775p", "qcom,scm"; + }; + }; + + aggre1_noc: interconnect-aggre1-noc { + compatible =3D "qcom,sa8775p-aggre1-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible =3D "qcom,sa8775p-aggre2-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,sa8775p-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible =3D "qcom,sa8775p-config-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible =3D "qcom,sa8775p-dc-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible =3D "qcom,sa8775p-gem-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect-gpdsp-anoc { + compatible =3D "qcom,sa8775p-gpdsp-anoc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect-lpass-ag-noc { + compatible =3D "qcom,sa8775p-lpass-ag-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible =3D "qcom,sa8775p-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible =3D "qcom,sa8775p-mmss-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible =3D "qcom,sa8775p-nspa-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible =3D "qcom,sa8775p-nspb-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect-pcie-anoc { + compatible =3D "qcom,sa8775p-pcie-anoc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible =3D "qcom,sa8775p-system-noc"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + /* Will be updated by the bootloader. */ + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + sail_ss_mem: sail-ss@80000000 { + reg =3D <0x0 0x80000000 0x0 0x10000000>; + no-map; + }; + + hyp_mem: hyp@90000000 { + reg =3D <0x0 0x90000000 0x0 0x600000>; + no-map; + }; + + xbl_boot_mem: xbl-boot@90600000 { + reg =3D <0x0 0x90600000 0x0 0x200000>; + no-map; + }; + + aop_image_mem: aop-image@90800000 { + reg =3D <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@90860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + uefi_log: uefi-log@908b0000 { + reg =3D <0x0 0x908b0000 0x0 0x10000>; + no-map; + }; + + reserved_mem: reserved@908f0000 { + reg =3D <0x0 0x908f0000 0x0 0xf000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908ff000 { + reg =3D <0x0 0x908ff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: cpucp-fw@90b00000 { + reg =3D <0x0 0x90b00000 0x0 0x100000>; + no-map; + }; + + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { + reg =3D <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { + reg =3D <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg =3D <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg =3D <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg =3D <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg =3D <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg =3D <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg =3D <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg =3D <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg =3D <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg =3D <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg =3D <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + tz_stat_mem: tz-stat@d0000000 { + reg =3D <0x0 0xd0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg =3D <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg =3D <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1800000 { + reg =3D <0x0 0xd1800000 0x0 0x3900000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,sa8775p-gcc"; + reg =3D <0x0 0x100000 0x0 0xc7018>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains =3D <&rpmhpd SA8775P_CX>; + }; + + ipcc: mailbox@408000 { + compatible =3D "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x408000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0xac0000 0x0 0x6000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus =3D <&apps_smmu 0x443 0x0>; + status =3D "disabled"; + + uart10: serial@a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + status =3D "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells =3D <3>; + interrupts =3D ; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17c21000 { + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@17c23000 { + reg =3D <0x17c23000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + status =3D "disabled"; + }; + + frame@17c25000 { + reg =3D <0x17c25000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + status =3D "disabled"; + }; + + frame@17c27000 { + reg =3D <0x17c27000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + status =3D "disabled"; + }; + + frame@17c29000 { + reg =3D <0x17c29000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + status =3D "disabled"; + }; + + frame@17c2b000 { + reg =3D <0x17c2b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + status =3D "disabled"; + }; + + frame@17c2d000 { + reg =3D <0x17c2d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , + , + , + ; + label =3D "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sa8775p-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,sa8775p-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level =3D ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level =3D ; + }; + }; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,sa8775p-tlmm"; + reg =3D <0x0 0xf000000 0x0 0x1000000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 149>; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + arch_timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.37.2