From nobody Thu Nov 14 06:50:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9705AC05027 for ; Mon, 13 Feb 2023 03:38:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229981AbjBMDil (ORCPT ); Sun, 12 Feb 2023 22:38:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229854AbjBMDiS (ORCPT ); Sun, 12 Feb 2023 22:38:18 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B01BDBC3; Sun, 12 Feb 2023 19:38:14 -0800 (PST) X-UUID: d2b27be2ab4f11eda06fc9ecc4dadd91-20230213 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=aJL5WwuNkLLAmjwNWyIG/SEF2/AxJaZzO9N8ums8eME=; b=JTaSAQ6GS0v4aFf0gUPiBsI4J4NrcQoLgzUuvxUzTBo9iWLIqg7bG6IpBuE6XEE1sS9VfeTeCoRr9AmAgwoHQXmKMvl2h6yWBGM7qgt9SFCoStWE+ROXx/AYFQAS92YLisExDQckMQ0OVeuYQDRSORaFwX6w3fuMUCenOlWQIGw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:c0627788-989e-4ee5-9bfa-50d9b2c517e4,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.19,REQID:c0627788-989e-4ee5-9bfa-50d9b2c517e4,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:885ddb2,CLOUDID:786ead8e-8530-4eff-9f77-222cf6e2895b,B ulkID:230213113807VPHMUHJI,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: d2b27be2ab4f11eda06fc9ecc4dadd91-20230213 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 161831734; Mon, 13 Feb 2023 11:38:04 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 13 Feb 2023 11:38:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 13 Feb 2023 11:38:03 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v6 03/12] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Date: Mon, 13 Feb 2023 11:37:49 +0800 Message-ID: <20230213033758.16681-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230213033758.16681-1-tinghan.shen@mediatek.com> References: <20230213033758.16681-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the SCP binding to describe the MT8195 dual-core SCP. Under different applications, the MT8195 SCP can be used as single-core or dual-core. This change keeps the single-core definition and adds new definitions for dual-core use case. Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/remoteproc/mtk,scp.yaml | 145 +++++++++++++++++- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Do= cumentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 271081df0e46..09102dda4942 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt8188-scp - mediatek,mt8192-scp - mediatek,mt8195-scp + - mediatek,mt8195-scp-dual =20 reg: description: @@ -31,10 +32,7 @@ properties: =20 reg-names: minItems: 2 - items: - - const: sram - - const: cfg - - const: l1tcm + maxItems: 3 =20 clocks: description: @@ -70,6 +68,81 @@ properties: =20 unevaluatedProperties: false =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: + description: + Standard ranges definition providing address translations for + local SCP SRAM address spaces to bus addresses. + +patternProperties: + "^scp@[a-f0-9]+$": + type: object + description: + The MediaTek SCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address sp= ace + for the processor. + + Each SCP core has own cache memory. The SRAM and L1TCM are shared by + cores. The power of cache, SRAM and L1TCM power should be enabled + before booting SCP cores. The size of cache, SRAM, and L1TCM are var= ied + on differnt SoCs. + + The SCP cores do not use an MMU, but has a set of registers to + control the translations between 32-bit CPU addresses into system bus + addresses. Cache and memory access settings are provided through a + Memory Protection Unit (MPU), programmable only from the SCP. + + properties: + compatible: + enum: + - mediatek,scp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing sub cores of multi-core SCP. + + memory-region: + maxItems: 1 + + cros-ec-rpmsg: + $ref: /schemas/mfd/google,cros-ec.yaml + description: + This subnode represents the rpmsg device. The properties + of this node are defined by the individual bindings for + the rpmsg devices. + + required: + - mediatek,rpmsg-name + + unevaluatedProperties: false + + required: + - compatible + - reg + - reg-names + + additionalProperties: false + required: - compatible - reg @@ -99,7 +172,37 @@ allOf: reg: maxItems: 2 reg-names: + items: + - const: sram + - const: cfg + - if: + properties: + compatible: + enum: + - mediatek,mt8192-scp + - mediatek,mt8195-scp + then: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: sram + - const: cfg + - const: l1tcm + - if: + properties: + compatible: + enum: + - mediatek,mt8195-scp-dual + then: + properties: + reg: maxItems: 2 + reg-names: + items: + - const: cfg + - const: l1tcm =20 additionalProperties: false =20 @@ -121,3 +224,37 @@ examples: mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; }; + + - | + scp@10500000 { + compatible =3D "mediatek,mt8195-scp-dual"; + reg =3D <0x10720000 0xe0000>, + <0x10700000 0x8000>; + reg-names =3D "cfg", "l1tcm"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x10500000 0x100000>; + + scp@0 { + compatible =3D "mediatek,scp-core"; + reg =3D <0x0 0xa0000>; + reg-names =3D "sram"; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; + }; + + scp@a0000 { + compatible =3D "mediatek,scp-core"; + reg =3D <0xa0000 0x20000>; + reg-names =3D "sram"; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; + }; + }; --=20 2.18.0