From nobody Sat Sep 21 03:09:47 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7700EC636D4 for ; Sun, 12 Feb 2023 21:42:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229677AbjBLVmH (ORCPT ); Sun, 12 Feb 2023 16:42:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229441AbjBLVmF (ORCPT ); Sun, 12 Feb 2023 16:42:05 -0500 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2055.outbound.protection.outlook.com [40.107.105.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6524DC678; Sun, 12 Feb 2023 13:42:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OWM2rjMfHX2zbIHge9XwgN4NyEHbItvn79FvOvIRdXZGCa9NiY4vzWaqtvt2wO6Qhy47zhqORuLOLp2UehTww0uBcSZY0ZPH/l2Y5jgxaQSoB7hRXjc3TZ4RTnhI5XxNBceLram6GzSEbB48pcn0CJ3jErvCLdO3/TF2WeNKXoWADKB+hsjJYDzrqTSfb2X3UM0itXguSrghLh4hTkG4WEGHAkUYQgA/qz59UP2DzfNSsqNx5Ji+gr2ekbwM/HIDMgqmN8U8b6X0FdT98cNnWyRkJbvF8jXqUJcT+SPc3Mx9ttK1kULjN7RVpaRPFp7lLLKRq2B8T+vwuA2AWEgp+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lqEZbnWlQOqLMsymQrXzwDxWrFiiFGuJ1rqroX7iqhg=; b=NP6yI4tbIq1hQmLiAItMfTyVoYNNAWyikvkRcKr1PIp7/B96K3nNzgEPsWDK5gbZGJY+FD99xhFWEOJYPcyQX99j1oo/mz3voO7pNp8hNDR+Vpn3o8YVRhmUOMGXZ5m2XHFYv0Sbmfnc+oSxL8iWy+uaW1WwiYD7L/9WZWovG/7DOEOAeodDdh0uQn/vbmop+kGYPJ5ixdoRnhN/TxA0m+lQg5LT7fqL5IxpXDiep/C69ViA4EAnuOXuFQXTHgya1MIcBNEK+qb9cKT2hjqd/pC4zeC3SULvx6S8r5faVoID7VgoqXElwj2hvhbPD/XpExHDMJ3FfYW8xoCE9ag8sQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=routerhints.com; dmarc=pass action=none header.from=routerhints.com; dkim=pass header.d=routerhints.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=routerhints.com; Received: from VE1PR04MB7454.eurprd04.prod.outlook.com (2603:10a6:800:1a8::7) by VI1PR04MB7149.eurprd04.prod.outlook.com (2603:10a6:800:12e::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.23; Sun, 12 Feb 2023 21:41:58 +0000 Received: from VE1PR04MB7454.eurprd04.prod.outlook.com ([fe80::e4a3:a727:5246:a5cd]) by VE1PR04MB7454.eurprd04.prod.outlook.com ([fe80::e4a3:a727:5246:a5cd%9]) with mapi id 15.20.6086.023; Sun, 12 Feb 2023 21:41:58 +0000 From: Richard van Schagen To: Sean Wang , Landen Chao , DENG Qingfang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Arinc Unal , Frank Wunderlich Cc: Richard van Schagen , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH] Fix setting up CPU and User ports to be in the correct mode during setup and when toggling vlan_filtering on a bridge port. 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charset="utf-8" --- drivers/net/dsa/mt7530.c | 124 ++++++++++++++------------------------- 1 file changed, 43 insertions(+), 81 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 3a15015bc409..f98a94361c84 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1027,6 +1027,12 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE); =20 + mt7530_rmw(priv, MT7530_PVC_P(port), + VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, + VLAN_ATTR(MT7530_VLAN_USER) | + PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | + MT7530_VLAN_ACC_ALL); + return 0; } =20 @@ -1229,10 +1235,6 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int p= ort, PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); priv->ports[port].pm |=3D PCR_MATRIX(port_bitmap); =20 - /* Set to fallback mode for independent VLAN learning */ - mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, - MT7530_PORT_FALLBACK_MODE); - mutex_unlock(&priv->reg_mutex); =20 return 0; @@ -1242,15 +1244,6 @@ static void mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) { struct mt7530_priv *priv =3D ds->priv; - bool all_user_ports_removed =3D true; - int i; - - /* This is called after .port_bridge_leave when leaving a VLAN-aware - * bridge. Don't set standalone ports to fallback mode. - */ - if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) - mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, - MT7530_PORT_FALLBACK_MODE); =20 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, @@ -1261,27 +1254,6 @@ mt7530_port_set_vlan_unaware(struct dsa_switch *ds, = int port) /* Set PVID to 0 */ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, G0_PORT_VID_DEF); - - for (i =3D 0; i < MT7530_NUM_PORTS; i++) { - if (dsa_is_user_port(ds, i) && - dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { - all_user_ports_removed =3D false; - break; - } - } - - /* CPU port also does the same thing until all user ports belonging to - * the CPU port get out of VLAN filtering mode. - */ - if (all_user_ports_removed) { - struct dsa_port *dp =3D dsa_to_port(ds, port); - struct dsa_port *cpu_dp =3D dp->cpu_dp; - - mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), - PCR_MATRIX(dsa_user_ports(priv->ds))); - mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG - | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); - } } =20 static void @@ -1292,36 +1264,24 @@ mt7530_port_set_vlan_aware(struct dsa_switch *ds, i= nt port) /* Trapped into security mode allows packet forwarding through VLAN * table lookup. */ - if (dsa_is_user_port(ds, port)) { - mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, - MT7530_PORT_SECURITY_MODE); - mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, - G0_PORT_VID(priv->ports[port].pvid)); + mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, + MT7530_PORT_SECURITY_MODE); + mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, + G0_PORT_VID(priv->ports[port].pvid)); =20 - /* Only accept tagged frames if PVID is not set */ - if (!priv->ports[port].pvid) - mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, - MT7530_VLAN_ACC_TAGGED); + /* Only accept tagged frames if PVID is not set */ + if (!priv->ports[port].pvid) + mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, + MT7530_VLAN_ACC_TAGGED); =20 - /* Set the port as a user port which is to be able to recognize - * VID from incoming packets before fetching entry within the - * VLAN table. - */ - mt7530_rmw(priv, MT7530_PVC_P(port), - VLAN_ATTR_MASK | PVC_EG_TAG_MASK, - VLAN_ATTR(MT7530_VLAN_USER) | - PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); - } else { - /* Also set CPU ports to the "user" VLAN port attribute, to - * allow VLAN classification, but keep the EG_TAG attribute as - * "consistent" (i.o.w. don't change its value) for packets - * received by the switch from the CPU, so that tagged packets - * are forwarded to user ports as tagged, and untagged as - * untagged. - */ - mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, - VLAN_ATTR(MT7530_VLAN_USER)); - } + /* Set the port as a user port which is to be able to recognize + * VID from incoming packets before fetching entry within the + * VLAN table. + */ + mt7530_rmw(priv, MT7530_PVC_P(port), + VLAN_ATTR_MASK | PVC_EG_TAG_MASK, + VLAN_ATTR(MT7530_VLAN_USER) | + PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); } =20 static void @@ -1526,20 +1486,11 @@ static int mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filt= ering, struct netlink_ext_ack *extack) { - struct dsa_port *dp =3D dsa_to_port(ds, port); - struct dsa_port *cpu_dp =3D dp->cpu_dp; - - if (vlan_filtering) { - /* The port is being kept as VLAN-unaware port when bridge is - * set up with vlan_filtering not being set, Otherwise, the - * port and the corresponding CPU port is required the setup - * for becoming a VLAN-aware port. - */ + if (vlan_filtering) mt7530_port_set_vlan_aware(ds, port); - mt7530_port_set_vlan_aware(ds, cpu_dp->index); - } else { + else mt7530_port_set_vlan_unaware(ds, port); - } + =20 return 0; } @@ -2225,10 +2176,16 @@ mt7530_setup(struct dsa_switch *ds) /* Set default PVID to 0 on all user ports */ mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, G0_PORT_VID_DEF); + + mt7530_rmw(priv, MT7530_PVC_P(i), + VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, + VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | + PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | + MT7530_VLAN_ACC_ALL); + + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_PORT_VLAN_MASK, + MT7530_PORT_MATRIX_MODE); } - /* Enable consistent egress tag */ - mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, - PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); } =20 /* Setup VLAN ID 0 for VLAN-unaware bridges */ @@ -2412,11 +2369,16 @@ mt7531_setup(struct dsa_switch *ds) /* Set default PVID to 0 on all user ports */ mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, G0_PORT_VID_DEF); - } =20 - /* Enable consistent egress tag */ - mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, - PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); + mt7530_rmw(priv, MT7530_PVC_P(i), + VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, + VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | + PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | + MT7530_VLAN_ACC_ALL); + + mt7530_rmw(priv, MT7530_PCR_P(i), PCR_PORT_VLAN_MASK, + MT7530_PORT_MATRIX_MODE); + } } =20 /* Setup VLAN ID 0 for VLAN-unaware bridges */ --=20 2.30.2