From nobody Fri Sep 12 08:58:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93CCBC636D4 for ; Sat, 11 Feb 2023 06:40:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229692AbjBKGkD (ORCPT ); Sat, 11 Feb 2023 01:40:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229696AbjBKGjx (ORCPT ); Sat, 11 Feb 2023 01:39:53 -0500 Received: from mail-oo1-xc2a.google.com (mail-oo1-xc2a.google.com [IPv6:2607:f8b0:4864:20::c2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CF60E3A6 for ; Fri, 10 Feb 2023 22:39:51 -0800 (PST) Received: by mail-oo1-xc2a.google.com with SMTP id r192-20020a4a37c9000000b00517677496d0so750438oor.13 for ; Fri, 10 Feb 2023 22:39:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hGLpsx3x56F4XExqZ+3YmAAyi85mUU1waCg5Al37KCU=; b=DDvBzjnkWpfUdwY/rg3cZnOUu1yzoDogUfZAj9PKlDg0d+bi2iRJAwo2/I8L4waloa yV8JoGtGvWKxVnUzAssHNflp2tHJBLPi0IVuB3pAozjIalNI+HoqJIWNum80Rg1yjxar uU5zIg3lHzWWvcs94fsLWAuaFrUu9pkKj4Av8LojcpFgiAZrbW8WntBJiqUT5mlen3oi a4fSEnlqpah0R3RIiXmq3QEfIy2m68z69lPe9/t44ZG0HnfsV4HBZN4tsmjWuGD/DN7m Cz5fESsBqIyKnykITNB2UmYZX1XDdohSMBLkxDp4zNV35FBx3HE/hMgeD7XKIHBPFq9r acBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hGLpsx3x56F4XExqZ+3YmAAyi85mUU1waCg5Al37KCU=; b=Ti1MYmhM8PqTQeAmzAilf6ldb/0z+MlvR0p3lDfUuUL7KMfrYD0KfLia005DxVwsc4 ZORhMOvXQNOaNrFDnWNansU5/0b6nQWuOaRfdwDI0sKlVlbQIjGr7qVqtkA85ZxQAhlA Kft6Od/vhmJy2bIr3oVZXxh9xev4OIpjwI7R2+Gw4oSBPZIUsYoeCfaosZoHONQJngfj Ozimvs2hUeJawsHr4JHZ3xuIl9lGoz7DL5mhBb8pbhkOwn6WcWuQYNnFsxCKgd6V4Jnq uEbsS+j3qoxrtXsaW0W6EUyE0pHHRKICbY1niJnAZZ5Prw5ZqTpYTq+IJYGpwFDpROeA bFcQ== X-Gm-Message-State: AO0yUKUNbR1yyc0TmtwddZygLFjHQboMiqgpiC4VkJxhuWUMGR+PM2mj Quml3k/RxIvHnmE3U1dLyTCuGQ== X-Google-Smtp-Source: AK7set/tShNgs95dQGGgbp9uDcpeqJIp3+i5sf5DZ8B+fDZhqHh5W/Si7avk5AdyR0qt4zd2I/7Y+A== X-Received: by 2002:a4a:e841:0:b0:51a:6572:152 with SMTP id m1-20020a4ae841000000b0051a65720152mr9616288oom.3.1676097590615; Fri, 10 Feb 2023 22:39:50 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id t5-20020a4adbc5000000b00511e01623bbsm2808013oou.7.2023.02.10.22.39.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 22:39:50 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Date: Sat, 11 Feb 2023 00:40:01 -0600 Message-Id: <20230211064006.14981-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211064006.14981-1-semen.protsenko@linaro.org> References: <20230211064006.14981-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D. Add clock indices and binding documentation for CMU_G3D. Signed-off-by: Sam Protsenko Acked-by: Rob Herring --- .../clock/samsung,exynos850-clock.yaml | 19 ++++++++++++++++++ include/dt-bindings/clock/exynos850.h | 20 ++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-cloc= k.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.ya= ml index 141cf173f87d..8aa87b8c1b33 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -37,6 +37,7 @@ properties: - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi - samsung,exynos850-cmu-is - samsung,exynos850-cmu-mfcmscl @@ -169,6 +170,24 @@ allOf: - const: oscclk - const: dout_dpu =20 + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/cl= ock/exynos850.h index 88d5289883d3..8bb62e43fd60 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -85,7 +85,10 @@ #define CLK_DOUT_MFCMSCL_M2M 73 #define CLK_DOUT_MFCMSCL_MCSC 74 #define CLK_DOUT_MFCMSCL_JPEG 75 -#define TOP_NR_CLK 76 +#define CLK_MOUT_G3D_SWITCH 76 +#define CLK_GOUT_G3D_SWITCH 77 +#define CLK_DOUT_G3D_SWITCH 78 +#define TOP_NR_CLK 79 =20 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +198,21 @@ #define CLK_GOUT_SYSREG_CMGP_PCLK 15 #define CMGP_NR_CLK 16 =20 +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 +#define CLK_MOUT_G3D_PLL 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_BUSD 4 +#define CLK_DOUT_G3D_BUSP 5 +#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 +#define CLK_GOUT_G3D_GPU_CLK 7 +#define CLK_GOUT_G3D_TZPC_PCLK 8 +#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 +#define CLK_GOUT_G3D_BUSD_CLK 10 +#define CLK_GOUT_G3D_BUSP_CLK 11 +#define CLK_GOUT_G3D_SYSREG_PCLK 12 +#define G3D_NR_CLK 13 + /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 #define CLK_MOUT_HSI_MMC_CARD_USER 2 --=20 2.39.1 From nobody Fri Sep 12 08:58:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97A0EC636CC for ; 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Fri, 10 Feb 2023 22:39:51 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks Date: Sat, 11 Feb 2023 00:40:02 -0600 Message-Id: <20230211064006.14981-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211064006.14981-1-semen.protsenko@linaro.org> References: <20230211064006.14981-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko Acked-by: Rob Herring --- include/dt-bindings/clock/exynos850.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/cl= ock/exynos850.h index 8bb62e43fd60..afacba338c91 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -178,7 +178,8 @@ #define IOCLK_AUDIOCDCLK5 58 #define IOCLK_AUDIOCDCLK6 59 #define TICK_USB 60 -#define AUD_NR_CLK 61 +#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 +#define AUD_NR_CLK 62 =20 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -227,7 +228,10 @@ #define CLK_GOUT_MMC_CARD_ACLK 11 #define CLK_GOUT_MMC_CARD_SDCLKIN 12 #define CLK_GOUT_SYSREG_HSI_PCLK 13 -#define HSI_NR_CLK 14 +#define CLK_GOUT_HSI_PPMU_ACLK 14 +#define CLK_GOUT_HSI_PPMU_PCLK 15 +#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 +#define HSI_NR_CLK 17 =20 /* CMU_IS */ #define CLK_MOUT_IS_BUS_USER 1 --=20 2.39.1 From nobody Fri Sep 12 08:58:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55C2EC61DA4 for ; Sat, 11 Feb 2023 06:40:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229534AbjBKGkJ (ORCPT ); Sat, 11 Feb 2023 01:40:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbjBKGjz (ORCPT ); Sat, 11 Feb 2023 01:39:55 -0500 Received: from mail-ot1-x32b.google.com (mail-ot1-x32b.google.com [IPv6:2607:f8b0:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2273C12F1E for ; Fri, 10 Feb 2023 22:39:53 -0800 (PST) Received: by mail-ot1-x32b.google.com with SMTP id g15-20020a9d6b0f000000b0068db1940216so2219892otp.5 for ; Fri, 10 Feb 2023 22:39:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+MhuA4Hcp/lVQHlfxLRLLaWYCwZ7dT0qzyi0BQVRFws=; b=zTCsyNP77wiVJv3iupkgRsZMAmonQDgktigW3x4DJrpXxijiGVEqAH0CPM0jF71wBl mwLHF55QSkg4nPda0vDmo8Vio/CfD0pS+yZMrIPrfZbOXr4RwERaB888ZU6Ugj4b7G7e SOz7Fjeo4ILbgu3xLu8xBl3vMNr/+MtzJ8cqZpI2yXZ3OY1cdm4f7LBEV8HL8KkoYR3T sjgVSbnzY9HAhrJuFP9ho2/1ud61y4auk77tAuD1RFtr7/y/ADO0OlGdCwDKy3DXKS+s HzcEf6xci1PO9f2y7+JHZKgXLdZBggYa1rXQCExpXiyUxOfW8jCikkVGhXJhbm1FQH3+ hYXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+MhuA4Hcp/lVQHlfxLRLLaWYCwZ7dT0qzyi0BQVRFws=; b=SGijHl2u8QW1ZsjUb/5x6XF4nXT9EqI8GPUJB0TMRdKdKUhy/M8pRw9agaxRDNbpOb 5PqkWVQGgWlUHO2sgzaIHFDUu67Rknnfq1ojFtQj8ifM9ah47Kjrg2bttJaYWBE3+Idy 0aQ+6LNsVcAnN44ivLOrmO3+Drf9SC9XDeY4kFr10NcX8MZ/G24rBkOUkuIOjMO/i7pf dCCrueP6hKGT9I217KZ4SVpZU1ZcstHq7xskSejukLPvWWBdHW+HdWyZGluQMa9m6cVP RYBSLTC5Hun4Ge/bZ6Yu9e9aZUc6L5QupJOOvs5SuK5WksgbNJzFuPWvFHTT7fubRZvZ 4khA== X-Gm-Message-State: AO0yUKV/Iqr9x57Gjx4U8ZRV8PTzIkv00ExhT86lBsw2B5whpvo+knuq Za2db3LcmA2dT1J3aJ0bCE2mjA== X-Google-Smtp-Source: AK7set8oP0z2amyZeEu8vK0HrPUNwIL+ou8GHPGpjd7EWl9Tg5BfdWHG2qtld2KBA5LK2H2enlzQXA== X-Received: by 2002:a05:6830:1449:b0:68b:d03b:5105 with SMTP id w9-20020a056830144900b0068bd03b5105mr9193605otp.8.1676097592473; Fri, 10 Feb 2023 22:39:52 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id d9-20020a056830044900b0068be372babfsm2948951otc.47.2023.02.10.22.39.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 22:39:52 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type Date: Sat, 11 Feb 2023 00:40:03 -0600 Message-Id: <20230211064006.14981-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211064006.14981-1-semen.protsenko@linaro.org> References: <20230211064006.14981-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise, pll0818x is the same as pll0822x. The only difference is: - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz) - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz) Add pll0818x type as an alias to pll0822x. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- drivers/clk/samsung/clk-pll.c | 1 + drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5ceac4c25c1c..74934c6182ce 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, init.ops =3D &samsung_pll35xx_clk_ops; break; case pll_1417x: + case pll_0818x: case pll_0822x: pll->enable_offs =3D PLL0822X_ENABLE_SHIFT; pll->lock_offs =3D PLL0822X_LOCK_STAT_SHIFT; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 5d5a58d40e7e..0725d485c6ee 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -34,6 +34,7 @@ enum samsung_pll_type { pll_1451x, pll_1452x, pll_1460x, + pll_0818x, pll_0822x, pll_0831x, pll_142xx, --=20 2.39.1 From nobody Fri Sep 12 08:58:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84E41C636CC for ; Sat, 11 Feb 2023 06:40:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229767AbjBKGkL (ORCPT ); Sat, 11 Feb 2023 01:40:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229775AbjBKGj4 (ORCPT ); Sat, 11 Feb 2023 01:39:56 -0500 Received: from mail-oi1-x231.google.com (mail-oi1-x231.google.com [IPv6:2607:f8b0:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD6CCC65D for ; Fri, 10 Feb 2023 22:39:53 -0800 (PST) Received: by mail-oi1-x231.google.com with SMTP id bd6so6262864oib.6 for ; Fri, 10 Feb 2023 22:39:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lnwh8PvzH4M3fqQVoLT90tP2lhDK7TTHHkCgxq6i/js=; b=Ol6JWk7nCP20i/OqMHlNDkpa69RwMDOCqCohAXIm1V74QS7VxtD01TAflem6jRNV8v AjWaxemfOtP1iZPXfM4kFjAFbsuvcIjqpVSIX6eVOt7FSPHRaefnfTVx7iKGjBFKClFX k3ar/iZ8J3Hmj8mKjqTYrnMfjHSJhBkODhJLNY3dES/Y+3b/u1PTMebtQZIas0Ra6YdZ K7RnZNK3gIhnuyB4Fdigrp2idDAjT7xS6SLABgYi3qaw7OgiU+Qch7mkOKAkPWn3oSWt Aqhxzt5SP37oobrsvYIfGavADqykX0ihTJqhk5VjT09prNB1ypJ2jGr4BVh2qxx8alcb fiVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lnwh8PvzH4M3fqQVoLT90tP2lhDK7TTHHkCgxq6i/js=; b=pRSnla6K3DkBLq2sJ64gcda7jspNqMQ6dPFXkg/GJXqYSTrcz8KuWdKlXCELxq4Lu/ RcC4VeWmAs/jib2o5Q2RaewY75vQiSglNOnV585V9yvb/96kQ7LnjYtcFbkWfX0Fb4Xt Gv1UES6KHk5e3lcFzsZp8c96vb40/WkwLgpKXXfCGzdPH36rQootlwcyrN7aJPm3PGmB if1DViFQuOm88Udupioxf+ZgJk/nUOMrY6m3/a5OW7i8sbWcmKiG/HnAgQm9nhSH1veK iUBlsm1w5DitLZzGj41/eesMQnq+HIY2iQGGOz0Qz0uS/JU3Xhfx6yDr4Xj5dNwxLNm+ 2ykQ== X-Gm-Message-State: AO0yUKVeeCG7eZdbKucKVY4FkPvP4HBxWtZYRcWkulPN1rBQN2TRdwgb ey86QCsv2XPq7c2EoflR/C3h7w== X-Google-Smtp-Source: AK7set9DRIgVl+UtYocAPknZ9Hw1v5tMCSYSKv0gIfztAkSSZa5qclC3niu2jcB0QVPTd9W/iyVGDA== X-Received: by 2002:aca:1015:0:b0:36d:ea30:7bdf with SMTP id 21-20020aca1015000000b0036dea307bdfmr7765530oiq.49.1676097593463; Fri, 10 Feb 2023 22:39:53 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id w17-20020a9d6751000000b0067781a9292asm2900899otm.2.2023.02.10.22.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 22:39:53 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain Date: Sat, 11 Feb 2023 00:40:04 -0600 Message-Id: <20230211064006.14981-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211064006.14981-1-semen.protsenko@linaro.org> References: <20230211064006.14981-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for BLK_G3D. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_G3D - all internal CMU_G3D clocks - leaf clocks for GPU, TZPC (TrustZone Protection Controller) and SysReg G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- drivers/clk/samsung/clk-exynos850.c | 121 ++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 541761e96aeb..a24eff42baae 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -36,6 +36,7 @@ #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 @@ -57,6 +58,7 @@ #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c #define CLK_CON_DIV_CLKCMU_DPU 0x1840 +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 @@ -84,6 +86,7 @@ #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c @@ -116,6 +119,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, CLK_CON_MUX_MUX_CLKCMU_DPU, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, @@ -137,6 +141,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, CLK_CON_DIV_CLKCMU_CORE_SSS, CLK_CON_DIV_CLKCMU_DPU, + CLK_CON_DIV_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_HSI_BUS, CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, CLK_CON_DIV_CLKCMU_HSI_USB20DRD, @@ -164,6 +169,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, CLK_CON_GAT_GATE_CLKCMU_DPU, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, @@ -216,6 +222,9 @@ PNAME(mout_core_mmc_embd_p) =3D { "oscclk", "dout_share= d0_div2", "oscclk", "oscclk" }; PNAME(mout_core_sss_p) =3D { "dout_shared0_div3", "dout_shared1_div3", "dout_shared0_div4", "dout_shared1_div4" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ +PNAME(mout_g3d_switch_p) =3D { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared1_div3" }; /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ PNAME(mout_hsi_bus_p) =3D { "dout_shared0_div2", "dout_shared1_div2" }; PNAME(mout_hsi_mmc_card_p) =3D { "oscclk", "dout_shared0_div2", @@ -283,6 +292,10 @@ static const struct samsung_mux_clock top_mux_clks[] _= _initconst =3D { MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), =20 + /* G3D */ + MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), + /* HSI */ MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), @@ -357,6 +370,10 @@ static const struct samsung_div_clock top_div_clks[] _= _initconst =3D { DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", CLK_CON_DIV_CLKCMU_DPU, 0, 4), =20 + /* G3D */ + DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch", + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), + /* HSI */ DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), @@ -417,6 +434,10 @@ static const struct samsung_gate_clock top_gate_clks[]= __initconst =3D { GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), =20 + /* G3D */ + GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch", + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), + /* HSI */ GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), @@ -992,6 +1013,103 @@ static const struct samsung_cmu_info cmgp_cmu_info _= _initconst =3D { .clk_name =3D "gout_clkcmu_cmgp_bus", }; =20 +/* ---- CMU_G3D ----------------------------------------------------------= --- */ + +/* Register Offset definitions for CMU_G3D (0x11400000) */ +#define PLL_LOCKTIME_PLL_G3D 0x0000 +#define PLL_CON0_PLL_G3D 0x0100 +#define PLL_CON3_PLL_G3D 0x010c +#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600 +#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000 +#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 +#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000 +#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004 +#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c +#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010 +#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024 +#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028 +#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c + + +static const unsigned long g3d_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_G3D, + PLL_CON0_PLL_G3D, + PLL_CON3_PLL_G3D, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, + CLK_CON_DIV_DIV_CLK_G3D_BUSP, + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, + CLK_CON_GAT_CLK_G3D_GPU_CLK, + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, +}; + +/* List of parent clocks for Muxes in CMU_G3D */ +PNAME(mout_g3d_pll_p) =3D { "oscclk", "fout_g3d_pll" }; +PNAME(mout_g3d_switch_user_p) =3D { "oscclk", "dout_g3d_switch" }; +PNAME(mout_g3d_busd_p) =3D { "mout_g3d_pll", "mout_g3d_switch_user" }; + +/* + * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set + * for that PLL by default, so set_rate operation would fail. + */ +static const struct samsung_pll_clock g3d_pll_clks[] __initconst =3D { + PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", + PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), +}; + +static const struct samsung_mux_clock g3d_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, + PLL_CON0_PLL_G3D, 4, 1), + MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", + mout_g3d_switch_user_p, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), + MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), +}; + +static const struct samsung_div_clock g3d_div_clks[] __initconst =3D { + DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd", + CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock g3d_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", + "dout_g3d_busp", + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd", + CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk", + "mout_g3d_busd", + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd", + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info g3d_cmu_info __initconst =3D { + .pll_clks =3D g3d_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(g3d_pll_clks), + .mux_clks =3D g3d_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(g3d_mux_clks), + .div_clks =3D g3d_div_clks, + .nr_div_clks =3D ARRAY_SIZE(g3d_div_clks), + .gate_clks =3D g3d_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(g3d_gate_clks), + .nr_clk_ids =3D G3D_NR_CLK, + .clk_regs =3D g3d_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(g3d_clk_regs), + .clk_name =3D "dout_g3d_switch", +}; + /* ---- CMU_HSI ----------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_HSI (0x13400000) */ @@ -1700,6 +1818,9 @@ static const struct of_device_id exynos850_cmu_of_mat= ch[] =3D { }, { .compatible =3D "samsung,exynos850-cmu-cmgp", .data =3D &cmgp_cmu_info, + }, { + .compatible =3D "samsung,exynos850-cmu-g3d", + .data =3D &g3d_cmu_info, }, { .compatible =3D "samsung,exynos850-cmu-hsi", .data =3D &hsi_cmu_info, --=20 2.39.1 From nobody Fri Sep 12 08:58:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F29B0C61DA4 for ; Sat, 11 Feb 2023 06:40:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229725AbjBKGkN (ORCPT ); Sat, 11 Feb 2023 01:40:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229787AbjBKGj5 (ORCPT ); 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Fri, 10 Feb 2023 22:39:54 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks Date: Sat, 11 Feb 2023 00:40:05 -0600 Message-Id: <20230211064006.14981-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211064006.14981-1-semen.protsenko@linaro.org> References: <20230211064006.14981-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index a24eff42baae..3d776d57cc8f 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info __ini= tconst =3D { #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst = =3D { CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] __= initconst =3D { }; =20 static const struct samsung_gate_clock aud_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", + "dout_aud_busd", + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", @@ -1117,12 +1122,15 @@ static const struct samsung_cmu_info g3d_cmu_info _= _initconst =3D { #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 @@ -1132,12 +1140,15 @@ static const unsigned long hsi_clk_regs[] __initcon= st =3D { PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, CLK_CON_MUX_MUX_CLK_HSI_RTC, + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, @@ -1163,6 +1174,9 @@ static const struct samsung_mux_clock hsi_mux_clks[] = __initconst =3D { }; =20 static const struct samsung_gate_clock hsi_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", + "mout_hsi_bus_user", + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", @@ -1177,6 +1191,10 @@ static const struct samsung_gate_clock hsi_gate_clks= [] __initconst =3D { GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", "mout_hsi_mmc_card_user", CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", "mout_hsi_bus_user", CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), --=20 2.39.1 From nobody Fri Sep 12 08:58:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDF34C636CC for ; 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Fri, 10 Feb 2023 22:39:55 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Chanwoo Choi , Sylwester Nawrocki , Rob Herring Cc: David Virag , Chanho Park , Alim Akhtar , Sumit Semwal , Tomasz Figa , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC Date: Sat, 11 Feb 2023 00:40:06 -0600 Message-Id: <20230211064006.14981-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211064006.14981-1-semen.protsenko@linaro.org> References: <20230211064006.14981-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add missing G3D clock domain to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index a38fe5129937..d67e98120313 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -245,6 +245,15 @@ cmu_peri: clock-controller@10030000 { "dout_peri_uart", "dout_peri_ip"; }; =20 + cmu_g3d: clock-controller@11400000 { + compatible =3D "samsung,exynos850-cmu-g3d"; + reg =3D <0x11400000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; + clock-names =3D "oscclk", "dout_g3d_switch"; + }; + cmu_apm: clock-controller@11800000 { compatible =3D "samsung,exynos850-cmu-apm"; reg =3D <0x11800000 0x8000>; --=20 2.39.1