From nobody Fri Sep 12 10:22:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E891FC05027 for ; Fri, 10 Feb 2023 15:10:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232482AbjBJPK1 (ORCPT ); Fri, 10 Feb 2023 10:10:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231902AbjBJPKY (ORCPT ); Fri, 10 Feb 2023 10:10:24 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05F2F3B3D4 for ; Fri, 10 Feb 2023 07:10:15 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id u10so4039211wmj.3 for ; Fri, 10 Feb 2023 07:10:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=0+nb49xfCO7TD3Kw+7mvNnwEcPqxWc5InnfsnZGnCRs=; b=Vf9PtwnuqpDb3fAhMflYECBHkp7KeCBtEl+u5e4CZLHluK63I/51FVapv1/EYp0ODv 3uWlEYgRD3tR9ihgjZQfL/UVF5+xyBQGahpE7piBa8f43rmOk0/darZ3iAzh2B2oY4ZQ 3RPyTj8KdeMSAyQ8vWWXCoYqF3is9+RVtHZ4u4EZBWoXNW8FtbjIKEtW6+3re5e1b2Di otYjLP/0wDcw5aFb6COJfdCqg4FIpd4Z0v6fH3tzScbp2Q8bxDFaTaL1K4y+mBoVL7l6 5Sa4wW7fvZ2ZAvFcDoZ5e19Aj/I+hzAvrSOHnm2G/I0SRw7rjqiBxI/m01u1liOdLTNt Rf5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=0+nb49xfCO7TD3Kw+7mvNnwEcPqxWc5InnfsnZGnCRs=; b=VKwNiXQ3ENi9ck6zzDl7smYr1Svdw0mR5iFjhjNHJNtU8tuatiBS/+/40xtvu5ndFM rpNzWODQ1L0U3F8C16fv8MRaVYDhtUChZ6V0yeomHG+nT6AG95O05ckBvautqYMVgkeD 5UKpaY59WwXOGhape3IdMJeW52H+V2l5OTuictD9JhirjDMCULg40abf1XWMw8+l8fe7 fW18nlAfk6LH8Q9UeY0ai07oBGTkBtD4P/ITYToQQdDMyzfP5t6YTm2Len3PUsfOsMVR 2IiJkPpP6bFa5Xw5B6k4cCE7F3paCFZue9hcN/AwGFyGAeWmgNg92lXsd+CGhw9Hk7L7 gtrw== X-Gm-Message-State: AO0yUKUE16DG2so/3Vbzq2uv92Qo+hLZwzmF3eS/TWyIOQl/+oeUrQOm OaWpZ3T7xDQqOVB6fEpV9Xll5Q== X-Google-Smtp-Source: AK7set8PgXQAjv0wyRo2U+xZEUpv6yGnZQRS3itBN5CqTvpSKRQOJRUkgpMti9J7JmvAwsTjZBymag== X-Received: by 2002:a05:600c:a692:b0:3df:d86d:797a with SMTP id ip18-20020a05600ca69200b003dfd86d797amr14892869wmb.25.1676041813610; Fri, 10 Feb 2023 07:10:13 -0800 (PST) Received: from linaro.org ([2a00:23c5:680a:d01:61c3:70d8:6500:e102]) by smtp.gmail.com with ESMTPSA id a1-20020a05600c348100b003db0ee277b2sm8587771wmq.5.2023.02.10.07.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 07:10:12 -0800 (PST) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, leo.yan@linaro.org, yabinc@google.com, Mike Leach Subject: [PATCH 1/3] coresight: Update timeout functions to allow return of test register value Date: Fri, 10 Feb 2023 15:10:06 +0000 Message-Id: <20230210151008.4587-2-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230210151008.4587-1-mike.leach@linaro.org> References: <20230210151008.4587-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Current coresight_timeout function spins on a bit on a test register, till bit value achieved or timeout hit. Add another function to return the full value of the register being tested. Signed-off-by: Mike Leach Reviewed-by: James Clark --- drivers/hwtracing/coresight/coresight-core.c | 50 +++++++++++++++----- include/linux/coresight.h | 10 +++- 2 files changed, 48 insertions(+), 12 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index d3bf82c0de1d..c4db111ab32b 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1456,32 +1456,37 @@ static void coresight_remove_conns(struct coresight= _device *csdev) } =20 /** - * coresight_timeout - loop until a bit has changed to a specific register - * state. + * coresight_timeout_retval - loop until a bit has changed to a specific r= egister + * state. Return final register value * @csa: coresight device access for the device * @offset: Offset of the register from the base of the device. * @position: the position of the bit of interest. * @value: the value the bit should have. + * @rval: the last read value of the register being tested. * * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if * TIMEOUT_US has elapsed, which ever happens first. */ -int coresight_timeout(struct csdev_access *csa, u32 offset, - int position, int value) +int coresight_timeout_retval(struct csdev_access *csa, u32 offset, + int position, int value, u32 *rval) { - int i; - u32 val; + int i, rc =3D -EAGAIN; + u32 val =3D 0; =20 for (i =3D TIMEOUT_US; i > 0; i--) { val =3D csdev_access_read32(csa, offset); /* waiting on the bit to go from 0 to 1 */ if (value) { - if (val & BIT(position)) - return 0; + if (val & BIT(position)) { + rc =3D 0; + goto return_rval; + } /* waiting on the bit to go from 1 to 0 */ } else { - if (!(val & BIT(position))) - return 0; + if (!(val & BIT(position))) { + rc =3D 0; + goto return_rval; + } } =20 /* @@ -1493,7 +1498,30 @@ int coresight_timeout(struct csdev_access *csa, u32 = offset, udelay(1); } =20 - return -EAGAIN; +return_rval: + *rval =3D val; + + return rc; +} +EXPORT_SYMBOL_GPL(coresight_timeout_retval); + +/** + * coresight_timeout - loop until a bit has changed to a specific register + * state + * @csa: coresight device access for the device + * @offset: Offset of the register from the base of the device. + * @position: the position of the bit of interest. + * @value: the value the bit should have. + * + * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if + * TIMEOUT_US has elapsed, which ever happens first. + */ +int coresight_timeout(struct csdev_access *csa, u32 offset, + int position, int value) +{ + u32 rval =3D 0; + + return coresight_timeout_retval(csa, offset, position, value, &rval); } EXPORT_SYMBOL_GPL(coresight_timeout); =20 diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f19a47b9bb5a..6b6b45ef6971 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -500,7 +500,8 @@ extern int coresight_enable(struct coresight_device *cs= dev); extern void coresight_disable(struct coresight_device *csdev); extern int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value); - +extern int coresight_timeout_retval(struct csdev_access *csa, u32 offset, + int position, int value, u32 *rval); extern int coresight_claim_device(struct coresight_device *csdev); extern int coresight_claim_device_unlocked(struct coresight_device *csdev); =20 @@ -536,6 +537,13 @@ static inline int coresight_timeout(struct csdev_acces= s *csa, u32 offset, return 1; } =20 +static inline int coresight_timeout_retval(struct csdev_access *csa, u32 o= ffset, + int position, int value, u32 *rval) +{ + *rval =3D 0; + return 1; +} + static inline int coresight_claim_device_unlocked(struct coresight_device = *csdev) { return -EINVAL; --=20 2.17.1 From nobody Fri Sep 12 10:22:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67345C636D7 for ; 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Fri, 10 Feb 2023 07:10:14 -0800 (PST) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, leo.yan@linaro.org, yabinc@google.com, Mike Leach Subject: [PATCH 2/3] coresight: tmc: Update error logging in tmc common functions Date: Fri, 10 Feb 2023 15:10:07 +0000 Message-Id: <20230210151008.4587-3-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230210151008.4587-1-mike.leach@linaro.org> References: <20230210151008.4587-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Enhance the error logging in the tmc_wait_for_tmcready() and tmc_flush_and_stop() to print key tmc register values on error conditions to improve hardware debug information. Signed-off-by: Mike Leach Reviewed-by: James Clark --- .../hwtracing/coresight/coresight-tmc-core.c | 37 +++++++++++++++---- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index c106d142e632..f048f450843d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -31,25 +31,36 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); =20 +#define TMC_WAIT_READY_FMT_STR "timeout while waiting for TMC to be Ready = [STS=3D0x%04x]\n" + int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa =3D &csdev->access; + u32 tmc_sts =3D 0; =20 /* Ensure formatter, unformatter and hardware fifo are empty */ - if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { - dev_err(&csdev->dev, - "timeout while waiting for TMC to be Ready\n"); + if (coresight_timeout_retval(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1, + &tmc_sts)) { + dev_err(&csdev->dev, TMC_WAIT_READY_FMT_STR, tmc_sts); return -EBUSY; } return 0; } =20 -void tmc_flush_and_stop(struct tmc_drvdata *drvdata) +int tmc_flush_and_stop(struct tmc_drvdata *drvdata) { struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa =3D &csdev->access; - u32 ffcr; + u32 ffcr, ffsr, tmc_sts; + int rc =3D 0; + + /* note any MemErr present when stopping TMC */ + tmc_sts =3D readl_relaxed(drvdata->base + TMC_STS); + if (tmc_sts & TMC_STS_MEMERR) + dev_err(&csdev->dev, + "MemErr detected before Manual Flush; STS[0x%02x]\n", + tmc_sts); =20 ffcr =3D readl_relaxed(drvdata->base + TMC_FFCR); ffcr |=3D TMC_FFCR_STOP_ON_FLUSH; @@ -57,12 +68,22 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata) ffcr |=3D BIT(TMC_FFCR_FLUSHMAN_BIT); writel_relaxed(ffcr, drvdata->base + TMC_FFCR); /* Ensure flush completes */ - if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { + if (coresight_timeout_retval(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0, + &ffcr)) { + ffsr =3D readl_relaxed(drvdata->base + TMC_FFSR); dev_err(&csdev->dev, - "timeout while waiting for completion of Manual Flush\n"); + "timeout while waiting for completion of Manual Flush\n"); + dev_err(&csdev->dev, + "regs: FFCR[0x%02x] FFSR[0x%02x] STS[0x%02x]\n", + ffcr, ffsr, tmc_sts); + rc =3D -EBUSY; } =20 - tmc_wait_for_tmcready(drvdata); + if (tmc_wait_for_tmcready(drvdata)) { + dev_err(&csdev->dev, "TMC ready error after Manual flush\n"); + rc =3D -EBUSY; + } + return rc; } =20 void tmc_enable_hw(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 01c0382a29c0..314f8244787f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -256,7 +256,7 @@ struct tmc_sg_table { =20 /* Generic functions */ int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); -void tmc_flush_and_stop(struct tmc_drvdata *drvdata); +int tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); 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Fri, 10 Feb 2023 07:10:16 -0800 (PST) Received: from linaro.org ([2a00:23c5:680a:d01:61c3:70d8:6500:e102]) by smtp.gmail.com with ESMTPSA id a1-20020a05600c348100b003db0ee277b2sm8587771wmq.5.2023.02.10.07.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 07:10:15 -0800 (PST) From: Mike Leach To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com, leo.yan@linaro.org, yabinc@google.com, Mike Leach Subject: [PATCH 3/3] coresight: etf: etr: Update logging around flush_and_stop() errors Date: Fri, 10 Feb 2023 15:10:08 +0000 Message-Id: <20230210151008.4587-4-mike.leach@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230210151008.4587-1-mike.leach@linaro.org> References: <20230210151008.4587-1-mike.leach@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Insert additional context around tmc_flush_and_stop() errors. Signed-off-by: Mike Leach Reviewed-by: James Clark --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 12 +++++++++--- drivers/hwtracing/coresight/coresight-tmc-etr.c | 8 ++++++-- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 0ab1f73c2d06..c8a4d4eff64f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -84,7 +84,9 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvd= ata) { CS_UNLOCK(drvdata->base); =20 - tmc_flush_and_stop(drvdata); + if (tmc_flush_and_stop(drvdata)) + dev_err(&drvdata->csdev->dev, + "Flush and stop error disabling ETB\n"); /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -146,7 +148,9 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvd= ata) =20 CS_UNLOCK(drvdata->base); =20 - tmc_flush_and_stop(drvdata); + if (tmc_flush_and_stop(drvdata)) + dev_err(&drvdata->csdev->dev, + "Flush and stop error disabling ETF\n"); tmc_disable_hw(drvdata); coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); @@ -492,7 +496,9 @@ static unsigned long tmc_update_etf_buffer(struct cores= ight_device *csdev, =20 CS_UNLOCK(drvdata->base); =20 - tmc_flush_and_stop(drvdata); + if (tmc_flush_and_stop(drvdata)) + dev_err(&drvdata->csdev->dev, + "Flush and stop error updating perf buffer\n"); =20 read_ptr =3D tmc_read_rrp(drvdata); write_ptr =3D tmc_read_rwp(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 918d461fcf4a..ceae6a093612 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1145,7 +1145,9 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *= drvdata) { CS_UNLOCK(drvdata->base); =20 - tmc_flush_and_stop(drvdata); + if (tmc_flush_and_stop(drvdata)) + dev_err(&drvdata->csdev->dev, + "Flush and stop error disabling ETR\n"); /* * When operating in sysFS mode the content of the buffer needs to be * read before the TMC is disabled. @@ -1548,7 +1550,9 @@ tmc_update_etr_buffer(struct coresight_device *csdev, =20 CS_UNLOCK(drvdata->base); =20 - tmc_flush_and_stop(drvdata); + if (tmc_flush_and_stop(drvdata)) + dev_err(&csdev->dev, + "Flush and Stop error updating perf buffer\n"); tmc_sync_etr_buf(drvdata); =20 CS_LOCK(drvdata->base); --=20 2.17.1