From nobody Sat Sep 21 07:42:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97000C636CC for ; Wed, 8 Feb 2023 10:46:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231152AbjBHKqT (ORCPT ); Wed, 8 Feb 2023 05:46:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230345AbjBHKqG (ORCPT ); Wed, 8 Feb 2023 05:46:06 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBE3448A0B; Wed, 8 Feb 2023 02:45:55 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id AC95E660209F; Wed, 8 Feb 2023 10:45:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675853141; bh=q3Ks3xCpv4XCuWtELbScLLMj0j/dhmkTbq/7OVCjIrs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZT3rh5G0RfvzFBq9vd7yUtHUlSJcPrjYnTbkD9tETEFa98yYaCN963PCGEzRPisRd qtFOy8Zyh3LHdlC98Fil1HNByz+xrMisDcR2eBYBa99gpcbD24g0lYaz8JKYHVmjV4 CJHaaBih2yN1aBUnLxnVIRSXIGw1nKraC0Y1vTBKHWarN9LNSVUeRr3jOixGGiTjlE VClmgVIxAsCVVeIbmUI5Ey6Hl38aOn6CubwBmZDdD6uErwM1yKCW8GesYk2q781Q5J Q1tA4X0AestvbWrdOyOVAxey9u1xX+sqa3pOuJtEJ6xna//2S0jRkeLn5iekomNZaR o45wXr2tEXVqQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, wenst@chromium.org Subject: [PATCH 08/16] arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain Date: Wed, 8 Feb 2023 11:45:19 +0100 Message-Id: <20230208104527.118929-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230208104527.118929-1-angelogioacchino.delregno@collabora.com> References: <20230208104527.118929-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mfg_ref_sel clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index a60120088d45..5b4bf2d1d584 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -499,8 +499,9 @@ power-domain@MT8192_POWER_DOMAIN_CONN { =20 power-domain@MT8192_POWER_DOMAIN_MFG0 { reg =3D ; - clocks =3D <&topckgen CLK_TOP_MFG_PLL_SEL>; - clock-names =3D "mfg"; + clocks =3D <&topckgen CLK_TOP_MFG_PLL_SEL>, + <&topckgen CLK_TOP_MFG_REF_SEL>; + clock-names =3D "mfg", "alt"; #address-cells =3D <1>; #size-cells =3D <0>; #power-domain-cells =3D <1>; --=20 2.39.1