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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT112.mail.protection.outlook.com (10.13.176.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6086.17 via Frontend Transport; Wed, 8 Feb 2023 07:36:32 +0000 Received: from BLR-5CG1133937.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 8 Feb 2023 01:36:28 -0600 From: Bharata B Rao To: , CC: , , , , , , , , , , , Bharata B Rao Subject: [RFC PATCH 1/5] x86/ibs: In-kernel IBS driver for page access profiling Date: Wed, 8 Feb 2023 13:05:29 +0530 Message-ID: <20230208073533.715-2-bharata@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208073533.715-1-bharata@amd.com> References: <20230208073533.715-1-bharata@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT112:EE_|CH0PR12MB5252:EE_ X-MS-Office365-Filtering-Correlation-Id: aac0a47c-063a-4ed3-3bd1-08db09a73364 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 07:36:32.8983 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aac0a47c-063a-4ed3-3bd1-08db09a73364 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT112.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5252 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use IBS (Instruction Based Sampling) feature present in AMD processors for memory access tracking. The access information obtained from IBS will be used in subsequent patches to drive NUMA balancing. An NMI handler is registered to obtain the IBS data. The handler does nothing much yet. It just filters out the non-useful samples and collects some stats. This patch just builds the framework and IBS execution sampling is enabled only in a subsequent patch. TODOs ----- 1. Perf also uses IBS. For the purpose of this prototype just disable the use of IBS in perf. This needs to be done cleanly. 2. Only the required MSR bits are defined here. About IBS --------- IBS can be programmed to provide data about instruction execution periodically. This is done by programming a desired sample count (number of ops) in a control register. When the programmed number of ops are dispatched, a micro-op gets tagged, various information about the tagged micro-op's execution is populated in IBS execution MSRs and an interrupt is raised. While IBS provides a lot of data for each sample, for the purpose of memory access profiling, we are interested in linear and physical address of the memory access that reached DRAM. Recent AMD processors provide further filtering where it is possible to limit the sampling to those ops that had an L3 miss which greately reduces the non-useful samples. While IBS provides capability to sample instruction fetch and execution, only IBS execution sampling is used here to collect data about memory accesses that occur during the instruction execution. More information about IBS is available in Sec 13.3 of AMD64 Architecture Programmer's Manual, Volume 2:System Programming which is present at: https://bugzilla.kernel.org/attachment.cgi?id=3D288923 Information about MSRs used for programming IBS can be found in Sec 2.1.14.4 of PPR Vol 1 for AMD Family 19h Model 11h B1 which is currently present at: https://www.amd.com/system/files/TechDocs/55901_0.25.zip Signed-off-by: Bharata B Rao --- arch/x86/events/amd/ibs.c | 6 ++ arch/x86/include/asm/msr-index.h | 12 +++ arch/x86/mm/Makefile | 1 + arch/x86/mm/ibs.c | 169 +++++++++++++++++++++++++++++++ include/linux/vm_event_item.h | 11 ++ mm/vmstat.c | 11 ++ 6 files changed, 210 insertions(+) create mode 100644 arch/x86/mm/ibs.c diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index da3f5ebac4e1..290e6d221844 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1512,6 +1512,12 @@ static __init int amd_ibs_init(void) { u32 caps; =20 + /* + * TODO: Find a clean way to disable perf IBS so that IBS + * can be used for NUMA balancing. + */ + return 0; + caps =3D __get_ibs_caps(); if (!caps) return -ENODEV; /* ibs not supported by the cpu */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 37ff47552bcb..443d4cf73366 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -593,6 +593,18 @@ /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e =20 +/* AMD IBS MSR bits */ +#define MSR_AMD64_IBSOPDATA2_DATASRC 0x7 +#define MSR_AMD64_IBSOPDATA2_DATASRC_DRAM 0x3 +#define MSR_AMD64_IBSOPDATA2_DATASRC_FAR_CCX_CACHE 0x5 + +#define MSR_AMD64_IBSOPDATA3_LDOP BIT_ULL(0) +#define MSR_AMD64_IBSOPDATA3_STOP BIT_ULL(1) +#define MSR_AMD64_IBSOPDATA3_DCMISS BIT_ULL(7) +#define MSR_AMD64_IBSOPDATA3_LADDR_VALID BIT_ULL(17) +#define MSR_AMD64_IBSOPDATA3_PADDR_VALID BIT_ULL(18) +#define MSR_AMD64_IBSOPDATA3_L2MISS BIT_ULL(20) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 =20 diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index c80febc44cd2..e74b95a57d86 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -27,6 +27,7 @@ endif obj-y :=3D init.o init_$(BITS).o fault.o ioremap.o extable.o mmap.o \ pgtable.o physaddr.o tlb.o cpu_entry_area.o maccess.o pgprot.o =20 +obj-$(CONFIG_NUMA_BALANCING) +=3D ibs.o obj-y +=3D pat/ =20 # Make sure __phys_addr has no stackprotector diff --git a/arch/x86/mm/ibs.c b/arch/x86/mm/ibs.c new file mode 100644 index 000000000000..411dba2a88d1 --- /dev/null +++ b/arch/x86/mm/ibs.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#include +#include /* TODO: Move defns like IBS_OP_ENABLE into no= n-perf header */ +#include + +static u64 ibs_config __read_mostly; + +static int ibs_overflow_handler(unsigned int cmd, struct pt_regs *regs) +{ + u64 ops_ctl, ops_data3, ops_data2; + u64 remote_access; + u64 laddr =3D -1, paddr =3D -1; + struct mm_struct *mm =3D current->mm; + + rdmsrl(MSR_AMD64_IBSOPCTL, ops_ctl); + + /* + * When IBS sampling period is reprogrammed via read-modify-update + * of MSR_AMD64_IBSOPCTL, overflow NMIs could be generated with + * IBS_OP_ENABLE not set. For such cases, return as HANDLED. + * + * With this, the handler will say "handled" for all NMIs that + * aren't related to this NMI. This stems from the limitation of + * having both status and control bits in one MSR. + */ + if (!(ops_ctl & IBS_OP_VAL)) + goto handled; + + wrmsrl(MSR_AMD64_IBSOPCTL, ops_ctl & ~IBS_OP_VAL); + + count_vm_event(IBS_NR_EVENTS); + + if (!mm) { + count_vm_event(IBS_KTHREAD); + goto handled; + } + + rdmsrl(MSR_AMD64_IBSOPDATA3, ops_data3); + + /* Load/Store ops only */ + if (!(ops_data3 & (MSR_AMD64_IBSOPDATA3_LDOP | + MSR_AMD64_IBSOPDATA3_STOP))) { + count_vm_event(IBS_NON_LOAD_STORES); + goto handled; + } + + /* Discard the sample if it was L1 or L2 hit */ + if (!(ops_data3 & (MSR_AMD64_IBSOPDATA3_DCMISS | + MSR_AMD64_IBSOPDATA3_L2MISS))) { + count_vm_event(IBS_DC_L2_HITS); + goto handled; + } + + rdmsrl(MSR_AMD64_IBSOPDATA2, ops_data2); + remote_access =3D ops_data2 & MSR_AMD64_IBSOPDATA2_DATASRC; + + /* Consider only DRAM accesses, exclude cache accesses from near ccx */ + if (remote_access < MSR_AMD64_IBSOPDATA2_DATASRC_DRAM) { + count_vm_event(IBS_NEAR_CACHE_HITS); + goto handled; + } + + /* Exclude hits from peer cache in far ccx */ + if (remote_access =3D=3D MSR_AMD64_IBSOPDATA2_DATASRC_FAR_CCX_CACHE) { + count_vm_event(IBS_FAR_CACHE_HITS); + goto handled; + } + + /* Is linear addr valid? */ + if (ops_data3 & MSR_AMD64_IBSOPDATA3_LADDR_VALID) + rdmsrl(MSR_AMD64_IBSDCLINAD, laddr); + else { + count_vm_event(IBS_LADDR_INVALID); + goto handled; + } + + /* Discard kernel address accesses */ + if (laddr & (1UL << 63)) { + count_vm_event(IBS_KERNEL_ADDR); + goto handled; + } + + /* Is phys addr valid? */ + if (ops_data3 & MSR_AMD64_IBSOPDATA3_PADDR_VALID) + rdmsrl(MSR_AMD64_IBSDCPHYSAD, paddr); + else + count_vm_event(IBS_PADDR_INVALID); + +handled: + return NMI_HANDLED; +} + +static inline int get_ibs_lvt_offset(void) +{ + u64 val; + + rdmsrl(MSR_AMD64_IBSCTL, val); + if (!(val & IBSCTL_LVT_OFFSET_VALID)) + return -EINVAL; + + return val & IBSCTL_LVT_OFFSET_MASK; +} + +static void setup_APIC_ibs(void) +{ + int offset; + + offset =3D get_ibs_lvt_offset(); + if (offset < 0) + goto failed; + + if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0)) + return; +failed: + pr_warn("IBS APIC setup failed on cpu #%d\n", + smp_processor_id()); +} + +static void clear_APIC_ibs(void) +{ + int offset; + + offset =3D get_ibs_lvt_offset(); + if (offset >=3D 0) + setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1); +} + +static int x86_amd_ibs_access_profile_startup(unsigned int cpu) +{ + setup_APIC_ibs(); + return 0; +} + +static int x86_amd_ibs_access_profile_teardown(unsigned int cpu) +{ + clear_APIC_ibs(); + return 0; +} + +int __init ibs_access_profiling_init(void) +{ + u32 caps; + + ibs_config =3D IBS_OP_CNT_CTL | IBS_OP_ENABLE; + + if (!boot_cpu_has(X86_FEATURE_IBS)) { + pr_info("IBS capability is unavailable for access profiling\n"); + return 0; + } + + caps =3D cpuid_eax(IBS_CPUID_FEATURES); + if (caps & IBS_CAPS_ZEN4) + ibs_config |=3D IBS_OP_L3MISSONLY; + + register_nmi_handler(NMI_LOCAL, ibs_overflow_handler, 0, "ibs"); + + cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING, + "x86/amd/ibs_access_profile:starting", + x86_amd_ibs_access_profile_startup, + x86_amd_ibs_access_profile_teardown); + + pr_info("IBS access profiling setup for NUMA Balancing\n"); + return 0; +} + +arch_initcall(ibs_access_profiling_init); diff --git a/include/linux/vm_event_item.h b/include/linux/vm_event_item.h index 7f5d1caf5890..1d55e347d16c 100644 --- a/include/linux/vm_event_item.h +++ b/include/linux/vm_event_item.h @@ -149,6 +149,17 @@ enum vm_event_item { PGPGIN, PGPGOUT, PSWPIN, PSWPOUT, #ifdef CONFIG_X86 DIRECT_MAP_LEVEL2_SPLIT, DIRECT_MAP_LEVEL3_SPLIT, +#ifdef CONFIG_NUMA_BALANCING + IBS_NR_EVENTS, + IBS_KTHREAD, + IBS_NON_LOAD_STORES, + IBS_DC_L2_HITS, + IBS_NEAR_CACHE_HITS, + IBS_FAR_CACHE_HITS, + IBS_LADDR_INVALID, + IBS_KERNEL_ADDR, + IBS_PADDR_INVALID, +#endif #endif NR_VM_EVENT_ITEMS }; diff --git a/mm/vmstat.c b/mm/vmstat.c index 1ea6a5ce1c41..c7a9d0d9ade8 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -1398,6 +1398,17 @@ const char * const vmstat_text[] =3D { #ifdef CONFIG_X86 "direct_map_level2_splits", "direct_map_level3_splits", +#ifdef CONFIG_NUMA_BALANCING + "ibs_nr_events", + "ibs_kthread", + "ibs_non_load_stores", + "ibs_dc_l2_hits", + "ibs_near_cache_hits", + "ibs_far_cache_hits", + "ibs_invalid_laddr", + "ibs_kernel_addr", + "ibs_invalid_paddr", +#endif #endif #endif /* CONFIG_VM_EVENT_COUNTERS || CONFIG_MEMCG */ }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT018.mail.protection.outlook.com (10.13.176.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6086.17 via Frontend Transport; Wed, 8 Feb 2023 07:36:37 +0000 Received: from BLR-5CG1133937.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 8 Feb 2023 01:36:32 -0600 From: Bharata B Rao To: , CC: , , , , , , , , , , , Bharata B Rao Subject: [RFC PATCH 2/5] x86/ibs: Drive NUMA balancing via IBS access data Date: Wed, 8 Feb 2023 13:05:30 +0530 Message-ID: <20230208073533.715-3-bharata@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208073533.715-1-bharata@amd.com> References: <20230208073533.715-1-bharata@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT018:EE_|CH2PR12MB4310:EE_ X-MS-Office365-Filtering-Correlation-Id: ce5579fc-c4d7-4c70-047f-08db09a7363c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 07:36:37.6679 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce5579fc-c4d7-4c70-047f-08db09a7363c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4310 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Feed the page access data obtained from IBS to NUMA balancing as hint fault equivalents. The existing per-task and per-group fault stats are now built from IBS-provided page access information. With this it will not be necessary to scan the address space to introduce NUMA hinting faults. Use task_work framework to process the IBS sampled data. Actual programming of IBS to generate page access information isn't done yet. Signed-off-by: Bharata B Rao --- arch/x86/mm/ibs.c | 38 ++++++++++++++- include/linux/migrate.h | 1 + include/linux/sched.h | 1 + include/linux/vm_event_item.h | 1 + kernel/sched/fair.c | 10 ++++ mm/memory.c | 92 +++++++++++++++++++++++++++++++++++ mm/vmstat.c | 1 + 7 files changed, 143 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/ibs.c b/arch/x86/mm/ibs.c index 411dba2a88d1..adbc587b1767 100644 --- a/arch/x86/mm/ibs.c +++ b/arch/x86/mm/ibs.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 =20 #include +#include +#include =20 #include #include /* TODO: Move defns like IBS_OP_ENABLE into no= n-perf header */ @@ -8,12 +10,30 @@ =20 static u64 ibs_config __read_mostly; =20 +struct ibs_access_work { + struct callback_head work; + u64 laddr, paddr; +}; + +void task_ibs_access_work(struct callback_head *work) +{ + struct ibs_access_work *iwork =3D container_of(work, struct ibs_access_wo= rk, work); + struct task_struct *p =3D current; + + u64 laddr =3D iwork->laddr; + u64 paddr =3D iwork->paddr; + + kfree(iwork); + do_numa_access(p, laddr, paddr); +} + static int ibs_overflow_handler(unsigned int cmd, struct pt_regs *regs) { u64 ops_ctl, ops_data3, ops_data2; u64 remote_access; u64 laddr =3D -1, paddr =3D -1; struct mm_struct *mm =3D current->mm; + struct ibs_access_work *iwork; =20 rdmsrl(MSR_AMD64_IBSOPCTL, ops_ctl); =20 @@ -86,8 +106,24 @@ static int ibs_overflow_handler(unsigned int cmd, struc= t pt_regs *regs) /* Is phys addr valid? */ if (ops_data3 & MSR_AMD64_IBSOPDATA3_PADDR_VALID) rdmsrl(MSR_AMD64_IBSDCPHYSAD, paddr); - else + else { count_vm_event(IBS_PADDR_INVALID); + goto handled; + } + + /* + * TODO: GFP_ATOMIC! + */ + iwork =3D kzalloc(sizeof(*iwork), GFP_ATOMIC); + if (!iwork) + goto handled; + + count_vm_event(IBS_USEFUL_SAMPLES); + + iwork->laddr =3D laddr; + iwork->paddr =3D paddr; + init_task_work(&iwork->work, task_ibs_access_work); + task_work_add(current, &iwork->work, TWA_RESUME); =20 handled: return NMI_HANDLED; diff --git a/include/linux/migrate.h b/include/linux/migrate.h index 3ef77f52a4f0..4dcce7885b0c 100644 --- a/include/linux/migrate.h +++ b/include/linux/migrate.h @@ -216,6 +216,7 @@ void migrate_device_pages(unsigned long *src_pfns, unsi= gned long *dst_pfns, unsigned long npages); void migrate_device_finalize(unsigned long *src_pfns, unsigned long *dst_pfns, unsigned long npages); +void do_numa_access(struct task_struct *p, u64 laddr, u64 paddr); =20 #endif /* CONFIG_MIGRATION */ =20 diff --git a/include/linux/sched.h b/include/linux/sched.h index 853d08f7562b..19dd4ee07436 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -2420,4 +2420,5 @@ static inline void sched_core_fork(struct task_struct= *p) { } =20 extern void sched_set_stop_task(int cpu, struct task_struct *stop); =20 +DECLARE_STATIC_KEY_FALSE(hw_access_hints); #endif diff --git a/include/linux/vm_event_item.h b/include/linux/vm_event_item.h index 1d55e347d16c..2ccc7dee3c13 100644 --- a/include/linux/vm_event_item.h +++ b/include/linux/vm_event_item.h @@ -159,6 +159,7 @@ enum vm_event_item { PGPGIN, PGPGOUT, PSWPIN, PSWPOUT, IBS_LADDR_INVALID, IBS_KERNEL_ADDR, IBS_PADDR_INVALID, + IBS_USEFUL_SAMPLES, #endif #endif NR_VM_EVENT_ITEMS diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 0f8736991427..c9b9e62da779 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -47,6 +47,7 @@ #include #include #include +#include =20 #include =20 @@ -3125,6 +3126,8 @@ void init_numa_balancing(unsigned long clone_flags, s= truct task_struct *p) } } =20 +DEFINE_STATIC_KEY_FALSE(hw_access_hints); + /* * Drive the periodic memory faults.. */ @@ -3133,6 +3136,13 @@ static void task_tick_numa(struct rq *rq, struct tas= k_struct *curr) struct callback_head *work =3D &curr->numa_work; u64 period, now; =20 + /* + * If we are using access hints from hardware (like using + * IBS), don't scan the address space. + */ + if (static_branch_unlikely(&hw_access_hints)) + return; + /* * We don't care about NUMA placement if we don't have memory. */ diff --git a/mm/memory.c b/mm/memory.c index aad226daf41b..79096aba197c 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -4668,6 +4668,98 @@ int numa_migrate_prep(struct page *page, struct vm_a= rea_struct *vma, return mpol_misplaced(page, vma, addr); } =20 +/* + * Called from task_work context to act upon the page access. + * + * Physical address (provided by IBS) is used directly instead + * of walking the page tables to get to the PTE/page. Hence we + * don't check if PTE is writable for the TNF_NO_GROUP + * optimization, which means RO pages are considered for grouping. + */ +void do_numa_access(struct task_struct *p, u64 laddr, u64 paddr) +{ + struct mm_struct *mm =3D p->mm; + struct vm_area_struct *vma; + struct page *page =3D NULL; + int page_nid =3D NUMA_NO_NODE; + int last_cpupid; + int target_nid; + int flags =3D 0; + + if (!mm) + return; + + if (!mmap_read_trylock(mm)) + return; + + vma =3D find_vma(mm, laddr); + if (!vma) + goto out_unlock; + + if (!vma_migratable(vma) || !vma_policy_mof(vma) || + is_vm_hugetlb_page(vma) || (vma->vm_flags & VM_MIXEDMAP)) + goto out_unlock; + + if (!vma->vm_mm || + (vma->vm_file && (vma->vm_flags & (VM_READ|VM_WRITE)) =3D=3D (VM_READ= ))) + goto out_unlock; + + if (!vma_is_accessible(vma)) + goto out_unlock; + + page =3D pfn_to_online_page(PHYS_PFN(paddr)); + if (!page || is_zone_device_page(page)) + goto out_unlock; + + if (unlikely(!PageLRU(page))) + goto out_unlock; + + /* TODO: handle PTE-mapped THP */ + if (PageCompound(page)) + goto out_unlock; + + /* + * Flag if the page is shared between multiple address spaces. This + * is later used when determining whether to group tasks together + */ + if (page_mapcount(page) > 1 && (vma->vm_flags & VM_SHARED)) + flags |=3D TNF_SHARED; + + last_cpupid =3D page_cpupid_last(page); + page_nid =3D page_to_nid(page); + + /* + * For memory tiering mode, cpupid of slow memory page is used + * to record page access time. So use default value. + */ + if ((sysctl_numa_balancing_mode & NUMA_BALANCING_MEMORY_TIERING) && + !node_is_toptier(page_nid)) + last_cpupid =3D (-1 & LAST_CPUPID_MASK); + else + last_cpupid =3D page_cpupid_last(page); + + target_nid =3D numa_migrate_prep(page, vma, laddr, page_nid, &flags); + if (target_nid =3D=3D NUMA_NO_NODE) { + put_page(page); + goto out; + } + + /* Migrate to the requested node */ + if (migrate_misplaced_page(page, vma, target_nid)) { + page_nid =3D target_nid; + flags |=3D TNF_MIGRATED; + } else { + flags |=3D TNF_MIGRATE_FAIL; + } + +out: + if (page_nid !=3D NUMA_NO_NODE) + task_numa_fault(last_cpupid, page_nid, 1, flags); + +out_unlock: + mmap_read_unlock(mm); +} + static vm_fault_t do_numa_page(struct vm_fault *vmf) { struct vm_area_struct *vma =3D vmf->vma; diff --git a/mm/vmstat.c b/mm/vmstat.c index c7a9d0d9ade8..33738426ae48 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -1408,6 +1408,7 @@ const char * const vmstat_text[] =3D { "ibs_invalid_laddr", "ibs_kernel_addr", "ibs_invalid_paddr", + "ibs_useful_samples", #endif #endif #endif /* CONFIG_VM_EVENT_COUNTERS || CONFIG_MEMCG */ --=20 2.25.1 From nobody Fri Sep 12 18:14:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7691EC05027 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 07:36:42.1095 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a363116-817e-43b1-5c51-08db09a738df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5766 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Program IBS for access profiling for threads from the task sched switch path. IBS is programmed with a period that corresponds to the incoming thread. Kernel threads are excluded from this. The sample period is currently kept at a fixed value of 10000. Signed-off-by: Bharata B Rao --- arch/x86/mm/ibs.c | 27 +++++++++++++++++++++++++++ include/linux/sched.h | 1 + kernel/sched/core.c | 1 + kernel/sched/fair.c | 1 + kernel/sched/sched.h | 5 +++++ 5 files changed, 35 insertions(+) diff --git a/arch/x86/mm/ibs.c b/arch/x86/mm/ibs.c index adbc587b1767..a479029e9262 100644 --- a/arch/x86/mm/ibs.c +++ b/arch/x86/mm/ibs.c @@ -8,6 +8,7 @@ #include /* TODO: Move defns like IBS_OP_ENABLE into no= n-perf header */ #include =20 +#define IBS_SAMPLE_PERIOD 10000 static u64 ibs_config __read_mostly; =20 struct ibs_access_work { @@ -15,6 +16,31 @@ struct ibs_access_work { u64 laddr, paddr; }; =20 +void hw_access_sched_in(struct task_struct *prev, struct task_struct *curr) +{ + u64 config =3D 0; + unsigned int period; + + if (!static_branch_unlikely(&hw_access_hints)) + return; + + /* Disable IBS for kernel thread */ + if (!curr->mm) + goto out; + + if (curr->numa_sample_period) + period =3D curr->numa_sample_period; + else + period =3D IBS_SAMPLE_PERIOD; + + + config =3D (period >> 4) & IBS_OP_MAX_CNT; + config |=3D (period & IBS_OP_MAX_CNT_EXT_MASK); + config |=3D ibs_config; +out: + wrmsrl(MSR_AMD64_IBSOPCTL, config); +} + void task_ibs_access_work(struct callback_head *work) { struct ibs_access_work *iwork =3D container_of(work, struct ibs_access_wo= rk, work); @@ -198,6 +224,7 @@ int __init ibs_access_profiling_init(void) x86_amd_ibs_access_profile_startup, x86_amd_ibs_access_profile_teardown); =20 + static_branch_enable(&hw_access_hints); pr_info("IBS access profiling setup for NUMA Balancing\n"); return 0; } diff --git a/include/linux/sched.h b/include/linux/sched.h index 19dd4ee07436..66c532418d38 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1254,6 +1254,7 @@ struct task_struct { int numa_scan_seq; unsigned int numa_scan_period; unsigned int numa_scan_period_max; + unsigned int numa_sample_period; int numa_preferred_nid; unsigned long numa_migrate_retry; /* Migration stamp: */ diff --git a/kernel/sched/core.c b/kernel/sched/core.c index e838feb6adc5..1c13fed8bebc 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5165,6 +5165,7 @@ static struct rq *finish_task_switch(struct task_stru= ct *prev) prev_state =3D READ_ONCE(prev->__state); vtime_task_switch(prev); perf_event_task_sched_in(prev, current); + hw_access_sched_in(prev, current); finish_task(prev); tick_nohz_task_switch(); finish_lock_switch(rq); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index c9b9e62da779..3f617c799821 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -3094,6 +3094,7 @@ void init_numa_balancing(unsigned long clone_flags, s= truct task_struct *p) p->node_stamp =3D 0; p->numa_scan_seq =3D mm ? mm->numa_scan_seq : 0; p->numa_scan_period =3D sysctl_numa_balancing_scan_delay; + p->numa_sample_period =3D 0; p->numa_migrate_retry =3D 0; /* Protect against double add, see task_tick_numa and task_numa_work */ p->numa_work.next =3D &p->numa_work; diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 771f8ddb7053..953d16c802d6 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1723,11 +1723,16 @@ extern int migrate_task_to(struct task_struct *p, i= nt cpu); extern int migrate_swap(struct task_struct *p, struct task_struct *t, int cpu, int scpu); extern void init_numa_balancing(unsigned long clone_flags, struct task_str= uct *p); +void hw_access_sched_in(struct task_struct *prev, struct task_struct *curr= ); #else static inline void init_numa_balancing(unsigned long clone_flags, struct task_struct *p) { } +static inline void hw_access_sched_in(struct task_struct *prev, + struct task_struct *curr) +{ +} #endif /* CONFIG_NUMA_BALANCING */ =20 #ifdef CONFIG_SMP --=20 2.25.1 From nobody Fri Sep 12 18:14:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC01DC05027 for ; Wed, 8 Feb 2023 07:37:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231222AbjBHHhZ (ORCPT ); Wed, 8 Feb 2023 02:37:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229797AbjBHHhJ (ORCPT ); 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Wed, 8 Feb 2023 01:36:42 -0600 From: Bharata B Rao To: , CC: , , , , , , , , , , , Bharata B Rao Subject: [RFC PATCH 4/5] x86/ibs: Adjust access faults sampling period Date: Wed, 8 Feb 2023 13:05:32 +0530 Message-ID: <20230208073533.715-5-bharata@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208073533.715-1-bharata@amd.com> References: <20230208073533.715-1-bharata@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT010:EE_|IA1PR12MB6436:EE_ X-MS-Office365-Filtering-Correlation-Id: f197b081-34c5-4bd7-5c6c-08db09a73bee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5ZY0fx/a8fXolnZRTIy4EFetIVVHpE8cOyBznCmmF25UGJHGGieYsOWYR+olbrwdOHS3HQ4YHlo81TU71tdH4gr650yD455tqTSOj1T0SOfJRt2DD7VEUpGm/Vy/vhAc49VEkBCP4DWWnAR8/mzjAbWhqZ912aeIvaYfn05HRpQyqe6LYI01UXgS6VGzVqthvT8jR6vJ1r9jBF1M7uUySCF4OZ8Ka59ZKAG+lSiZ4LZtLAsMKq5FS4hlu0ZJTZZ/jy6Dnyc6ZNnnz9hz5GMkoh+DCygTJc1etRIyIYgWUn9QZ0hli2ho6QAnHhfkjC7duMlNXz0H7GdN/PRmL6CliSw9v4rL/pUsQaTgU5FVyIY5lLV+7cMc0hNN477ySNG8kyJIwVglaSakk8UDh/XwQMbffNtaKb+2D7EWE0dxtfmdWFpgchcS4cEblG2yUrVxQkbNfHbB9RF/HlxM1Oy3lXXNW9FqoLpLU1mzuwRGRBJRky0d9toI0cZoj/rbV/T0HB86+/O4S0U7hVNV4BvE7xtwfGn33V/mcvaSfiDo15jPug2v3ZODPJLvCikSv2U/CdCPDS70iGhAQ5283OsAjd5MTQGPqJGZYQLnvcPavDwW21OJ5qhTdF6xH5O8Cm1S8XPi2kgjKiy3BSzvFHqJoRKn/bDQW4Va8ChB+0X7c3eN8FDuxM7dISfEcP7fNvEEZ7LXz6CiWucP3NWwlnDeqjRvOhzAqsqYCiu44y6/k8Dwbtfi+MTufl9OH6aPDBAk X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(346002)(396003)(39860400002)(136003)(376002)(451199018)(46966006)(40470700004)(36840700001)(54906003)(186003)(26005)(82310400005)(86362001)(110136005)(40480700001)(426003)(47076005)(36756003)(7696005)(8676002)(40460700003)(16526019)(2906002)(5660300002)(70586007)(7416002)(36860700001)(8936002)(70206006)(41300700001)(4326008)(478600001)(336012)(2616005)(6666004)(1076003)(82740400003)(356005)(316002)(83380400001)(81166007)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 07:36:47.2253 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f197b081-34c5-4bd7-5c6c-08db09a73bee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6436 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adjust the access faults sampling period of a thread to be within the fixed mininum and maximum value. The adjustment logic uses the private/shared and local/remote access faults stats. The algorithm is same as the logic followed to adjust the scan period. Unlike hinting faults, the min and max sampling period aren't adjusted (yet) for access based sampling. Signed-off-by: Bharata B Rao --- include/linux/sched.h | 2 + kernel/sched/debug.c | 8 +++ kernel/sched/fair.c | 130 +++++++++++++++++++++++++++++++++++++----- kernel/sched/sched.h | 4 ++ 4 files changed, 130 insertions(+), 14 deletions(-) diff --git a/include/linux/sched.h b/include/linux/sched.h index 66c532418d38..101c6377abbc 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1257,6 +1257,8 @@ struct task_struct { unsigned int numa_sample_period; int numa_preferred_nid; unsigned long numa_migrate_retry; + unsigned int numa_access_faults; + unsigned int numa_access_faults_window; /* Migration stamp: */ u64 node_stamp; u64 last_task_numa_placement; diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c index 1637b65ba07a..1cf19778a232 100644 --- a/kernel/sched/debug.c +++ b/kernel/sched/debug.c @@ -334,6 +334,14 @@ static __init int sched_init_debug(void) debugfs_create_u32("scan_period_max_ms", 0644, numa, &sysctl_numa_balanci= ng_scan_period_max); debugfs_create_u32("scan_size_mb", 0644, numa, &sysctl_numa_balancing_sca= n_size); debugfs_create_u32("hot_threshold_ms", 0644, numa, &sysctl_numa_balancing= _hot_threshold); + debugfs_create_u32("sample_period_def", 0644, numa, + &sysctl_numa_balancing_sample_period_def); + debugfs_create_u32("sample_period_min", 0644, numa, + &sysctl_numa_balancing_sample_period_min); + debugfs_create_u32("sample_period_max", 0644, numa, + &sysctl_numa_balancing_sample_period_max); + debugfs_create_u32("access_faults_threshold", 0644, numa, + &sysctl_numa_balancing_access_faults_threshold); #endif =20 debugfs_create_file("debug", 0444, debugfs_sched, NULL, &sched_debug_fops= ); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 3f617c799821..1b0665b034d0 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -1093,6 +1093,11 @@ adjust_numa_imbalance(int imbalance, int dst_running= , int imb_numa_nr) #endif /* CONFIG_NUMA */ =20 #ifdef CONFIG_NUMA_BALANCING +unsigned int sysctl_numa_balancing_sample_period_def =3D 10000; +unsigned int sysctl_numa_balancing_sample_period_min =3D 5000; +unsigned int sysctl_numa_balancing_sample_period_max =3D 20000; +unsigned int sysctl_numa_balancing_access_faults_threshold =3D 250; + /* * Approximate time to scan a full NUMA task in ms. The task scan period is * calculated based on the tasks virtual memory size and @@ -1572,6 +1577,7 @@ bool should_numa_migrate_memory(struct task_struct *p= , struct page * page, struct numa_group *ng =3D deref_curr_numa_group(p); int dst_nid =3D cpu_to_node(dst_cpu); int last_cpupid, this_cpupid; + bool early =3D false; =20 /* * The pages in slow memory node should be migrated according @@ -1611,13 +1617,21 @@ bool should_numa_migrate_memory(struct task_struct = *p, struct page * page, !node_is_toptier(src_nid) && !cpupid_valid(last_cpupid)) return false; =20 + if (static_branch_unlikely(&hw_access_hints)) { + if (p->numa_access_faults < sysctl_numa_balancing_access_faults_threshol= d * 4) + early =3D true; + } else { + if (p->numa_scan_seq <=3D 4) + early =3D true; + } + /* * Allow first faults or private faults to migrate immediately early in * the lifetime of a task. The magic number 4 is based on waiting for * two full passes of the "multi-stage node selection" test that is * executed below. */ - if ((p->numa_preferred_nid =3D=3D NUMA_NO_NODE || p->numa_scan_seq <=3D 4= ) && + if ((p->numa_preferred_nid =3D=3D NUMA_NO_NODE || early) && (cpupid_pid_unset(last_cpupid) || cpupid_match_pid(p, last_cpupid))) return true; =20 @@ -2305,7 +2319,11 @@ static void numa_migrate_preferred(struct task_struc= t *p) return; =20 /* Periodically retry migrating the task to the preferred node */ - interval =3D min(interval, msecs_to_jiffies(p->numa_scan_period) / 16); + if (static_branch_unlikely(&hw_access_hints)) + interval =3D min(interval, msecs_to_jiffies(p->numa_sample_period) / 16); + else + interval =3D min(interval, msecs_to_jiffies(p->numa_scan_period) / 16); + p->numa_migrate_retry =3D jiffies + interval; =20 /* Success if task is already running on preferred CPU */ @@ -2430,6 +2448,77 @@ static void update_task_scan_period(struct task_stru= ct *p, memset(p->numa_faults_locality, 0, sizeof(p->numa_faults_locality)); } =20 +static void update_task_sample_period(struct task_struct *p, + unsigned long shared, unsigned long private) +{ + unsigned int period_slot; + int lr_ratio, ps_ratio; + int diff; + + unsigned long remote =3D p->numa_faults_locality[0]; + unsigned long local =3D p->numa_faults_locality[1]; + + /* + * If there were no access faults then either the task is + * completely idle or all activity is in areas that are not of interest + * to automatic numa balancing. Related to that, if there were failed + * migration then it implies we are migrating too quickly or the local + * node is overloaded. In either case, increase the sampling rate. + */ + if (local + shared =3D=3D 0 || p->numa_faults_locality[2]) { + p->numa_sample_period =3D min(sysctl_numa_balancing_sample_period_max, + p->numa_sample_period << 1); + return; + } + + /* + * Prepare to scale scan period relative to the current period. + * =3D=3D NUMA_PERIOD_THRESHOLD sample period stays the same + * < NUMA_PERIOD_THRESHOLD sample period decreases + * >=3D NUMA_PERIOD_THRESHOLD sample period increases + */ + period_slot =3D DIV_ROUND_UP(p->numa_sample_period, NUMA_PERIOD_SLOTS); + lr_ratio =3D (local * NUMA_PERIOD_SLOTS) / (local + remote); + ps_ratio =3D (private * NUMA_PERIOD_SLOTS) / (private + shared); + + if (ps_ratio >=3D NUMA_PERIOD_THRESHOLD) { + /* + * Most memory accesses are local. There is no need to + * do fast access sampling, since memory is already local. + */ + int slot =3D ps_ratio - NUMA_PERIOD_THRESHOLD; + + if (!slot) + slot =3D 1; + diff =3D slot * period_slot; + } else if (lr_ratio >=3D NUMA_PERIOD_THRESHOLD) { + /* + * Most memory accesses are shared with other tasks. + * There is no point in continuing fast access sampling, + * since other tasks may just move the memory elsewhere. + */ + int slot =3D lr_ratio - NUMA_PERIOD_THRESHOLD; + + if (!slot) + slot =3D 1; + diff =3D slot * period_slot; + } else { + /* + * Private memory faults exceed (SLOTS-THRESHOLD)/SLOTS, + * yet they are not on the local NUMA node. Speed up + * access sampling to get the memory moved over. + */ + int ratio =3D max(lr_ratio, ps_ratio); + + diff =3D -(NUMA_PERIOD_THRESHOLD - ratio) * period_slot; + } + + p->numa_sample_period =3D clamp(p->numa_sample_period + diff, + sysctl_numa_balancing_sample_period_min, + sysctl_numa_balancing_sample_period_max); + memset(p->numa_faults_locality, 0, sizeof(p->numa_faults_locality)); +} + /* * Get the fraction of time the task has been running since the last * NUMA placement cycle. The scheduler keeps similar statistics, but @@ -2560,16 +2649,24 @@ static void task_numa_placement(struct task_struct = *p) spinlock_t *group_lock =3D NULL; struct numa_group *ng; =20 - /* - * The p->mm->numa_scan_seq field gets updated without - * exclusive access. Use READ_ONCE() here to ensure - * that the field is read in a single access: - */ - seq =3D READ_ONCE(p->mm->numa_scan_seq); - if (p->numa_scan_seq =3D=3D seq) - return; - p->numa_scan_seq =3D seq; - p->numa_scan_period_max =3D task_scan_max(p); + if (static_branch_unlikely(&hw_access_hints)) { + p->numa_access_faults_window++; + p->numa_access_faults++; + if (p->numa_access_faults_window < sysctl_numa_balancing_access_faults_t= hreshold) + return; + p->numa_access_faults_window =3D 0; + } else { + /* + * The p->mm->numa_scan_seq field gets updated without + * exclusive access. Use READ_ONCE() here to ensure + * that the field is read in a single access: + */ + seq =3D READ_ONCE(p->mm->numa_scan_seq); + if (p->numa_scan_seq =3D=3D seq) + return; + p->numa_scan_seq =3D seq; + p->numa_scan_period_max =3D task_scan_max(p); + } =20 total_faults =3D p->numa_faults_locality[0] + p->numa_faults_locality[1]; @@ -2672,7 +2769,10 @@ static void task_numa_placement(struct task_struct *= p) sched_setnuma(p, max_nid); } =20 - update_task_scan_period(p, fault_types[0], fault_types[1]); + if (static_branch_unlikely(&hw_access_hints)) + update_task_sample_period(p, fault_types[0], fault_types[1]); + else + update_task_scan_period(p, fault_types[0], fault_types[1]); } =20 static inline int get_numa_group(struct numa_group *grp) @@ -3094,7 +3194,9 @@ void init_numa_balancing(unsigned long clone_flags, s= truct task_struct *p) p->node_stamp =3D 0; p->numa_scan_seq =3D mm ? mm->numa_scan_seq : 0; p->numa_scan_period =3D sysctl_numa_balancing_scan_delay; - p->numa_sample_period =3D 0; + p->numa_sample_period =3D sysctl_numa_balancing_sample_period_def; + p->numa_access_faults =3D 0; + p->numa_access_faults_window =3D 0; p->numa_migrate_retry =3D 0; /* Protect against double add, see task_tick_numa and task_numa_work */ p->numa_work.next =3D &p->numa_work; diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 953d16c802d6..0367dc727cc4 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -2473,6 +2473,10 @@ extern unsigned int sysctl_numa_balancing_scan_perio= d_min; extern unsigned int sysctl_numa_balancing_scan_period_max; extern unsigned int sysctl_numa_balancing_scan_size; extern unsigned int sysctl_numa_balancing_hot_threshold; +extern unsigned int sysctl_numa_balancing_sample_period_def; +extern unsigned int sysctl_numa_balancing_sample_period_min; +extern unsigned int sysctl_numa_balancing_sample_period_max; +extern unsigned int sysctl_numa_balancing_access_faults_threshold; #endif =20 #ifdef CONFIG_SCHED_HRTICK --=20 2.25.1 From nobody Fri Sep 12 18:14:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6F82C05027 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT059.mail.protection.outlook.com (10.13.177.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6086.17 via Frontend Transport; Wed, 8 Feb 2023 07:36:51 +0000 Received: from BLR-5CG1133937.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 8 Feb 2023 01:36:46 -0600 From: Bharata B Rao To: , CC: , , , , , , , , , , , Bharata B Rao Subject: [RFC PATCH 5/5] x86/ibs: Delay the collection of HW-provided access info Date: Wed, 8 Feb 2023 13:05:33 +0530 Message-ID: <20230208073533.715-6-bharata@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208073533.715-1-bharata@amd.com> References: <20230208073533.715-1-bharata@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT059:EE_|IA0PR12MB8328:EE_ X-MS-Office365-Filtering-Correlation-Id: f743052a-3f22-48a8-74c3-08db09a73e62 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 07:36:51.3416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f743052a-3f22-48a8-74c3-08db09a73e62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8328 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow an initial delay before enabling the collection of IBS provided access info. Signed-off-by: Bharata B Rao --- arch/x86/mm/ibs.c | 18 ++++++++++++++++++ include/linux/mm.h | 2 ++ include/linux/mm_types.h | 3 +++ kernel/sched/debug.c | 2 ++ kernel/sched/fair.c | 3 +++ 5 files changed, 28 insertions(+) diff --git a/arch/x86/mm/ibs.c b/arch/x86/mm/ibs.c index a479029e9262..dfe5246954c0 100644 --- a/arch/x86/mm/ibs.c +++ b/arch/x86/mm/ibs.c @@ -16,6 +16,21 @@ struct ibs_access_work { u64 laddr, paddr; }; =20 +static bool delay_hw_access_profiling(struct mm_struct *mm) +{ + unsigned long delay, now =3D jiffies; + + if (!mm->numa_hw_access_delay) + mm->numa_hw_access_delay =3D now + + msecs_to_jiffies(sysctl_numa_balancing_access_faults_delay); + + delay =3D mm->numa_hw_access_delay; + if (time_before(now, delay)) + return true; + + return false; +} + void hw_access_sched_in(struct task_struct *prev, struct task_struct *curr) { u64 config =3D 0; @@ -28,6 +43,9 @@ void hw_access_sched_in(struct task_struct *prev, struct = task_struct *curr) if (!curr->mm) goto out; =20 + if (delay_hw_access_profiling(curr->mm)) + goto out; + if (curr->numa_sample_period) period =3D curr->numa_sample_period; else diff --git a/include/linux/mm.h b/include/linux/mm.h index 8f857163ac89..118705a296ef 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1397,6 +1397,8 @@ static inline int folio_nid(const struct folio *folio) } =20 #ifdef CONFIG_NUMA_BALANCING +extern unsigned int sysctl_numa_balancing_access_faults_delay; + /* page access time bits needs to hold at least 4 seconds */ #define PAGE_ACCESS_TIME_MIN_BITS 12 #if LAST_CPUPID_SHIFT < PAGE_ACCESS_TIME_MIN_BITS diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index 9757067c3053..8a2fb8bf2d62 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -750,6 +750,9 @@ struct mm_struct { =20 /* numa_scan_seq prevents two threads remapping PTEs. */ int numa_scan_seq; + + /* HW-provided access info is collected after this initial delay */ + unsigned long numa_hw_access_delay; #endif /* * An operation with batched TLB flushing is going on. Anything diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c index 1cf19778a232..5c76a7594358 100644 --- a/kernel/sched/debug.c +++ b/kernel/sched/debug.c @@ -342,6 +342,8 @@ static __init int sched_init_debug(void) &sysctl_numa_balancing_sample_period_max); debugfs_create_u32("access_faults_threshold", 0644, numa, &sysctl_numa_balancing_access_faults_threshold); + debugfs_create_u32("access_faults_delay", 0644, numa, + &sysctl_numa_balancing_access_faults_delay); #endif =20 debugfs_create_file("debug", 0444, debugfs_sched, NULL, &sched_debug_fops= ); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 1b0665b034d0..2e2b1e706a24 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -1097,6 +1097,7 @@ unsigned int sysctl_numa_balancing_sample_period_def = =3D 10000; unsigned int sysctl_numa_balancing_sample_period_min =3D 5000; unsigned int sysctl_numa_balancing_sample_period_max =3D 20000; unsigned int sysctl_numa_balancing_access_faults_threshold =3D 250; +unsigned int sysctl_numa_balancing_access_faults_delay =3D 1000; =20 /* * Approximate time to scan a full NUMA task in ms. The task scan period is @@ -3189,6 +3190,8 @@ void init_numa_balancing(unsigned long clone_flags, s= truct task_struct *p) if (mm_users =3D=3D 1) { mm->numa_next_scan =3D jiffies + msecs_to_jiffies(sysctl_numa_balancing= _scan_delay); mm->numa_scan_seq =3D 0; + mm->numa_hw_access_delay =3D jiffies + + msecs_to_jiffies(sysctl_numa_balancing_access_faults_delay); } } p->node_stamp =3D 0; --=20 2.25.1