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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id g24-20020a7bc4d8000000b003df30c94850sm17987385wmk.25.2023.02.07.05.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 05:10:13 -0800 (PST) From: bchihi@baylibre.com To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, james.lo@mediatek.com, rex-bc.chen@mediatek.com Subject: [PATCH v13 6/6] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold Date: Tue, 7 Feb 2023 14:09:58 +0100 Message-Id: <20230207130958.608305-7-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230207130958.608305-1-bchihi@baylibre.com> References: <20230207130958.608305-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI The mt8195 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold when to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 169 ++++++++++++++++++++--- 1 file changed, 153 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index c7e958f8f1b5..10c8fb0856bc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 / { @@ -2413,107 +2414,243 @@ dp_tx: dp-tx@1c600000 { =20 thermal_zones: thermal-zones { cpu0-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; + trips { + cpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu1-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; + trips { + cpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu1_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu2-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; + trips { + cpu2_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu2_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu3-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; + trips { + cpu3_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu3_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu4-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU0>; + trips { + cpu4_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu4_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu5-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU1>; + trips { + cpu5_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu5_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu6-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU2>; + trips { + cpu6_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu6_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; =20 cpu7-thermal { - polling-delay =3D <0>; - polling-delay-passive =3D <0>; + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; thermal-sensors =3D <&lvts_mcu MT8195_MCU_BIG_CPU3>; + trips { + cpu7_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu7_crit: trip-crit { temperature =3D <100000>; hysteresis =3D <2000>; type =3D "critical"; }; }; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; }; --=20 2.34.1