From nobody Fri Sep 12 22:24:38 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89B11C6379F for ; Tue, 7 Feb 2023 11:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231934AbjBGLIp (ORCPT ); Tue, 7 Feb 2023 06:08:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230193AbjBGLIm (ORCPT ); Tue, 7 Feb 2023 06:08:42 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 642C537F02; Tue, 7 Feb 2023 03:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768119; x=1707304119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GErCnaam8qR/4c0j1O9AOMChyzVaA95w4ppDdsa2PuQ=; b=gEsVAf3RRwclBxUwzSh/Q+6zMtnCxodrnY8EaFmXl4daUVMHYDUAwHz1 hJgsDYs4MrJHG0Sp8gZdj6IiyRX4M3riaK7o++P6a/viF+5wJtdFmJWCT EPY1jGbaTtN+nxMY40KD8PPMdWCG4r9UkA97MJvxFfrShcBzSmRhTV18A C7XK3yKIj5cUz5Z4qpGZU3bcqUNOad6dCbyAtag7Z0IlYB4zI6MgOBs2A 8/CDzerr5SjKkj3dXQsI0PiIsIlEkpKG6H9KO8NQnDMuFeMVfwVOiqaj4 o37I6lna20jjHHYlFXAue5fe/a+GDVzhwS2ejcvK/MciZr+Vu1HzlGGnl w==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="199892624" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:08:34 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:08:30 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:08:21 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 6/8] ARM: dts: at91: sam9x60: Add missing flexcom definitions Date: Tue, 7 Feb 2023 16:36:49 +0530 Message-ID: <20230207110651.197268-7-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Manikandan Muralidharan Added the missing flexcom functions for all the flexcom nodes. Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: added missing UART compatibles] Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/sam9x60.dtsi | 545 +++++++++++++++++++++++++++++++++ 1 file changed, 545 insertions(+) diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 8442971458e4..91225f0fb984 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -171,6 +171,27 @@ flx4: flexcom@f0000000 { ranges =3D <0x0 0xf0000000 0x800>; status =3D "disabled"; =20 + uart4: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + spi4: spi@400 { compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg =3D <0x400 0x200>; @@ -189,6 +210,24 @@ AT91_XDMAC_DT_PER_IF(1) | atmel,fifo-size =3D <16>; status =3D "disabled"; }; + + i2c4: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx5: flexcom@f0004000 { @@ -221,6 +260,43 @@ AT91_XDMAC_DT_PER_IF(1) | atmel,fifo-size =3D <16>; status =3D "disabled"; }; + + spi5: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c5: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 dma0: dma-controller@f0008000 { @@ -292,6 +368,45 @@ flx11: flexcom@f0020000 { #size-cells =3D <1>; ranges =3D <0x0 0xf0020000 0x800>; status =3D "disabled"; + + uart11: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c11: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx12: flexcom@f0024000 { @@ -302,6 +417,45 @@ flx12: flexcom@f0024000 { #size-cells =3D <1>; ranges =3D <0x0 0xf0024000 0x800>; status =3D "disabled"; + + uart12: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c12: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 pit64b: timer@f0028000 { @@ -421,6 +575,27 @@ flx6: flexcom@f8010000 { ranges =3D <0x0 0xf8010000 0x800>; status =3D "disabled"; =20 + uart6: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + i2c6: i2c@600 { compatible =3D "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -448,6 +623,45 @@ flx7: flexcom@f8014000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8014000 0x800>; status =3D "disabled"; + + uart7: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx8: flexcom@f8018000 { @@ -458,6 +672,45 @@ flx8: flexcom@f8018000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8018000 0x800>; status =3D "disabled"; + + uart8: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c8: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx0: flexcom@f801c000 { @@ -469,6 +722,46 @@ flx0: flexcom@f801c000 { ranges =3D <0x0 0xf801c000 0x800>; status =3D "disabled"; =20 + uart0: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + i2c0: i2c@600 { compatible =3D "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -496,6 +789,64 @@ flx1: flexcom@f8020000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8020000 0x800>; status =3D "disabled"; + + uart1: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx2: flexcom@f8024000 { @@ -506,6 +857,64 @@ flx2: flexcom@f8024000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8024000 0x800>; status =3D "disabled"; + + uart2: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx3: flexcom@f8028000 { @@ -516,6 +925,64 @@ flx3: flexcom@f8028000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8028000 0x800>; status =3D "disabled"; + + uart3: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 macb0: ethernet@f802c000 { @@ -581,6 +1048,45 @@ flx9: flexcom@f8040000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8040000 0x800>; status =3D "disabled"; + + uart9: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c9: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx10: flexcom@f8044000 { @@ -591,6 +1097,45 @@ flx10: flexcom@f8044000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8044000 0x800>; status =3D "disabled"; + + uart10: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c10: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 isi: isi@f8048000 { --=20 2.25.1