From nobody Fri Sep 12 20:11:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66ECFC636CC for ; Tue, 7 Feb 2023 11:07:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231919AbjBGLHb (ORCPT ); Tue, 7 Feb 2023 06:07:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230516AbjBGLHY (ORCPT ); Tue, 7 Feb 2023 06:07:24 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAAA13866E; Tue, 7 Feb 2023 03:07:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768040; x=1707304040; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rueJZQaYj5/OCL0rhwE4IQRQNJdQeur4XqdJx6V7odE=; b=P1h8kazBf2WJwCQqoXalOfVX0QWwn9RkfPqTIIWheQbILOE+Uujtjrja o45g0uWZxM/qm+bPY8ZGzi/0zfDTGQkI2UCtBcwhBGQ2/hWb/dWvQDUw2 B8bBEVTJKTw2Ius7sAFOX0T6rCIBDNUWW8jk9xuXLU/7QdN0iKTz0B1D8 0VQWM4Hnstmt+cRAakHLTWzm8N7J2yYpct4SqzJfFCH5iaJcHm78mKYN4 X8JrvuLujSSiZbrB4LuByJKfatd3HTGyuNI3UmKTv+GtYSSpVIro4TXIz gQz5qTqmfajtyYn8NMAKAHnxIt/13L+ZcyTZsfvktgrvQPE1BvwTo/18P w==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="135929117" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:07:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:07:16 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:07:07 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 1/8] ARM: dts: at91: sam9x60: Fix the label numbering for the flexcom functions Date: Tue, 7 Feb 2023 16:36:44 +0530 Message-ID: <20230207110651.197268-2-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Manikandan Muralidharan Fixed the label numbering of the flexcom functions so that all 13 flexcom functions of sam9x60 are in the following order when the missing flexcom functions are added: flx0: uart0, spi0, i2c0 flx1: uart1, spi1, i2c1 flx2: uart2, spi2, i2c2 flx3: uart3, spi3, i2c3 flx4: uart4, spi4, i2c4 flx5: uart5, spi5, i2c5 flx6: uart6, i2c6 flx7: uart7, i2c7 flx8: uart8, i2c8 flx9: uart9, i2c9 flx10: uart10, i2c10 flx11: uart11, i2c11 flx12: uart12, i2c12 Signed-off-by: Manikandan Muralidharan Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sam9x60ek.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-= sam9x60ek.dts index d929c1ba5789..cf5d786531f2 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -16,8 +16,8 @@ / { =20 aliases { i2c0 =3D &i2c0; - i2c1 =3D &i2c1; - serial1 =3D &uart1; + i2c1 =3D &i2c6; + serial1 =3D &uart5; }; =20 chosen { @@ -234,7 +234,7 @@ &flx4 { atmel,flexcom-mode =3D ; status =3D "disabled"; =20 - spi0: spi@400 { + spi4: spi@400 { compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg =3D <0x400 0x200>; interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; @@ -253,7 +253,7 @@ &flx5 { atmel,flexcom-mode =3D ; status =3D "okay"; =20 - uart1: serial@200 { + uart5: serial@200 { compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atm= el,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg =3D <0x200 0x200>; atmel,usart-mode =3D ; @@ -279,7 +279,7 @@ &flx6 { atmel,flexcom-mode =3D ; status =3D "okay"; =20 - i2c1: i2c@600 { + i2c6: i2c@600 { compatible =3D "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; @@ -439,7 +439,7 @@ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; =20 - pinctrl_flx5_default: flx_uart { + pinctrl_flx5_default: flx5_uart { atmel,pins =3D X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60AB0C636CC for ; Tue, 7 Feb 2023 11:07:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231923AbjBGLHm (ORCPT ); Tue, 7 Feb 2023 06:07:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231266AbjBGLHj (ORCPT ); Tue, 7 Feb 2023 06:07:39 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBB4737F2A; Tue, 7 Feb 2023 03:07:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768057; x=1707304057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mjHwzmjVx5AsDKi0vsPeqIFr4VuECLn5thzx9mG1050=; b=jG7OAO+99gFZsNpY4WOSvsQPAy5JJHWHsLEWN77u2Q/EiFfKSI5d1N7X NBB0BwoMeMnXRlfA/bNHLNHv/ws5/GbUELjzxZHy8XNe6uO0x+WwkXzCi bnd5Kb3TSkPWtXU0+SH30BGB3cf7uttiMMpCiMcgdOLvVy0qjrUYhckRk Ylhb/zEWRyTvIAbUWsWwS/AF0QQI3G9WidCcT6XyQPKP78jmb9Nyjpprn uSEcYOuvsMZ5oYFFdLDMosWIuD93vvwZvz5BTjLlY3lLbkZcLSkEbN87n K3Q5rZXnYZO0r8nEv8RYqzpUKgLZjgt5OySG3XAPe602fsB8mStR+nWVx g==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="210907328" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:07:37 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:07:36 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:07:27 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 2/8] ARM: dts: at91: sam9x60: move flexcom definitions Date: Tue, 7 Feb 2023 16:36:45 +0530 Message-ID: <20230207110651.197268-3-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Manikandan Muralidharan Move the flexcom definitions from board specific DTS file to the SoC specific DTSI file for sam9x60ek. Signed-off-by: Manikandan Muralidharan Signed-off-by: Hari Prasath Gujulan Elango [durai.manickamkr@microchip.com: Logical split-up of this patch and added missing UART5 compatibles] Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sam9x60ek.dts | 33 +------------------ arch/arm/boot/dts/sam9x60.dtsi | 49 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-= sam9x60ek.dts index cf5d786531f2..4ff84633dd43 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -207,15 +207,10 @@ &flx0 { status =3D "okay"; =20 i2c0: i2c@600 { - compatible =3D "microchip,sam9x60-i2c"; - reg =3D <0x600 0x200>; - interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; #address-cells =3D <1>; #size-cells =3D <0>; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_flx0_default>; - atmel,fifo-size =3D <16>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns =3D <35>; @@ -235,14 +230,8 @@ &flx4 { status =3D "disabled"; =20 spi4: spi@400 { - compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg =3D <0x400 0x200>; - interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names =3D "spi_clk"; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_flx4_default>; - atmel,fifo-size =3D <16>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -254,23 +243,8 @@ &flx5 { status =3D "okay"; =20 uart5: serial@200 { - compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atm= el,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg =3D <0x200 0x200>; - atmel,usart-mode =3D ; - interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; - dmas =3D <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(10))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>; - dma-names =3D "tx", "rx"; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names =3D "usart"; - pinctrl-0 =3D <&pinctrl_flx5_default>; pinctrl-names =3D "default"; - atmel,use-dma-rx; - atmel,use-dma-tx; + pinctrl-0 =3D <&pinctrl_flx5_default>; status =3D "okay"; }; }; @@ -280,15 +254,10 @@ &flx6 { status =3D "okay"; =20 i2c6: i2c@600 { - compatible =3D "microchip,sam9x60-i2c"; - reg =3D <0x600 0x200>; - interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; #address-cells =3D <1>; #size-cells =3D <0>; - clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_flx6_default>; - atmel,fifo-size =3D <16>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns =3D <35>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 8f5477e307dd..ee6cc4329ae4 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -170,6 +170,16 @@ flx4: flexcom@f0000000 { #size-cells =3D <1>; ranges =3D <0x0 0xf0000000 0x800>; status =3D "disabled"; + + spi4: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "spi_clk"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx5: flexcom@f0004000 { @@ -180,6 +190,27 @@ flx5: flexcom@f0004000 { #size-cells =3D <1>; ranges =3D <0x0 0xf0004000 0x800>; status =3D "disabled"; + + uart5: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + atmel,usart-mode =3D ; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status =3D "disabled"; + }; }; =20 dma0: dma-controller@f0008000 { @@ -379,6 +410,15 @@ flx6: flexcom@f8010000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8010000 0x800>; status =3D "disabled"; + + i2c6: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx7: flexcom@f8014000 { @@ -409,6 +449,15 @@ flx0: flexcom@f801c000 { #size-cells =3D <1>; ranges =3D <0x0 0xf801c000 0x800>; status =3D "disabled"; + + i2c0: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx1: flexcom@f8020000 { --=20 2.25.1 From nobody Fri Sep 12 20:11:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14B1BC636CC for ; Tue, 7 Feb 2023 11:08:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231927AbjBGLH5 (ORCPT ); Tue, 7 Feb 2023 06:07:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231933AbjBGLHw (ORCPT ); Tue, 7 Feb 2023 06:07:52 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD08F38024; Tue, 7 Feb 2023 03:07:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768072; x=1707304072; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p6Kji/TJYZJzNMpJy1w1p5Y3R+ZBdEpdO8oW5jbtFpc=; b=YGSxDSg7kGLfUCem/uyPMlD7OeR9/ill4R9IZtu/Q9jN4k+4hYbzT7Q0 Bsdb8Ry4+n4dO1sTvLWSs8szJ9ZSqBuucQIxy86F0eQIlWPNhcdLLLD02 7jINXJlr4mlTxynZDmiZvvzgo++mTz2kbXWlqJx3kQL33tFtxgOyZhyOX aHIYkFjTFLETPji7hiIL0L/x9j+9LIMNHE952L68hZsqG9zjSW4tMxjWF 9XdZneRmcOCvFG1YTAWNLyJ94iFuzntXdpGD85kSZS4AoNTUFBo2CuuQb lIKMG5YwR2+diynWLs4hHQYIpytr3gwTptNrb4jWi2/u7q4LXUEPe7i7A Q==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="195720583" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:07:51 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:07:49 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:07:39 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 3/8] ARM: dts: at91: sam9x60: fix spi4 node Date: Tue, 7 Feb 2023 16:36:46 +0530 Message-ID: <20230207110651.197268-4-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ranges, #address-cells and #size-cells properties are not required, remove them from the spi4 node. Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sam9x60ek.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-= sam9x60ek.dts index 4ff84633dd43..6b6391d5041e 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -232,8 +232,6 @@ &flx4 { spi4: spi@400 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_flx4_default>; - #address-cells =3D <1>; - #size-cells =3D <0>; status =3D "disabled"; }; }; --=20 2.25.1 From nobody Fri Sep 12 20:11:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BD67C636D6 for ; Tue, 7 Feb 2023 11:08:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231929AbjBGLIR (ORCPT ); Tue, 7 Feb 2023 06:08:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231935AbjBGLIJ (ORCPT ); Tue, 7 Feb 2023 06:08:09 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1E1A3757F; Tue, 7 Feb 2023 03:08:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768086; x=1707304086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kibqO0YpM7UaIfNnh1seK66BbS3IQS1tOIJMA8jsTZ0=; b=K3/Fh/CwwPgGM+xc8/kw0pSYZCXKfKo/48oQqsTPlQEdhWFOq7KR4DEc 4oy0eg2iwq2S9OyP61HDzhsbKfVMu/NyHAbd2DeNghP3MWXe7nnyoJ5KD GMd2QdP4C57TGL00TWR8vehGiS2hcC04vDQdFgW7+Ai84rdkFWJCHZj8a WihFmjATcJw6LtU7yEKq5OcFvaBLR2bs1KSAr4HRyHaCFHxk6EYA05QV7 frGl46B+nF9rAE5ubL8c8eGrscShsnTTlD98xELttp98YMH08tvGIz7Ov ziuvVDqlRs6d8qJjRGAfSiKI+6YIDtkZMKif6ZFbeQGu6O2g7h0kGE+I4 Q==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="199283485" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:08:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:08:03 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:07:53 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 4/8] ARM: dts: at91: sam9x60: Specify the FIFO size for the Flexcom UART Date: Tue, 7 Feb 2023 16:36:47 +0530 Message-ID: <20230207110651.197268-5-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Manikandan Muralidharan The UART submodule in Flexcom has 16-byte Transmit and Receive FIFOs. Signed-off-by: Manikandan Muralidharan Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/sam9x60.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index ee6cc4329ae4..1e401a919f56 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -209,6 +209,7 @@ AT91_XDMAC_DT_PER_IF(1) | clock-names =3D "usart"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size =3D <16>; status =3D "disabled"; }; }; --=20 2.25.1 From nobody Fri Sep 12 20:11:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB56AC636D6 for ; Tue, 7 Feb 2023 11:08:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231937AbjBGLI1 (ORCPT ); Tue, 7 Feb 2023 06:08:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231184AbjBGLIU (ORCPT ); Tue, 7 Feb 2023 06:08:20 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3365638033; Tue, 7 Feb 2023 03:08:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768099; x=1707304099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yzMU5+tyWNsi37KdlDLEIsJGVyKaMVo94ixAwQFMfcM=; b=vglGeBC5QpVnKGbi3+Qr6MOlVUpKtcmaX1KmHUNjUT99ON4Rk8Epw+II lnsAuLB0TNIO2ixwMW9QTTgbt6JEIlrlKp3LTy8iMizekKgBQILlGVonv dgUZOajlbbOP0Rh7BNylgUdzp29zf2h0a4JUKLNVhHUX2PZinXcUQvHLm VJ2z7wYwUDSWZrynsEI23NveciifQ1NRoDkdmc5WjWJIHCzfXR8dKDHyV eCiOKWPvjhoQI8LUum5q5JiJgljQaisrIqRMORx/Htp43aU3PlI3aNEHR Xe6vBfRotl0sShAqYIfqOr9oiVKwkCN3RCujOGZPUGj12BCRNQgEoHFaR Q==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="135929239" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:08:18 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:08:17 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:08:09 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 5/8] ARM: dts: at91: sam9x60: Add DMA bindings for the flexcom nodes Date: Tue, 7 Feb 2023 16:36:48 +0530 Message-ID: <20230207110651.197268-6-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Manikandan Muralidharan Add dma bindings for flexcom nodes in the soc dtsi file. Users those who don't wish to use the DMA function for their flexcom functions can overwrite the dma bindings in the board device tree file. Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: fixed code indentation and updated commit = log] Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sam9x60ek.dts | 3 +++ arch/arm/boot/dts/sam9x60.dtsi | 27 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-= sam9x60ek.dts index 6b6391d5041e..180e4b1aa2f6 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -209,6 +209,7 @@ &flx0 { i2c0: i2c@600 { #address-cells =3D <1>; #size-cells =3D <0>; + dmas =3D <0>, <0>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_flx0_default>; i2c-analog-filter; @@ -230,6 +231,7 @@ &flx4 { status =3D "disabled"; =20 spi4: spi@400 { + dmas =3D <0>, <0>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_flx4_default>; status =3D "disabled"; @@ -254,6 +256,7 @@ &flx6 { i2c6: i2c@600 { #address-cells =3D <1>; #size-cells =3D <0>; + dmas =3D <0>, <0>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_flx6_default>; i2c-analog-filter; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 1e401a919f56..8442971458e4 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -177,6 +177,15 @@ spi4: spi@400 { interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; atmel,fifo-size =3D <16>; status =3D "disabled"; }; @@ -417,6 +426,15 @@ i2c6: i2c@600 { reg =3D <0x600 0x200>; interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; atmel,fifo-size =3D <16>; status =3D "disabled"; }; @@ -456,6 +474,15 @@ i2c0: i2c@600 { reg =3D <0x600 0x200>; interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; atmel,fifo-size =3D <16>; status =3D "disabled"; }; --=20 2.25.1 From nobody Fri Sep 12 20:11:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89B11C6379F for ; Tue, 7 Feb 2023 11:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231934AbjBGLIp (ORCPT ); Tue, 7 Feb 2023 06:08:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230193AbjBGLIm (ORCPT ); Tue, 7 Feb 2023 06:08:42 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 642C537F02; Tue, 7 Feb 2023 03:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768119; x=1707304119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GErCnaam8qR/4c0j1O9AOMChyzVaA95w4ppDdsa2PuQ=; b=gEsVAf3RRwclBxUwzSh/Q+6zMtnCxodrnY8EaFmXl4daUVMHYDUAwHz1 hJgsDYs4MrJHG0Sp8gZdj6IiyRX4M3riaK7o++P6a/viF+5wJtdFmJWCT EPY1jGbaTtN+nxMY40KD8PPMdWCG4r9UkA97MJvxFfrShcBzSmRhTV18A C7XK3yKIj5cUz5Z4qpGZU3bcqUNOad6dCbyAtag7Z0IlYB4zI6MgOBs2A 8/CDzerr5SjKkj3dXQsI0PiIsIlEkpKG6H9KO8NQnDMuFeMVfwVOiqaj4 o37I6lna20jjHHYlFXAue5fe/a+GDVzhwS2ejcvK/MciZr+Vu1HzlGGnl w==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="199892624" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:08:34 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:08:30 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:08:21 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 6/8] ARM: dts: at91: sam9x60: Add missing flexcom definitions Date: Tue, 7 Feb 2023 16:36:49 +0530 Message-ID: <20230207110651.197268-7-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Manikandan Muralidharan Added the missing flexcom functions for all the flexcom nodes. Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: added missing UART compatibles] Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/sam9x60.dtsi | 545 +++++++++++++++++++++++++++++++++ 1 file changed, 545 insertions(+) diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 8442971458e4..91225f0fb984 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -171,6 +171,27 @@ flx4: flexcom@f0000000 { ranges =3D <0x0 0xf0000000 0x800>; status =3D "disabled"; =20 + uart4: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + spi4: spi@400 { compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg =3D <0x400 0x200>; @@ -189,6 +210,24 @@ AT91_XDMAC_DT_PER_IF(1) | atmel,fifo-size =3D <16>; status =3D "disabled"; }; + + i2c4: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx5: flexcom@f0004000 { @@ -221,6 +260,43 @@ AT91_XDMAC_DT_PER_IF(1) | atmel,fifo-size =3D <16>; status =3D "disabled"; }; + + spi5: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c5: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 dma0: dma-controller@f0008000 { @@ -292,6 +368,45 @@ flx11: flexcom@f0020000 { #size-cells =3D <1>; ranges =3D <0x0 0xf0020000 0x800>; status =3D "disabled"; + + uart11: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c11: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx12: flexcom@f0024000 { @@ -302,6 +417,45 @@ flx12: flexcom@f0024000 { #size-cells =3D <1>; ranges =3D <0x0 0xf0024000 0x800>; status =3D "disabled"; + + uart12: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c12: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 pit64b: timer@f0028000 { @@ -421,6 +575,27 @@ flx6: flexcom@f8010000 { ranges =3D <0x0 0xf8010000 0x800>; status =3D "disabled"; =20 + uart6: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + i2c6: i2c@600 { compatible =3D "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -448,6 +623,45 @@ flx7: flexcom@f8014000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8014000 0x800>; status =3D "disabled"; + + uart7: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx8: flexcom@f8018000 { @@ -458,6 +672,45 @@ flx8: flexcom@f8018000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8018000 0x800>; status =3D "disabled"; + + uart8: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c8: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx0: flexcom@f801c000 { @@ -469,6 +722,46 @@ flx0: flexcom@f801c000 { ranges =3D <0x0 0xf801c000 0x800>; status =3D "disabled"; =20 + uart0: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + i2c0: i2c@600 { compatible =3D "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -496,6 +789,64 @@ flx1: flexcom@f8020000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8020000 0x800>; status =3D "disabled"; + + uart1: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx2: flexcom@f8024000 { @@ -506,6 +857,64 @@ flx2: flexcom@f8024000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8024000 0x800>; status =3D "disabled"; + + uart2: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx3: flexcom@f8028000 { @@ -516,6 +925,64 @@ flx3: flexcom@f8028000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8028000 0x800>; status =3D "disabled"; + + uart3: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 macb0: ethernet@f802c000 { @@ -581,6 +1048,45 @@ flx9: flexcom@f8040000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8040000 0x800>; status =3D "disabled"; + + uart9: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c9: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 flx10: flexcom@f8044000 { @@ -591,6 +1097,45 @@ flx10: flexcom@f8044000 { #size-cells =3D <1>; ranges =3D <0x0 0xf8044000 0x800>; status =3D "disabled"; + + uart10: serial@200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "= atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c10: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; }; =20 isi: isi@f8048000 { --=20 2.25.1 From nobody Fri Sep 12 20:11:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BA33C636CC for ; Tue, 7 Feb 2023 11:08:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231225AbjBGLIy (ORCPT ); Tue, 7 Feb 2023 06:08:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231160AbjBGLIv (ORCPT ); Tue, 7 Feb 2023 06:08:51 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B29D39BAA; Tue, 7 Feb 2023 03:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768123; x=1707304123; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p1lbUVhb7i+rNn22EBbKPX27IsYE8BqOKDNggZDvwDs=; b=Y7ATvVS//3N4W8ReMPTkvc8FGAiZCLdrMAMKyPBeTodXwGloKmPcjXTY /TKHpKAO8lIf5x2uI4tvXNVzw48Oz8GQBSiwTm+d8qalJY9ty+CY/tpus P9VktByis0Gq/ulUxXdheW9Cn7KLSsjPJMNKxEd0JyDvvP3RNMgd50uLL 64eQ4XpMD+MR7MNlzQ7RIln9ZNHIsCtxETMKfVpf3wljuYJG3QSq+Z8IY opMvhDmC7T36KcDuPtdJnallEAdvruktMfrgMVjU7WUCARxcEuNrNOhd0 a9K8oH9zSecgR468yuWTWo0TEUOWagHV6MsamDvVcqByX9TGQU3aZEMyT Q==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="199283546" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:08:43 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:08:42 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:08:32 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 7/8] dt-bindings: arm: at91: Add info on sam9x60 curiosity Date: Tue, 7 Feb 2023 16:36:50 +0530 Message-ID: <20230207110651.197268-8-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adding the sam9x60 curiosity board from Microchip into the atmel AT91 board description yaml file. Signed-off-by: Durai Manickam KR Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Docume= ntation/devicetree/bindings/arm/atmel-at91.yaml index 2224b18801a1..dfb8fd089197 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -91,9 +91,11 @@ properties: - const: atmel,sama5d2 - const: atmel,sama5 =20 - - description: SAM9X60-EK board + - description: Microchip SAM9X60 Evaluation Boards items: - - const: microchip,sam9x60ek + - enum: + - microchip,sam9x60ek + - microchip,sam9x60-curiosity - const: microchip,sam9x60 - const: atmel,at91sam9 =20 --=20 2.25.1 From nobody Fri Sep 12 20:11:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73ACFC636CC for ; Tue, 7 Feb 2023 11:09:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229755AbjBGLJU (ORCPT ); Tue, 7 Feb 2023 06:09:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231169AbjBGLJL (ORCPT ); Tue, 7 Feb 2023 06:09:11 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EDEE39CED; Tue, 7 Feb 2023 03:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675768135; x=1707304135; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m4yDL+XtCPg6VU7kOr4gaZmDDqQEWDGR+by0TA/Nh8Y=; b=YlVgiXdVrho8o5ccvuM/Bm5lXCp2/JaG2XDB2VqBUmyc/fuA+dYzgUMF UuXEwmz8Ub/JZ/1AMadGnoqyww9i+xoiDh5QmsClULK9J7++JXbwZiw62 FQf/42vuuCJia2P9KrSH2Rm9i8MPBRHjlRJyDIqdg0wanQx+YF9+jDSik H/E8Hcc6ekWIF5uD0Qlo7+diSOV3aB298rIvTVNdH+yH6aumuhD5wKLap ratZT+g9nnGkaw1SiVJpQHdn7qh+X695Nm4ryb/MOLJfWuosLV+kCUUCG oKXsGw1ANTMlWnbivHaT4e/Mj37kIH0p0kW8fJNwS8HUWp0ig3DbWD0b7 Q==; X-IronPort-AV: E=Sophos;i="5.97,278,1669100400"; d="scan'208";a="195720687" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Feb 2023 04:08:55 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 7 Feb 2023 04:08:52 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 7 Feb 2023 04:08:43 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCH v6 8/8] ARM: dts: at91: sam9x60_curiosity: Add device tree for sam9x60 curiosity board Date: Tue, 7 Feb 2023 16:36:51 +0530 Message-ID: <20230207110651.197268-9-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207110651.197268-1-durai.manickamkr@microchip.com> References: <20230207110651.197268-1-durai.manickamkr@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree file for sam9x60 curiosity board. Signed-off-by: Durai Manickam KR Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-sam9x60_curiosity.dts | 503 +++++++++++++++++++ 2 files changed, 504 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sam9x60_curiosity.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6aa7dc4db2fc..da20980384c4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) +=3D \ at91sam9x25ek.dtb \ at91sam9x35ek.dtb dtb-$(CONFIG_SOC_SAM9X60) +=3D \ + at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb dtb-$(CONFIG_SOC_SAM_V7) +=3D \ at91-kizbox2-2.dtb \ diff --git a/arch/arm/boot/dts/at91-sam9x60_curiosity.dts b/arch/arm/boot/d= ts/at91-sam9x60_curiosity.dts new file mode 100644 index 000000000000..cb86a3a170ce --- /dev/null +++ b/arch/arm/boot/dts/at91-sam9x60_curiosity.dts @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Cur= iosity board + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Durai Manickam KR + */ +/dts-v1/; +#include "sam9x60.dtsi" +#include + +/ { + model =3D "Microchip SAM9X60 Curiosity"; + compatible =3D "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel= ,at91sam9"; + + aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c6; + serial2 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@20000000 { + reg =3D <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency =3D <32768>; + }; + + main_xtal { + clock-frequency =3D <24000000>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_key_gpio_default>; + + button-user { + label =3D "PB_USER"; + gpios =3D <&pioA 29 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_leds>; + + led-red { + label =3D "red"; + gpios =3D <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label =3D "green"; + gpios =3D <&pioD 19 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label =3D "blue"; + gpios =3D <&pioD 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + + vdd_1v8: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "VDD_1V8"; + }; + + vdd_1v15: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <1150000>; + regulator-min-microvolt =3D <1150000>; + regulator-name =3D "VDD_1V15"; + }; + + vdd1_3v3: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VDD1_3V3"; + }; +}; + +&adc { + vddana-supply =3D <&vdd1_3v3>; + vref-supply =3D <&vdd1_3v3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc_default &pinctrl_adtrg_default>; + status =3D "okay"; +}; + +&can0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can0_rx_tx>; + status =3D "disabled"; /* Conflict with dbgu. */ +}; + +&can1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can1_rx_tx>; + status =3D "okay"; +}; + +&dbgu { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dbgu>; + status =3D "okay"; /* Conflict with can0. */ +}; + +&ebi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_lsb>; + status =3D "okay"; + + nand_controller: nand-controller { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; + status =3D "okay"; + + nand@3 { + reg =3D <0x3 0x0 0x800000>; + rb-gpios =3D <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios =3D <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width =3D <8>; + nand-ecc-mode =3D "hw"; + nand-ecc-strength =3D <8>; + nand-ecc-step-size =3D <512>; + nand-on-flash-bbt; + label =3D "atmel_nand"; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + at91bootstrap@0 { + label =3D "at91bootstrap"; + reg =3D <0x0 0x40000>; + }; + + uboot@40000 { + label =3D "u-boot"; + reg =3D <0x40000 0xc0000>; + }; + + ubootenvred@100000 { + label =3D "U-Boot Env Redundant"; + reg =3D <0x100000 0x40000>; + }; + + ubootenv@140000 { + label =3D "U-Boot Env"; + reg =3D <0x140000 0x40000>; + }; + + dtb@180000 { + label =3D "device tree"; + reg =3D <0x180000 0x80000>; + }; + + kernel@200000 { + label =3D "kernel"; + reg =3D <0x200000 0x600000>; + }; + + rootfs@800000 { + label =3D "rootfs"; + reg =3D <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + +&flx0 { + atmel,flexcom-mode =3D ; + status =3D "okay"; + + i2c0: i2c@600 { + dmas =3D <0>, <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx0_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + status =3D "okay"; + + eeprom@53 { + compatible =3D "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + }; + }; +}; + +&flx6 { + atmel,flexcom-mode =3D ; + status =3D "okay"; + + i2c6: i2c@600 { + dmas =3D <0>, <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + status =3D "disabled"; + }; +}; + +&flx7 { + atmel,flexcom-mode =3D ; + status =3D "okay"; + + uart7: serial@200 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx7_default>; + status =3D "okay"; + }; +}; + +&macb0 { + phy-mode =3D "rmii"; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_macb0_rmii>; + status =3D "okay"; + + ethernet-phy@0 { + reg =3D <0x0>; + }; +}; + +&pinctrl { + adc { + pinctrl_adc_default: adc-default { + atmel,pins =3D ; + }; + + pinctrl_adtrg_default: adtrg-default { + atmel,pins =3D ; + }; + }; + + can0 { + pinctrl_can0_rx_tx: can0-rx-tx { + atmel,pins =3D + ; /* Enable CAN T= ransceivers */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1-rx-tx { + atmel,pins =3D + ; /* Enable CAN = Transceivers */ + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins =3D ; + }; + }; + + ebi { + pinctrl_ebi_data_lsb: ebi-data-lsb { + atmel,pins =3D + ; + }; + + pinctrl_ebi_addr_nand: ebi-addr-nand { + atmel,pins =3D + ; + }; + }; + + flexcom { + pinctrl_flx0_default: flx0-twi { + atmel,pins =3D + ; + }; + + pinctrl_flx6_default: flx6-twi { + atmel,pins =3D + ; + }; + + pinctrl_flx7_default: flx7-usart { + atmel,pins =3D + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: pinctrl-key-gpio { + atmel,pins =3D ; + }; + }; + + leds { + pinctrl_gpio_leds: gpio-leds { + atmel,pins =3D ; + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0-rmii-0 { + atmel,pins =3D + ; /* PB10 periph A */ + }; + }; + + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins =3D + ; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins =3D + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins =3D + ; + }; + }; + + pwm0 { + pinctrl_pwm0_0: pwm0-0 { + atmel,pins =3D ; + }; + + pinctrl_pwm0_1: pwm0-1 { + atmel,pins =3D ; + }; + + pinctrl_pwm0_2: pwm0-2 { + atmel,pins =3D ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0 { + atmel,pins =3D + ; /* PA20 DAT3 periph A with pullup */ + }; + + pinctrl_sdmmc0_cd: sdmmc0-cd { + atmel,pins =3D + ; + }; + }; + + sdmmc1 { + pinctrl_sdmmc1_default: sdmmc1 { + atmel,pins =3D + ; /* PA4 DAT3 periph B with pullup */ + }; + }; + + usb0 { + pinctrl_usba_vbus: usba-vbus { + atmel,pins =3D ; + }; + }; + + usb1 { + pinctrl_usb_default: usb-default { + atmel,pins =3D ; + }; + }; +}; /* pinctrl */ + +&pwm0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2>; + status =3D "okay"; +}; + +&sdmmc0 { + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>; + cd-gpios =3D <&pioA 25 GPIO_ACTIVE_LOW>; + disable-wp; + status =3D "okay"; +}; + +&sdmmc1 { + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sdmmc1_default>; + disable-wp; + status =3D "okay"; +}; + +&shutdown_controller { + debounce-delay-us =3D <976>; + status =3D "okay"; + + input@0 { + reg =3D <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible =3D "atmel,tcb-timer"; + reg =3D <0>; + }; + + timer1: timer@1 { + compatible =3D "atmel,tcb-timer"; + reg =3D <1>; + }; +}; + +&usb0 { + atmel,vbus-gpio =3D <&pioA 27 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usba_vbus>; + status =3D "okay"; +}; + +&usb1 { + num-ports =3D <3>; + atmel,vbus-gpio =3D <0 + &pioD 18 GPIO_ACTIVE_HIGH + &pioD 15 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_default>; + status =3D "okay"; +}; + +&usb2 { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.25.1