From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD3DDC636D4 for ; Tue, 7 Feb 2023 09:56:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231725AbjBGJ4f (ORCPT ); Tue, 7 Feb 2023 04:56:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231611AbjBGJ4b (ORCPT ); Tue, 7 Feb 2023 04:56:31 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13748EFB7 for ; Tue, 7 Feb 2023 01:56:30 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id r8so15117132pls.2 for ; Tue, 07 Feb 2023 01:56:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WKlW5q6yjuU3XeXevn1T+f+MrCmphziSra4SvghaxAg=; b=TEnaVT7PYxs4JyVGUW6aY4WTRKeyCKV8ouUmBA2lK0Wh+OV9/pKI3c6QgalkAP9Xh3 nW+gy6DwMm6B3tZ9tz2nRkuX6ty+qBeE6OVOA/vQrmmY122FxcaZzzSNyIwhUu/7p8Gq QE84NMjs0x7xKhxQXO6UWhQ/7tBjt0Uhkxog8S9JJGHeGr/4cRDR5QPRZivUCwS+1C1F A3Le5MZ4Yfh/x1wMnMZogTqRJ/b9yidFBuW0Orh33akhAvYA4pF6CGNwD4LHxjZQrEVa ClgnMuK0Z9FvHUf4+27bpLhrb1EE3NWL8Y4pGVeGwvVVw0A+IxxSHQr99llwYnK++f1b t8Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WKlW5q6yjuU3XeXevn1T+f+MrCmphziSra4SvghaxAg=; b=pGo376uhyEG5B5+BpJq/ooYH9sSAZk8n+C8aM9X+DmsHsZY7M8rdKh+F9Fe/pOMUYv hoYpAwAxlqEMqxZjkEsaFHQu/nGCn/HrMIirGzXN7D2fhfT/YxIUVTH/LOrQo+6pjPpC gR8lrdkOJEkN6Rrg21/l1N33JpseqUz5lGhN733H8CZFNsoqkl3dbZQ2NY5PWjQh7O3W VrYih9lmcKfr0TMUrGUXRQ9T/0Tg4GgVyKp4/C1FGbwLdjznGfK3/S8Y1YlVnSa6HwXc XJ55pSRjGNMERhPqw+mKj5OqLZ4sQLFeNZpibrYlkC63qhM9RnlV/4oId4CZ2IjZcYvs OXtA== X-Gm-Message-State: AO0yUKXrg165Gw45Jt5iWWZcsQ5noNIUy+9sN3+ltQoHcYsDQsVhH2yZ uwDoRglCbORTfLrMa6mDCA6SrFA7nhYTmvJy X-Google-Smtp-Source: AK7set+90CMMp0x7RiSYU1Hdnxx79pQK8RCRBSydQXwsuooxNy600xIHu64/eDHl1N4YOnE1i7R8lg== X-Received: by 2002:a17:902:d294:b0:198:fd67:ba33 with SMTP id t20-20020a170902d29400b00198fd67ba33mr1879753plc.19.1675763789262; Tue, 07 Feb 2023 01:56:29 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w8-20020a1709027b8800b0019602b2c00csm4030598pll.175.2023.02.07.01.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 01:56:28 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 1/8] RISC-V: KVM: Add skeleton support for perf Date: Tue, 7 Feb 2023 01:55:22 -0800 Message-Id: <20230207095529.1787260-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch only adds barebone structure of perf implementation. Most of the function returns zero at this point and will be implemented fully in the future. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_pmu.h | 75 ++++++++++++++ arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 7 ++ arch/riscv/kvm/vcpu_pmu.c | 138 ++++++++++++++++++++++++++ 5 files changed, 225 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_pmu.h create mode 100644 arch/riscv/kvm/vcpu_pmu.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 93f43a3..b90be9a 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -18,6 +18,7 @@ #include #include #include +#include =20 #define KVM_MAX_VCPUS 1024 =20 @@ -228,6 +229,9 @@ struct kvm_vcpu_arch { =20 /* Don't run the VCPU (blocked) */ bool pause; + + /* Performance monitoring context */ + struct kvm_pmu pmu_context; }; =20 static inline void kvm_arch_hardware_unsetup(void) {} diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h new file mode 100644 index 0000000..0b86a47 --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#ifndef __KVM_VCPU_RISCV_PMU_H +#define __KVM_VCPU_RISCV_PMU_H + +#include +#include +#include + +#ifdef CONFIG_RISCV_PMU_SBI +#define RISCV_KVM_MAX_FW_CTRS 32 +#define RISCV_KVM_MAX_HW_CTRS 32 +#define RISCV_KVM_MAX_COUNTERS (RISCV_KVM_MAX_HW_CTRS + RISCV_KVM_MAX_FW_C= TRS) +static_assert(RISCV_KVM_MAX_COUNTERS <=3D 64); + +/* Per virtual pmu counter data */ +struct kvm_pmc { + u8 idx; + struct perf_event *perf_event; + u64 counter_val; + union sbi_pmu_ctr_info cinfo; + /* Event monitoring status */ + bool started; +}; + +/* PMU data structure per vcpu */ +struct kvm_pmu { + struct kvm_pmc pmc[RISCV_KVM_MAX_COUNTERS]; + /* Number of the virtual firmware counters available */ + int num_fw_ctrs; + /* Number of the virtual hardware counters available */ + int num_hw_ctrs; + /* A flag to indicate that pmu initialization is done */ + bool init_done; + /* Bit map of all the virtual counter used */ + DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); +}; + +#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu_context) +#define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu_c= ontext)) + +int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _return *retdata); +int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_= base, + unsigned long ctr_mask, unsigned long flags, u64 ival, + struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_b= ase, + unsigned long ctr_mask, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long = ctr_base, + unsigned long ctr_mask, unsigned long flags, + unsigned long eidx, u64 evtdata, + struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_return *retdata); +void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); + +#else +struct kvm_pmu { +}; + +static inline void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) {} +static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {} +static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {} +#endif /* CONFIG_RISCV_PMU_SBI */ +#endif /* !__KVM_VCPU_RISCV_PMU_H */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 019df920..5de1053 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -25,3 +25,4 @@ kvm-y +=3D vcpu_sbi_base.o kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_hsm.o kvm-y +=3D vcpu_timer.o +kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7c08567..7d010b0 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -138,6 +138,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) WRITE_ONCE(vcpu->arch.irqs_pending, 0); WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); =20 + kvm_riscv_vcpu_pmu_reset(vcpu); + vcpu->arch.hfence_head =3D 0; vcpu->arch.hfence_tail =3D 0; memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); @@ -194,6 +196,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) /* Setup VCPU timer */ kvm_riscv_vcpu_timer_init(vcpu); =20 + /* setup performance monitoring */ + kvm_riscv_vcpu_pmu_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); =20 @@ -216,6 +221,8 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) /* Cleanup VCPU timer */ kvm_riscv_vcpu_timer_deinit(vcpu); =20 + kvm_riscv_vcpu_pmu_deinit(vcpu); + /* Free unused pages pre-allocated for G-stage page table mappings */ kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); } diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c new file mode 100644 index 0000000..e79721b --- /dev/null +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) + +int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _return *retdata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + retdata->out_val =3D kvm_pmu_num_counters(kvpmu); + + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_return *retdata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + if (cidx > RISCV_KVM_MAX_COUNTERS || cidx =3D=3D 1) { + retdata->err_val =3D SBI_ERR_INVALID_PARAM; + return 0; + } + + retdata->out_val =3D kvpmu->pmc[cidx].cinfo.value; + + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_= base, + unsigned long ctr_mask, unsigned long flags, u64 ival, + struct kvm_vcpu_sbi_return *retdata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_b= ase, + unsigned long ctr_mask, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long = ctr_base, + unsigned long ctr_mask, unsigned long flags, + unsigned long eidx, u64 evtdata, + struct kvm_vcpu_sbi_return *retdata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_return *retdata) +{ + /* TODO */ + return 0; +} + +void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) +{ + int i =3D 0, ret, num_hw_ctrs =3D 0, hpm_width =3D 0; + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + + ret =3D riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs); + if (ret < 0 || !hpm_width || !num_hw_ctrs) + return; + /* + * Increase the number of hardware counters to offset the time counter. + */ + kvpmu->num_hw_ctrs =3D num_hw_ctrs + 1; + kvpmu->num_fw_ctrs =3D SBI_PMU_FW_MAX; + + if (kvpmu->num_hw_ctrs > RISCV_KVM_MAX_HW_CTRS) { + pr_warn("Limiting the hardware counters to 32 as specified by the ISA"); + kvpmu->num_hw_ctrs =3D RISCV_KVM_MAX_HW_CTRS; + } + /* + * There is no correlation between the logical hardware counter and virtu= al counters. + * However, we need to encode a hpmcounter CSR in the counter info field = so that + * KVM can trap n emulate the read. This works well in the migration use = case as + * KVM doesn't care if the actual hpmcounter is available in the hardware= or not. + */ + for (i =3D 0; i < kvm_pmu_num_counters(kvpmu); i++) { + /* TIME CSR shouldn't be read from perf interface */ + if (i =3D=3D 1) + continue; + pmc =3D &kvpmu->pmc[i]; + pmc->idx =3D i; + if (i < kvpmu->num_hw_ctrs) { + pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_HW; + if (i < 3) + /* CY, IR counters */ + pmc->cinfo.width =3D 63; + else + pmc->cinfo.width =3D hpm_width; + /* + * The CSR number doesn't have any relation with the logical + * hardware counters. The CSR numbers are encoded sequentially + * to avoid maintaining a map between the virtual counter + * and CSR number. + */ + pmc->cinfo.csr =3D CSR_CYCLE + i; + } else { + pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_FW; + pmc->cinfo.width =3D BITS_PER_LONG - 1; + } + } + + kvpmu->init_done =3D true; +} + +void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) +{ + /* TODO */ +} + +void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) +{ + kvm_riscv_vcpu_pmu_deinit(vcpu); +} --=20 2.25.1 From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADF01C636D4 for ; Tue, 7 Feb 2023 09:56:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231715AbjBGJ4h (ORCPT ); Tue, 7 Feb 2023 04:56:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231666AbjBGJ4c (ORCPT ); Tue, 7 Feb 2023 04:56:32 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3E8D2413B for ; Tue, 7 Feb 2023 01:56:30 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id b5so15105458plz.5 for ; Tue, 07 Feb 2023 01:56:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ULNMR5Ocp1PNupfsvdIL5d5DRjzc3aRnh38pGV22zi8=; b=jsjQLmEJu+Rf0RpzAP/8uCkuDH7Fs1becZ1ts0p7Hvoy50DATjr45e9mlXtoYslWtR pxbIzrmWILftf2D7niL8fzkr8FCZAjVX0iEK51k1CuArIWvMGgRRpbBbBwkVVW7kfPcJ KJphmdFZq4DE92KoQXhyr7iEr0mr/BKhFNyJswMIKr3T+xelrNs5WketOf+hFAQTourP NnwseEesdgNLnxOZuKAi0VVlAQ//T4ji4CyRPrvo6he50/wsan2Ll3cxp8llQNZ/Z5O1 SmX8HNJoGEAVJGo2ZEMYXa2gYT5MBZxUhnxK5T/5BMC0injae9zwMTVGvpKCpHZQ4Lpb LCkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ULNMR5Ocp1PNupfsvdIL5d5DRjzc3aRnh38pGV22zi8=; b=HHip/nwJyDR0hznyzilVCpLJBOkYJrRqKve8Xas2HUhnAwX16ObMHoUPpw2ZPEXGCG //Jdj9B1YK7PEFCOYX+newsJQRotUzsWUfyS35QbcEm6i4mSqJ1B/0mWfCu+X84ImZxB KurHuHehztLTH7bV9J8IsjKPxrvAUgGz8y+u1AL40NS4d0ERNqwaFf0FyLQHph/zDBJf ikgeFEOgKDc8tI2GkXdSckONYz/iBHz7V84ALP+Fl7xCkolDRbe5R5Y1DO5+jutSkxjG rM8TBgpcpQXUh9HnL/spu0R7LRj4JeUPj05TuklFKWKqt+himEcy34ZPzuvfxszFUdys JxUg== X-Gm-Message-State: AO0yUKWaD8CmF0Zf1G9jYNuiTmxUCggqNW46JjUXYWYw8WIn2Za3celi HNYC6Ibc/TVtHpIu0KxqSWLMpxkH4cjJq+7G X-Google-Smtp-Source: AK7set8Uk2pIH/HpkP+1Jihyh75Gz31f6PUT76AC8PIC1Arx/kfUyeFaJv1eNy7XJweB6ETzm0dwjw== X-Received: by 2002:a17:902:ce83:b0:199:2236:ae88 with SMTP id f3-20020a170902ce8300b001992236ae88mr2159830plg.43.1675763790092; Tue, 07 Feb 2023 01:56:30 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w8-20020a1709027b8800b0019602b2c00csm4030598pll.175.2023.02.07.01.56.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 01:56:29 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 2/8] RISC-V: KVM: Add SBI PMU extension support Date: Tue, 7 Feb 2023 01:55:23 -0800 Message-Id: <20230207095529.1787260-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SBI PMU extension allows KVM guests to configure/start/stop/query about the PMU counters in virtualized enviornment as well. In order to allow that, KVM implements the entire SBI PMU extension. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu_sbi.c | 11 +++++ arch/riscv/kvm/vcpu_sbi_pmu.c | 86 +++++++++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kvm/vcpu_sbi_pmu.c diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 5de1053..278e97c 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -25,4 +25,4 @@ kvm-y +=3D vcpu_sbi_base.o kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_hsm.o kvm-y +=3D vcpu_timer.o -kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o +kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o vcpu_sbi_pmu.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index fe2897e..15fde15 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -20,6 +20,16 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_= v01 =3D { }; #endif =20 +#ifdef CONFIG_RISCV_PMU_SBI +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu; +#else +static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu =3D { + .extid_start =3D -1UL, + .extid_end =3D -1UL, + .handler =3D NULL, +}; +#endif + static const struct kvm_vcpu_sbi_extension *sbi_ext[] =3D { &vcpu_sbi_ext_v01, &vcpu_sbi_ext_base, @@ -28,6 +38,7 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] =3D= { &vcpu_sbi_ext_rfence, &vcpu_sbi_ext_srst, &vcpu_sbi_ext_hsm, + &vcpu_sbi_ext_pmu, &vcpu_sbi_ext_experimental, &vcpu_sbi_ext_vendor, }; diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c new file mode 100644 index 0000000..38efadb --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include + +static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *= run, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret =3D 0; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + unsigned long funcid =3D cp->a6; + u64 temp; + + if (!kvpmu->init_done) { + retdata->err_val =3D SBI_ERR_NOT_SUPPORTED; + return 0; + } + + switch (funcid) { + case SBI_EXT_PMU_NUM_COUNTERS: + ret =3D kvm_riscv_vcpu_pmu_num_ctrs(vcpu, retdata); + break; + case SBI_EXT_PMU_COUNTER_GET_INFO: + ret =3D kvm_riscv_vcpu_pmu_ctr_info(vcpu, cp->a0, retdata); + break; + case SBI_EXT_PMU_COUNTER_CFG_MATCH: +#if defined(CONFIG_32BIT) + temp =3D ((uint64_t)cp->a5 << 32) | cp->a4; +#else + temp =3D cp->a4; +#endif + /* + * This can fail if perf core framework fails to create an event. + * Forward the error to userspace which is an error happened + * within the host kernel. The other option would be to convert + * to an SBI error and forward to the guest. + */ + ret =3D kvm_riscv_vcpu_pmu_ctr_cfg_match(vcpu, cp->a0, cp->a1, + cp->a2, cp->a3, temp, retdata); + break; + case SBI_EXT_PMU_COUNTER_START: +#if defined(CONFIG_32BIT) + temp =3D ((uint64_t)cp->a4 << 32) | cp->a3; +#else + temp =3D cp->a3; +#endif + ret =3D kvm_riscv_vcpu_pmu_ctr_start(vcpu, cp->a0, cp->a1, cp->a2, + temp, retdata); + break; + case SBI_EXT_PMU_COUNTER_STOP: + ret =3D kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, retdat= a); + break; + case SBI_EXT_PMU_COUNTER_FW_READ: + ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); + break; + default: + retdata->err_val =3D SBI_ERR_NOT_SUPPORTED; + } + + return ret; +} + +static unsigned long kvm_sbi_ext_pmu_probe(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + return kvpmu->init_done; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu =3D { + .extid_start =3D SBI_EXT_PMU, + .extid_end =3D SBI_EXT_PMU, + .handler =3D kvm_sbi_ext_pmu_handler, + .probe =3D kvm_sbi_ext_pmu_probe, +}; --=20 2.25.1 From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64264C636CC for ; Tue, 7 Feb 2023 09:56:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231727AbjBGJ4m (ORCPT ); Tue, 7 Feb 2023 04:56:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231672AbjBGJ4c (ORCPT ); Tue, 7 Feb 2023 04:56:32 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64E3A2E0F6 for ; Tue, 7 Feb 2023 01:56:31 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id h15so7726570plk.12 for ; Tue, 07 Feb 2023 01:56:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U3Hr20eyCmr1XHvNCY+x9mO1pacGqN3TdQd+bzW/k8M=; b=4HEe0hzldZYwed5Z8Cp2++a5PJtmn28f8PTxEBZtcLZlF8EZm170x+BYoMl26u3x5T TRKm4iw2gy0MRLw6KZq/QzFP+V9r0l3hY4NGP5/PiII1Ol1HyHOOqjSWKLRHGo8ywXFb FvjnfuaC/OjtogkNOItzaP6cyDqZG/+6ugri5f74tfAJ/jfTwl4FEbfz4rCTwAv3uwDU lvTK/D9mtthTxn+aicm5Xw4+b3rtrifXhYBMCGHpEgMbxzSCTP7nM4Pq9N7GxMgiLOyC 53mUzm4iUP5qMNNC8rqchdmoVr6Ligi6Fa3/nC6Cq6Igfk11s1aHMv32+2c9BBhyBNt/ Kcow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U3Hr20eyCmr1XHvNCY+x9mO1pacGqN3TdQd+bzW/k8M=; b=5vEBVfutrRNcufmUq2ONUaVCulSDgr9/s55OQfs8frQ3p5IoSWOR7TS1zuojFLQk/W uRCgr+Ff6lEwLIOS64xq1109lG9o0wm0yiAHWs8bSz0DmS1MAgokF99wM5iwJpTGWPNY VEAccHiDCc21XPdgsFkF+v4RhZ8yNLG5uJv4rPFHGyi8EDCMgFp3g+sc46zmVtRHqt/9 ci5QDiw9gci9RZ9s9QT4i58fIxtH3PXvAsu0c/qi5V4yCqoTAj/UpFp4m1Gywe3fmXp9 DRKbqUuBFZS8Th/rRA2yd+yGhFhDQvG8/nqjM0YV3f2SOHKjDH7c1zxIvGJkk14mV7m9 tvxg== X-Gm-Message-State: AO0yUKWUjOlkCjzsDSr4cAA6+eqs1s1ikWRHpQT7vU1Pvoz9DB45VHTI du/x4necoL27wpEQb4laXXX28wOhFjpJlBVV X-Google-Smtp-Source: AK7set8QQLOwrqLTTA0LlDm/5ideQ9RT0pkFR/RF033vPbcn2NcFmH2jpV7biDMrXUHPtAQvFVZnzw== X-Received: by 2002:a17:903:2444:b0:189:5ef4:6ae9 with SMTP id l4-20020a170903244400b001895ef46ae9mr2840251pls.45.1675763790800; Tue, 07 Feb 2023 01:56:30 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w8-20020a1709027b8800b0019602b2c00csm4030598pll.175.2023.02.07.01.56.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 01:56:30 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 3/8] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Date: Tue, 7 Feb 2023 01:55:24 -0800 Message-Id: <20230207095529.1787260-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The privilege mode filtering feature must be available in the host so that the host can inhibit the counters while the execution is in HS mode. Otherwise, the guests may have access to critical guest information. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index e79721b..6c1f073 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -79,6 +79,14 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); struct kvm_pmc *pmc; =20 + /* + * PMU functionality should be only available to guests if privilege mode + * filtering is available in the host. Otherwise, guest will always count + * events while the execution is in hypervisor mode. + */ + if (!riscv_isa_extension_available(NULL, SSCOFPMF)) + return; + ret =3D riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs); if (ret < 0 || !hpm_width || !num_hw_ctrs) return; --=20 2.25.1 From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A74BEC636D4 for ; Tue, 7 Feb 2023 09:56:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231754AbjBGJ4p (ORCPT ); Tue, 7 Feb 2023 04:56:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231716AbjBGJ4d (ORCPT ); Tue, 7 Feb 2023 04:56:33 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33ED7EFB7 for ; Tue, 7 Feb 2023 01:56:32 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id o13so14440510pjg.2 for ; Tue, 07 Feb 2023 01:56:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7bBrWzpq7M02ECVIO9gyLMkgsYGf96qlJ2xLFArrFiw=; b=RZdqDs25xResS/KYEDi/LtQFjek0M+Plb/4s7ffMGS3hx5ZzV4nC3lSe6hphmBNMYc ohPhw0Hffp1TF8CvnrZbYI/IGviC7OKfGm1gGf85RcIKMMXUZbZheC3Prsz1oF4E0ZH5 hzKTtIm4AXANG8W8gUKbQjrizR36Dv81M5mOPqk36sqOn5CjoP+bGmdiMwB5ZL0MwJXa J8JFKBnNKaZhAVAuWAVBKa+RkPkutzJL5LSsjz5MBsRfYEpnV6mIhFhV2/WDSAND/Cwl xtwXLkLb5JFo34JL15qk7gNKbbTQh9mJZi0xNfBZMYhE8ZTrDtCYQ9ltix3keZw8CjJs oSMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7bBrWzpq7M02ECVIO9gyLMkgsYGf96qlJ2xLFArrFiw=; b=biFlTwouVxyqW8qM/TvfWm6BT2IZEJI2gkCdWaIuU8M5bHhCqDs7GFWEQTcEsfzcde MvyUEaoSdONoIIe8Tx8cJCqSpg8DGS2H3bCILGp6++xCn0QOlT1H+cNX88zgP2rg2qQc Zxx4so3WQ1uucdOU6KgdFpSorD90l79jNwRPt539VidDAPrdeSdXDGeATZiGyVKlrV+k Qd+SuQQcwuBTkp7eS1HAZx5JGR0eZfRAtPWYEbNHcn1o+Orz5S4YlF/r4xI17Bxjr0Mn u7NMN7Rg9b9pBye7CI/Rcu5FKp6CPZZcMtmuRBO+qAySAaY+VUTNQPj67vSsj8EHrsD2 iJOQ== X-Gm-Message-State: AO0yUKWBVnI2F2rS0S6xd6SQGYlTrEYolg/kfNVbpF09ipWYFca6Gai+ JiNyE20otuf2sUAwu8IjNjBMSyhWI/klqsAn X-Google-Smtp-Source: AK7set+yWUejKGqKbCenoyjAhUDv3HTfD5iunwTnaUqSClL1mPUrIF1mJqLBV0a3M9F3PPfyImKdPg== X-Received: by 2002:a17:902:e88d:b0:196:433e:2384 with SMTP id w13-20020a170902e88d00b00196433e2384mr2470244plg.57.1675763791523; Tue, 07 Feb 2023 01:56:31 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w8-20020a1709027b8800b0019602b2c00csm4030598pll.175.2023.02.07.01.56.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 01:56:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 4/8] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Date: Tue, 7 Feb 2023 01:55:25 -0800 Message-Id: <20230207095529.1787260-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Any guest must not get access to any hpmcounter including cycle/instret without any checks. We achieve that by disabling all the bits except TM bit in hcounteren. However, instret and cycle access for guest user space can be enabled upon explicit request (via ONE REG) or on first trap from VU mode to maintain ABI requirement in the future. This patch doesn't support that as ONE REG interface is not settled yet. Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kvm/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 58c5489..c5d400f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -49,7 +49,8 @@ int kvm_arch_hardware_enable(void) hideleg |=3D (1UL << IRQ_VS_EXT); csr_write(CSR_HIDELEG, hideleg); =20 - csr_write(CSR_HCOUNTEREN, -1UL); + /* VS should access only the time counter directly. Everything else shoul= d trap */ + csr_write(CSR_HCOUNTEREN, 0x02); =20 csr_write(CSR_HVIP, 0); =20 --=20 2.25.1 From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0ACB0C636D4 for ; Tue, 7 Feb 2023 09:56:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231782AbjBGJ4s (ORCPT ); Tue, 7 Feb 2023 04:56:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231722AbjBGJ4e (ORCPT ); Tue, 7 Feb 2023 04:56:34 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FC9730EAF for ; Tue, 7 Feb 2023 01:56:33 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id w5so5070273plg.8 for ; Tue, 07 Feb 2023 01:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E7BAkWfqdBTUxQj0K6lnix41P2O8NAVb+CIBpMCn0RU=; b=r/pxSzwFt3rSFhL9SlF2NTmmpfBhXdNppDOyxZKm/BSjdeXPVxIbyKmsDPR/QdNRFl +ccPnEwalFo4+cgEyzKywSQX/e5rYh435mp7loDiyetbQdGkP81QSoKxkSt8+VsMjrf/ 6zCVykyzHeChRXwEBMpUzIC1QLUc/da/HpVKPASmCNzsMcTrE1t8UjHD+urL6V29SJik zLpOu2s6Va0E5UYdQcn6IIkD+DOTiKmU/gkP9oRN8Uu7rsPevaizXnZ872GK8tJ4P4kx pHGWTBTT+Yd9EemxxDYEW+F+11jG2YiWMHI7+DgQmJrejig9JxhSGlR5eYXH4FtVOjzx Db8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E7BAkWfqdBTUxQj0K6lnix41P2O8NAVb+CIBpMCn0RU=; b=SLAqqKEh2HwP/ZUbs15o+56sS3OGSIGafQU/SRIatQXbhgbqMIFJOnmzncnXNN43iQ OWfG1Dh3kRt7XaO3P4oiS9k6V3esZoUEUXcYnsAIKwHrdenbCTNXMO4VFnhXuYXdImWD 61nFq+ZEtBEYshysxxK6ynaYvdxKNd6oKV2CITpRuRmWF/MZbQRqsR//G0UbyU1BqSqu g8qIFubY6mBnoTmxQceL5IzN2luGFOpxoUYQEnEl4LNXVKrAcPmDq/Mvh484w/EMASpE gh2BjZE82SKTPir0ma9nt4vGAmLb7gr0WywTLnoR02y6DeSo+eguDYlJTDwIapTCkIzW 5paQ== X-Gm-Message-State: AO0yUKWnzjK4iq2RiWdu93zkltCF1Eh2IMpZny+sjeG30TInaRWAOhlR TJUuhIR+bj4nCTW6sJv1gQaJ+RJHJ3gxlnxc X-Google-Smtp-Source: AK7set/KiNwvCDsB2jHSC1iBRbVtSSUeEB+XSFx7WsAj9uN9aXriHH6Laqe053+EYk5hSHnzd57K0A== X-Received: by 2002:a17:902:e38a:b0:198:fd58:ee43 with SMTP id g10-20020a170902e38a00b00198fd58ee43mr1718482ple.12.1675763792316; Tue, 07 Feb 2023 01:56:32 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w8-20020a1709027b8800b0019602b2c00csm4030598pll.175.2023.02.07.01.56.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 01:56:32 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 5/8] RISC-V: KVM: Implement trap & emulate for hpmcounters Date: Tue, 7 Feb 2023 01:55:26 -0800 Message-Id: <20230207095529.1787260-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As the KVM guests only see the virtual PMU counters, all hpmcounter access should trap and KVM emulates the read access on behalf of guests. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 16 ++++++++ arch/riscv/kvm/vcpu_insn.c | 4 +- arch/riscv/kvm/vcpu_pmu.c | 59 ++++++++++++++++++++++++++- 3 files changed, 77 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 0b86a47..4bc774c 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -45,6 +45,19 @@ struct kvm_pmu { #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu_context) #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu_c= ontext)) =20 +#if defined(CONFIG_32BIT) +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ +{.base =3D CSR_CYCLEH, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_read_hp= m }, \ +{.base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_read_hpm= }, +#else +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ +{.base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_read_hpm= }, +#endif + +int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, + unsigned long *val, unsigned long new_val, + unsigned long wr_mask); + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _return *retdata); int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); @@ -68,6 +81,9 @@ void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); struct kvm_pmu { }; =20 +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ +{.base =3D 0, .count =3D 0, .func =3D NULL }, + static inline void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) {} static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {} static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {} diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 0bb5276..f689337 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -213,7 +213,9 @@ struct csr_func { unsigned long wr_mask); }; =20 -static const struct csr_func csr_funcs[] =3D { }; +static const struct csr_func csr_funcs[] =3D { + KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS +}; =20 /** * kvm_riscv_vcpu_csr_return -- Handle CSR read/write after user space diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 6c1f073..51a0237 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -17,6 +17,58 @@ =20 #define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) =20 +static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + unsigned long *out_val) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + u64 enabled, running; + + pmc =3D &kvpmu->pmc[cidx]; + if (!pmc->perf_event) + return -EINVAL; + + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &r= unning); + *out_val =3D pmc->counter_val; + + return 0; +} + +int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, + unsigned long *val, unsigned long new_val, + unsigned long wr_mask) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int cidx, ret =3D KVM_INSN_CONTINUE_NEXT_SEPC; + + if (!kvpmu || !kvpmu->init_done) { + /* + * In absence of sscofpmf in the platform, the guest OS may use + * the legacy PMU driver to read cycle/instret. In that case, + * just return 0 to avoid any illegal trap. However, any other + * hpmcounter access should result in illegal trap as they must + * be access through SBI PMU only. + */ + if (csr_num =3D=3D CSR_CYCLE || csr_num =3D=3D CSR_INSTRET) { + *val =3D 0; + return ret; + } else { + return KVM_INSN_ILLEGAL_TRAP; + } + } + + /* The counter CSR are read only. Thus, any write should result in illega= l traps */ + if (wr_mask) + return KVM_INSN_ILLEGAL_TRAP; + + cidx =3D csr_num - CSR_CYCLE; + + if (pmu_ctr_read(vcpu, cidx, val) < 0) + return KVM_INSN_ILLEGAL_TRAP; + + return ret; +} + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _return *retdata) { struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); @@ -69,7 +121,12 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata) { - /* TODO */ + int ret; + + ret =3D pmu_ctr_read(vcpu, cidx, &retdata->out_val); + if (ret =3D=3D -EINVAL) + retdata->err_val =3D SBI_ERR_INVALID_PARAM; + return 0; } =20 --=20 2.25.1 From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FD51C636CD for ; Tue, 7 Feb 2023 09:56:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231305AbjBGJ4w (ORCPT ); Tue, 7 Feb 2023 04:56:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231733AbjBGJ4h (ORCPT ); Tue, 7 Feb 2023 04:56:37 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEEA32FCF2 for ; Tue, 7 Feb 2023 01:56:33 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id v23so15123170plo.1 for ; Tue, 07 Feb 2023 01:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tz4B42PGLL8rSEQIFNlcBQdaaYEXw29m9v8KoNjY0mM=; b=LbZjQhmcW7WxY1PmkUSpeuLU4YUH+8oeud9ddraG+vJr3FVPq5ItykPltdynkGierc DowOubmo3vm41Tnt0ibJiIgBSkOv/5ZWbTplmfCAgOoqrbQxIuptqLzbKXxD2MQVNoZ9 lKl/9+SMz9m6Wd18hx/b7O0IWItJm6myLpOatXWbl/2LzgtLmQ2KBsktzYBDI1jv6RYW RmqMvJ6kCTNIWShmOCoqVA2vROlfIUvJ/LVWH495Ue32nWC5EbR1gqGxIOL2qke5CD21 zgoXguBBDB4lEQR1EmEev/h3yV9V66ANB2F3p4I4fplFhj/Z8AnjUrQ1JEO5a/pnPdlZ oLow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tz4B42PGLL8rSEQIFNlcBQdaaYEXw29m9v8KoNjY0mM=; b=xDhoAeVfHxhx+NCLuAloHYLYcmiQLEN7vM8K0j9MLIL7cHlTLPqegLrMaN/OmHCuYk 2iDxphhM63QqEJHJpIOw3+nkzyh1e+6kjqZ183B+GAL/s24Mvgall0A2L5Yt18i0pNfi OWy2pLn++/vuplW7MEQDhkRm1e2KMup4VDvO5aMBGF1/AonBJN+4lz5LaDtWvctbr/oQ WJ4o0v3KHemmc03idMCilY2+oMkXvZca5wEB1hm42urIc/a/4/bHZF2TGE0fne4T4FtF knMVDLpE4pMBB11l4R85R8YlgKfXPDQ+BEwEe9PjvHJIl2GQCnSbKqos+68DBNaQTbHG rVGg== X-Gm-Message-State: AO0yUKWWoRndCM50ict3dBIeirmsq0uOmksIgzegl+7OOwoB7y4KDlHC HF0/9oLh+19rsJni2kOOKHO1Ay0xUYifzltk X-Google-Smtp-Source: AK7set+NkYQ1upBmuIofdNvV9k3hCPb48VXDW57yBIEw3HRcDbNPDiz3lksuY4l0KYv/zI1YPtl5Gw== X-Received: by 2002:a17:902:d08b:b0:196:3056:38f4 with SMTP id v11-20020a170902d08b00b00196305638f4mr1780364plv.50.1675763793145; Tue, 07 Feb 2023 01:56:33 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w8-20020a1709027b8800b0019602b2c00csm4030598pll.175.2023.02.07.01.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 01:56:32 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 6/8] RISC-V: KVM: Implement perf support without sampling Date: Tue, 7 Feb 2023 01:55:27 -0800 Message-Id: <20230207095529.1787260-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RISC-V SBI PMU & Sscofpmf ISA extension allows supporting perf in the virtualization enviornment as well. KVM implementation relies on SBI PMU extension for the most part while trapping & emulating the CSRs read for counter access. This patch doesn't have the event sampling support yet. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 360 +++++++++++++++++++++++++++++++++++++- 1 file changed, 356 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 51a0237..cb315af 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -13,9 +13,188 @@ #include #include #include +#include #include =20 #define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) +#define get_event_type(x) (((x) & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16) +#define get_event_code(x) ((x) & SBI_PMU_EVENT_IDX_CODE_MASK) + +static enum perf_hw_id hw_event_perf_map[SBI_PMU_HW_GENERAL_MAX] =3D { + [SBI_PMU_HW_CPU_CYCLES] =3D PERF_COUNT_HW_CPU_CYCLES, + [SBI_PMU_HW_INSTRUCTIONS] =3D PERF_COUNT_HW_INSTRUCTIONS, + [SBI_PMU_HW_CACHE_REFERENCES] =3D PERF_COUNT_HW_CACHE_REFERENCES, + [SBI_PMU_HW_CACHE_MISSES] =3D PERF_COUNT_HW_CACHE_MISSES, + [SBI_PMU_HW_BRANCH_INSTRUCTIONS] =3D PERF_COUNT_HW_BRANCH_INSTRUCTIONS, + [SBI_PMU_HW_BRANCH_MISSES] =3D PERF_COUNT_HW_BRANCH_MISSES, + [SBI_PMU_HW_BUS_CYCLES] =3D PERF_COUNT_HW_BUS_CYCLES, + [SBI_PMU_HW_STALLED_CYCLES_FRONTEND] =3D PERF_COUNT_HW_STALLED_CYCLES_FRO= NTEND, + [SBI_PMU_HW_STALLED_CYCLES_BACKEND] =3D PERF_COUNT_HW_STALLED_CYCLES_BACK= END, + [SBI_PMU_HW_REF_CPU_CYCLES] =3D PERF_COUNT_HW_REF_CPU_CYCLES, +}; + +static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc) +{ + u64 counter_val_mask =3D GENMASK(pmc->cinfo.width, 0); + u64 sample_period; + + if (!pmc->counter_val) + sample_period =3D counter_val_mask + 1; + else + sample_period =3D (-pmc->counter_val) & counter_val_mask; + + return sample_period; +} + +static u32 kvm_pmu_get_perf_event_type(unsigned long eidx) +{ + enum sbi_pmu_event_type etype =3D get_event_type(eidx); + u32 type =3D PERF_TYPE_MAX; + + switch (etype) { + case SBI_PMU_EVENT_TYPE_HW: + type =3D PERF_TYPE_HARDWARE; + break; + case SBI_PMU_EVENT_TYPE_CACHE: + type =3D PERF_TYPE_HW_CACHE; + break; + case SBI_PMU_EVENT_TYPE_RAW: + case SBI_PMU_EVENT_TYPE_FW: + type =3D PERF_TYPE_RAW; + break; + default: + break; + } + + return type; +} + +static bool kvm_pmu_is_fw_event(unsigned long eidx) +{ + return get_event_type(eidx) =3D=3D SBI_PMU_EVENT_TYPE_FW; +} + +static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc) +{ + if (pmc->perf_event) { + perf_event_disable(pmc->perf_event); + perf_event_release_kernel(pmc->perf_event); + pmc->perf_event =3D NULL; + } +} + +static u64 kvm_pmu_get_perf_event_hw_config(u32 sbi_event_code) +{ + return hw_event_perf_map[sbi_event_code]; +} + +static u64 kvm_pmu_get_perf_event_cache_config(u32 sbi_event_code) +{ + u64 config =3D U64_MAX; + unsigned int cache_type, cache_op, cache_result; + + /* All the cache event masks lie within 0xFF. No separate masking is nece= ssary */ + cache_type =3D (sbi_event_code & SBI_PMU_EVENT_CACHE_ID_CODE_MASK) >> + SBI_PMU_EVENT_CACHE_ID_SHIFT; + cache_op =3D (sbi_event_code & SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK) >> + SBI_PMU_EVENT_CACHE_OP_SHIFT; + cache_result =3D sbi_event_code & SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK; + + if (cache_type >=3D PERF_COUNT_HW_CACHE_MAX || + cache_op >=3D PERF_COUNT_HW_CACHE_OP_MAX || + cache_result >=3D PERF_COUNT_HW_CACHE_RESULT_MAX) + return config; + + config =3D cache_type | (cache_op << 8) | (cache_result << 16); + + return config; +} + +static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_= data) +{ + enum sbi_pmu_event_type etype =3D get_event_type(eidx); + u32 ecode =3D get_event_code(eidx); + u64 config =3D U64_MAX; + + switch (etype) { + case SBI_PMU_EVENT_TYPE_HW: + if (ecode < SBI_PMU_HW_GENERAL_MAX) + config =3D kvm_pmu_get_perf_event_hw_config(ecode); + break; + case SBI_PMU_EVENT_TYPE_CACHE: + config =3D kvm_pmu_get_perf_event_cache_config(ecode); + break; + case SBI_PMU_EVENT_TYPE_RAW: + config =3D evt_data & RISCV_PMU_RAW_EVENT_MASK; + break; + case SBI_PMU_EVENT_TYPE_FW: + if (ecode < SBI_PMU_FW_MAX) + config =3D (1ULL << 63) | ecode; + break; + default: + break; + } + + return config; +} + +static int kvm_pmu_get_fixed_pmc_index(unsigned long eidx) +{ + u32 etype =3D kvm_pmu_get_perf_event_type(eidx); + u32 ecode =3D get_event_code(eidx); + + if (etype !=3D SBI_PMU_EVENT_TYPE_HW) + return -EINVAL; + + if (ecode =3D=3D SBI_PMU_HW_CPU_CYCLES) + return 0; + else if (ecode =3D=3D SBI_PMU_HW_INSTRUCTIONS) + return 2; + else + return -EINVAL; +} + +static int kvm_pmu_get_programmable_pmc_index(struct kvm_pmu *kvpmu, unsig= ned long eidx, + unsigned long cbase, unsigned long cmask) +{ + int ctr_idx =3D -1; + int i, pmc_idx; + int min, max; + + if (kvm_pmu_is_fw_event(eidx)) { + /* Firmware counters are mapped 1:1 starting from num_hw_ctrs for simpli= city */ + min =3D kvpmu->num_hw_ctrs; + max =3D min + kvpmu->num_fw_ctrs; + } else { + /* First 3 counters are reserved for fixed counters */ + min =3D 3; + max =3D kvpmu->num_hw_ctrs; + } + + for_each_set_bit(i, &cmask, BITS_PER_LONG) { + pmc_idx =3D i + cbase; + if ((pmc_idx >=3D min && pmc_idx < max) && + !test_bit(pmc_idx, kvpmu->pmc_in_use)) { + ctr_idx =3D pmc_idx; + break; + } + } + + return ctr_idx; +} + +static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsigned long eidx, + unsigned long cbase, unsigned long cmask) +{ + int ret; + + /* Fixed counters need to be have fixed mapping as they have different wi= dth */ + ret =3D kvm_pmu_get_fixed_pmc_index(eidx); + if (ret >=3D 0) + return ret; + + return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask); +} =20 static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, unsigned long *out_val) @@ -34,6 +213,16 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned= long cidx, return 0; } =20 +static int kvm_pmu_validate_counter_mask(struct kvm_pmu *kvpmu, unsigned l= ong ctr_base, + unsigned long ctr_mask) +{ + /* Make sure the we have a valid counter mask requested from the caller */ + if (!ctr_mask || (ctr_base + __fls(ctr_mask) >=3D kvm_pmu_num_counters(kv= pmu))) + return -EINVAL; + + return 0; +} + int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, unsigned long new_val, unsigned long wr_mask) @@ -97,7 +286,39 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu,= unsigned long ctr_base, unsigned long ctr_mask, unsigned long flags, u64 ival, struct kvm_vcpu_sbi_return *retdata) { - /* TODO */ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int i, pmc_index, sbiret =3D 0; + struct kvm_pmc *pmc; + + if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + /* Start the counters that have been configured and requested by the gues= t */ + for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { + pmc_index =3D i + ctr_base; + if (!test_bit(pmc_index, kvpmu->pmc_in_use)) + continue; + pmc =3D &kvpmu->pmc[pmc_index]; + if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) + pmc->counter_val =3D ival; + if (pmc->perf_event) { + if (unlikely(pmc->started)) { + sbiret =3D SBI_ERR_ALREADY_STARTED; + continue; + } + perf_event_period(pmc->perf_event, kvm_pmu_get_sample_period(pmc)); + perf_event_enable(pmc->perf_event); + pmc->started =3D true; + } else { + sbiret =3D SBI_ERR_INVALID_PARAM; + } + } + +out: + retdata->err_val =3D sbiret; + return 0; } =20 @@ -105,7 +326,46 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, unsigned long ctr_mask, unsigned long flags, struct kvm_vcpu_sbi_return *retdata) { - /* TODO */ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int i, pmc_index, sbiret =3D 0; + u64 enabled, running; + struct kvm_pmc *pmc; + + if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + /* Stop the counters that have been configured and requested by the guest= */ + for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { + pmc_index =3D i + ctr_base; + if (!test_bit(pmc_index, kvpmu->pmc_in_use)) + continue; + pmc =3D &kvpmu->pmc[pmc_index]; + if (pmc->perf_event) { + if (pmc->started) { + /* Stop counting the counter */ + perf_event_disable(pmc->perf_event); + pmc->started =3D false; + } else { + sbiret =3D SBI_ERR_ALREADY_STOPPED; + } + + if (flags & SBI_PMU_STOP_FLAG_RESET) { + /* Relase the counter if this is a reset request */ + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, + &enabled, &running); + kvm_pmu_release_perf_event(pmc); + clear_bit(pmc_index, kvpmu->pmc_in_use); + } + } else { + sbiret =3D SBI_ERR_INVALID_PARAM; + } + } + +out: + retdata->err_val =3D sbiret; + return 0; } =20 @@ -114,7 +374,87 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *= vcpu, unsigned long ctr_ba unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata) { - /* TODO */ + int ctr_idx, sbiret =3D 0; + u64 config; + u32 etype =3D kvm_pmu_get_perf_event_type(eidx); + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct perf_event *event; + struct kvm_pmc *pmc; + struct perf_event_attr attr =3D { + .type =3D etype, + .size =3D sizeof(struct perf_event_attr), + .pinned =3D true, + /* + * It should never reach here if the platform doesn't support the sscofp= mf + * extension as mode filtering won't work without it. + */ + .exclude_host =3D true, + .exclude_hv =3D true, + .exclude_user =3D !!(flags & SBI_PMU_CFG_FLAG_SET_UINH), + .exclude_kernel =3D !!(flags & SBI_PMU_CFG_FLAG_SET_SINH), + .config1 =3D RISCV_PMU_CONFIG1_GUEST_EVENTS, + }; + + if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + if (kvm_pmu_is_fw_event(eidx)) { + sbiret =3D SBI_ERR_NOT_SUPPORTED; + goto out; + } + + /* + * SKIP_MATCH flag indicates the caller is aware of the assigned counter + * for this event. Just do a sanity check if it already marked used. + */ + if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) { + if (!test_bit(ctr_base + __ffs(ctr_mask), kvpmu->pmc_in_use)) { + sbiret =3D SBI_ERR_FAILURE; + goto out; + } + ctr_idx =3D ctr_base + __ffs(ctr_mask); + } else { + ctr_idx =3D pmu_get_pmc_index(kvpmu, eidx, ctr_base, ctr_mask); + if (ctr_idx < 0) { + sbiret =3D SBI_ERR_NOT_SUPPORTED; + goto out; + } + } + + pmc =3D &kvpmu->pmc[ctr_idx]; + kvm_pmu_release_perf_event(pmc); + pmc->idx =3D ctr_idx; + + config =3D kvm_pmu_get_perf_event_config(eidx, evtdata); + attr.config =3D config; + if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) { + //TODO: Do we really want to clear the value in hardware counter + pmc->counter_val =3D 0; + } + + /* + * Set the default sample_period for now. The guest specified value + * will be updated in the start call. + */ + attr.sample_period =3D kvm_pmu_get_sample_period(pmc); + + event =3D perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc); + if (IS_ERR(event)) { + pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); + return PTR_ERR(event); + } + + set_bit(ctr_idx, kvpmu->pmc_in_use); + pmc->perf_event =3D event; + if (flags & SBI_PMU_CFG_FLAG_AUTO_START) + perf_event_enable(pmc->perf_event); + + retdata->out_val =3D ctr_idx; +out: + retdata->err_val =3D sbiret; + return 0; } =20 @@ -194,7 +534,19 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) =20 void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) { - /* TODO */ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + int i; + + if (!kvpmu) + return; + + for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_MAX_COUNTERS) { + pmc =3D &kvpmu->pmc[i]; + pmc->counter_val =3D 0; + kvm_pmu_release_perf_event(pmc); + } + bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); } =20 void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) --=20 2.25.1 From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A699C636CD for ; Tue, 7 Feb 2023 09:56:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231792AbjBGJ4z (ORCPT ); Tue, 7 Feb 2023 04:56:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231740AbjBGJ4h (ORCPT ); Tue, 7 Feb 2023 04:56:37 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27EF8366B7 for ; Tue, 7 Feb 2023 01:56:34 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id f16-20020a17090a9b1000b0023058bbd7b2so13708413pjp.0 for ; Tue, 07 Feb 2023 01:56:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9B2v1xXVO9urztyguosfvMU7qfopljP/6lHOqoqX10A=; b=seBy+Gi6HYMwD2jCWspyZY3sHQOWJESwLrvLhtOkwApLXLsRbKE65/plBlJUm5Ly5f hLkB3VxyccXJMAkFZlY244x4yV8N0Sg9ctX+1ejJVQzCraavh/Z2OmkbnCZOi3znFqw7 67RGg0t881VcAD1kM+H16v7/RCKwOr1xg0+5C5rLAWFFcSQ2VQjkYO3jAPV98KdbAiov xxSQEmKWFlpgtG23FkuMYCciCI0RFu/RxzswlP3l4rWWqfJ/s9NoA94bF/4x0mymY8Ji v0l3EKl7clDW6okJ3hswkmotqVO3xHK41CtCTTa5yiFJGZBeVXxiVpX+BxoZU8fZFZt/ vB7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9B2v1xXVO9urztyguosfvMU7qfopljP/6lHOqoqX10A=; b=bWsXrGpAU64cFtA6V57/mAU21TuNLQqwWMjWRZVHZ3cn5ms+Jqi2CU8JJ6huA5zuD0 V7nAl229B4EVtDAqw9Tjd94VEbLvUy3Poe8+2wDccH6pm19Eewap+tzPBlW5SV36gBqS gwSWg2ZkZBTgHRyAIyLMR8vAB1oJKtYsdOBIYmoaZw+zB/BLGNAGdiMgc6O8E97VVgjX w83hKmckoS4AoVpk7XBUfAeT39FnOQbsDcJADiecA7bmpokOIWLZ28aR7PL/TBUGuOqA KvMbdDKM80GSaPM6vxbB/vvIBtlJw+mCdp8VWszl5wDBafurU+3j0YMSX/Cl9/ObkTtj cTTA== X-Gm-Message-State: AO0yUKVeOY8J2x7S0JHOipCZoTqS4vd3zDwHbneKXfIgV9EwmHwcr1Nj f1Fc9EZb81WfXeJmz2PxQypZl1IBYhftyktE X-Google-Smtp-Source: AK7set/RMeeawMTATZYPzmVguxxUAU4V2myuozCZT5WacgPZlWjWwuGueU6FlAMMgXrSD8DXCMRhng== X-Received: by 2002:a17:902:c40e:b0:196:8a80:4d91 with SMTP id k14-20020a170902c40e00b001968a804d91mr2626667plk.35.1675763794038; Tue, 07 Feb 2023 01:56:34 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w8-20020a1709027b8800b0019602b2c00csm4030598pll.175.2023.02.07.01.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Feb 2023 01:56:33 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 7/8] RISC-V: KVM: Support firmware events Date: Tue, 7 Feb 2023 01:55:28 -0800 Message-Id: <20230207095529.1787260-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SBI PMU extension defines a set of firmware events which can provide useful information to guests about the number of SBI calls. As hypervisor implements the SBI PMU extension, these firmware events correspond to ecall invocations between VS->HS mode. All other firmware events will always report zero if monitored as KVM doesn't implement them. This patch adds all the infrastructure required to support firmware events. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 17 ++++ arch/riscv/kvm/vcpu_pmu.c | 141 ++++++++++++++++++++------ 2 files changed, 125 insertions(+), 33 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 4bc774c..203ee72 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -19,6 +19,14 @@ #define RISCV_KVM_MAX_COUNTERS (RISCV_KVM_MAX_HW_CTRS + RISCV_KVM_MAX_FW_C= TRS) static_assert(RISCV_KVM_MAX_COUNTERS <=3D 64); =20 +struct kvm_fw_event { + /* Current value of the event */ + unsigned long value; + + /* Event monitoring status */ + bool started; +}; + /* Per virtual pmu counter data */ struct kvm_pmc { u8 idx; @@ -27,11 +35,14 @@ struct kvm_pmc { union sbi_pmu_ctr_info cinfo; /* Event monitoring status */ bool started; + /* Monitoring event ID */ + unsigned long event_idx; }; =20 /* PMU data structure per vcpu */ struct kvm_pmu { struct kvm_pmc pmc[RISCV_KVM_MAX_COUNTERS]; + struct kvm_fw_event fw_event[RISCV_KVM_MAX_FW_CTRS]; /* Number of the virtual firmware counters available */ int num_fw_ctrs; /* Number of the virtual hardware counters available */ @@ -54,6 +65,7 @@ struct kvm_pmu { {.base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_read_hpm= }, #endif =20 +int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid); int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, unsigned long new_val, unsigned long wr_mask); @@ -85,6 +97,11 @@ struct kvm_pmu { {.base =3D 0, .count =3D 0, .func =3D NULL }, =20 static inline void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) {} +static inline int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsign= ed long fid) +{ + return 0; +} + static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {} static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {} #endif /* CONFIG_RISCV_PMU_SBI */ diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index cb315af..257f9a2 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -202,12 +202,18 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsign= ed long cidx, struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); struct kvm_pmc *pmc; u64 enabled, running; + int fevent_code; =20 pmc =3D &kvpmu->pmc[cidx]; - if (!pmc->perf_event) - return -EINVAL; =20 - pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &r= unning); + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + fevent_code =3D get_event_code(pmc->event_idx); + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; + } else if (pmc->perf_event) { + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &= running); + } else { + return -EINVAL; + } *out_val =3D pmc->counter_val; =20 return 0; @@ -223,6 +229,52 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pm= u *kvpmu, unsigned long ct return 0; } =20 +static int kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_even= t_attr *attr, + unsigned long flags, unsigned long eidx, unsigned long evtdata) +{ + struct perf_event *event; + + kvm_pmu_release_perf_event(pmc); + attr->config =3D kvm_pmu_get_perf_event_config(eidx, evtdata); + if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) { + //TODO: Do we really want to clear the value in hardware counter + pmc->counter_val =3D 0; + } + + /* + * Set the default sample_period for now. The guest specified value + * will be updated in the start call. + */ + attr->sample_period =3D kvm_pmu_get_sample_period(pmc); + + event =3D perf_event_create_kernel_counter(attr, -1, current, NULL, pmc); + if (IS_ERR(event)) { + pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); + return PTR_ERR(event); + } + + pmc->perf_event =3D event; + if (flags & SBI_PMU_CFG_FLAG_AUTO_START) + perf_event_enable(pmc->perf_event); + + return 0; +} + +int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_fw_event *fevent; + + if (!kvpmu || fid >=3D SBI_PMU_FW_MAX) + return -EINVAL; + + fevent =3D &kvpmu->fw_event[fid]; + if (fevent->started) + fevent->value++; + + return 0; +} + int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, unsigned long new_val, unsigned long wr_mask) @@ -289,6 +341,7 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu,= unsigned long ctr_base, struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); int i, pmc_index, sbiret =3D 0; struct kvm_pmc *pmc; + int fevent_code; =20 if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret =3D SBI_ERR_INVALID_PARAM; @@ -303,7 +356,22 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu= , unsigned long ctr_base, pmc =3D &kvpmu->pmc[pmc_index]; if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) pmc->counter_val =3D ival; - if (pmc->perf_event) { + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + fevent_code =3D get_event_code(pmc->event_idx); + if (fevent_code >=3D SBI_PMU_FW_MAX) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + /* Check if the counter was already started for some reason */ + if (kvpmu->fw_event[fevent_code].started) { + sbiret =3D SBI_ERR_ALREADY_STARTED; + continue; + } + + kvpmu->fw_event[fevent_code].started =3D true; + kvpmu->fw_event[fevent_code].value =3D pmc->counter_val; + } else if (pmc->perf_event) { if (unlikely(pmc->started)) { sbiret =3D SBI_ERR_ALREADY_STARTED; continue; @@ -330,6 +398,7 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, = unsigned long ctr_base, int i, pmc_index, sbiret =3D 0; u64 enabled, running; struct kvm_pmc *pmc; + int fevent_code; =20 if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret =3D SBI_ERR_INVALID_PARAM; @@ -342,7 +411,18 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; pmc =3D &kvpmu->pmc[pmc_index]; - if (pmc->perf_event) { + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + fevent_code =3D get_event_code(pmc->event_idx); + if (fevent_code >=3D SBI_PMU_FW_MAX) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + if (!kvpmu->fw_event[fevent_code].started) + sbiret =3D SBI_ERR_ALREADY_STOPPED; + + kvpmu->fw_event[fevent_code].started =3D false; + } else if (pmc->perf_event) { if (pmc->started) { /* Stop counting the counter */ perf_event_disable(pmc->perf_event); @@ -356,11 +436,14 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu= , unsigned long ctr_base, pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &running); kvm_pmu_release_perf_event(pmc); - clear_bit(pmc_index, kvpmu->pmc_in_use); } } else { sbiret =3D SBI_ERR_INVALID_PARAM; } + if (flags & SBI_PMU_STOP_FLAG_RESET) { + pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; + clear_bit(pmc_index, kvpmu->pmc_in_use); + } } =20 out: @@ -374,12 +457,12 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu = *vcpu, unsigned long ctr_ba unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata) { - int ctr_idx, sbiret =3D 0; - u64 config; + int ctr_idx, ret, sbiret =3D 0; + bool is_fevent; + unsigned long event_code; u32 etype =3D kvm_pmu_get_perf_event_type(eidx); struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); - struct perf_event *event; - struct kvm_pmc *pmc; + struct kvm_pmc *pmc =3D NULL; struct perf_event_attr attr =3D { .type =3D etype, .size =3D sizeof(struct perf_event_attr), @@ -400,7 +483,9 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba goto out; } =20 - if (kvm_pmu_is_fw_event(eidx)) { + event_code =3D get_event_code(eidx); + is_fevent =3D kvm_pmu_is_fw_event(eidx); + if (is_fevent && event_code >=3D SBI_PMU_FW_MAX) { sbiret =3D SBI_ERR_NOT_SUPPORTED; goto out; } @@ -424,33 +509,19 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu = *vcpu, unsigned long ctr_ba } =20 pmc =3D &kvpmu->pmc[ctr_idx]; - kvm_pmu_release_perf_event(pmc); pmc->idx =3D ctr_idx; =20 - config =3D kvm_pmu_get_perf_event_config(eidx, evtdata); - attr.config =3D config; - if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) { - //TODO: Do we really want to clear the value in hardware counter - pmc->counter_val =3D 0; - } - - /* - * Set the default sample_period for now. The guest specified value - * will be updated in the start call. - */ - attr.sample_period =3D kvm_pmu_get_sample_period(pmc); - - event =3D perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc); - if (IS_ERR(event)) { - pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); - return PTR_ERR(event); + if (is_fevent) { + if (flags & SBI_PMU_CFG_FLAG_AUTO_START) + kvpmu->fw_event[event_code].started =3D true; + } else { + ret =3D kvm_pmu_create_perf_event(pmc, &attr, flags, eidx, evtdata); + if (ret) + return ret; } =20 set_bit(ctr_idx, kvpmu->pmc_in_use); - pmc->perf_event =3D event; - if (flags & SBI_PMU_CFG_FLAG_AUTO_START) - perf_event_enable(pmc->perf_event); - + pmc->event_idx =3D eidx; retdata->out_val =3D ctr_idx; out: retdata->err_val =3D sbiret; @@ -492,6 +563,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) */ kvpmu->num_hw_ctrs =3D num_hw_ctrs + 1; kvpmu->num_fw_ctrs =3D SBI_PMU_FW_MAX; + memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); =20 if (kvpmu->num_hw_ctrs > RISCV_KVM_MAX_HW_CTRS) { pr_warn("Limiting the hardware counters to 32 as specified by the ISA"); @@ -509,6 +581,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) continue; pmc =3D &kvpmu->pmc[i]; pmc->idx =3D i; + pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; if (i < kvpmu->num_hw_ctrs) { pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_HW; if (i < 3) @@ -545,8 +618,10 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) pmc =3D &kvpmu->pmc[i]; pmc->counter_val =3D 0; kvm_pmu_release_perf_event(pmc); + pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; } bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); + memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); } =20 void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) --=20 2.25.1 From nobody Fri Sep 12 22:08:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78791C636CC for ; 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Tue, 07 Feb 2023 01:56:34 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Atish Patra , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v6 8/8] RISC-V: KVM: Increment firmware pmu events Date: Tue, 7 Feb 2023 01:55:29 -0800 Message-Id: <20230207095529.1787260-9-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207095529.1787260-1-atishp@rivosinc.com> References: <20230207095529.1787260-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" KVM supports firmware events now. Invoke the firmware event increment function from appropriate places. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/tlb.c | 4 ++++ arch/riscv/kvm/vcpu_sbi_replace.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 309d79b..b797f7c 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -181,6 +181,7 @@ void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu) =20 void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu) { + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_RCVD); local_flush_icache_all(); } =20 @@ -264,15 +265,18 @@ void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu) d.addr, d.size, d.order); break; case KVM_RISCV_HFENCE_VVMA_ASID_GVA: + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); kvm_riscv_local_hfence_vvma_asid_gva( READ_ONCE(v->vmid), d.asid, d.addr, d.size, d.order); break; case KVM_RISCV_HFENCE_VVMA_ASID_ALL: + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); kvm_riscv_local_hfence_vvma_asid_all( READ_ONCE(v->vmid), d.asid); break; case KVM_RISCV_HFENCE_VVMA_GVA: + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD); kvm_riscv_local_hfence_vvma_gva( READ_ONCE(v->vmid), d.addr, d.size, d.order); diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_re= place.c index 38fa4c0..7c4d5d3 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, @@ -24,6 +25,7 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, return 0; } =20 + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_SET_TIMER); #if __riscv_xlen =3D=3D 32 next_cycle =3D ((u64)cp->a1 << 32) | (u64)cp->a0; #else @@ -55,6 +57,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, return 0; } =20 + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_IPI_SENT); kvm_for_each_vcpu(i, tmp, vcpu->kvm) { if (hbase !=3D -1UL) { if (tmp->vcpu_id < hbase) @@ -65,6 +68,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, ret =3D kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT); if (ret < 0) break; + kvm_riscv_vcpu_pmu_incr_fw(tmp, SBI_PMU_FW_IPI_RCVD); } =20 return ret; @@ -87,6 +91,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vc= pu, struct kvm_run *run switch (funcid) { case SBI_EXT_RFENCE_REMOTE_FENCE_I: kvm_riscv_fence_i(vcpu->kvm, hbase, hmask); + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_SENT); break; case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: if (cp->a2 =3D=3D 0 && cp->a3 =3D=3D 0) @@ -94,6 +99,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vc= pu, struct kvm_run *run else kvm_riscv_hfence_vvma_gva(vcpu->kvm, hbase, hmask, cp->a2, cp->a3, PAGE_SHIFT); + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_SENT); break; case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: if (cp->a2 =3D=3D 0 && cp->a3 =3D=3D 0) @@ -104,6 +110,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *= vcpu, struct kvm_run *run hbase, hmask, cp->a2, cp->a3, PAGE_SHIFT, cp->a4); + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_SENT); break; case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: --=20 2.25.1