From nobody Sat Sep 13 01:54:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1021C636D3 for ; Tue, 7 Feb 2023 02:35:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230048AbjBGCfm (ORCPT ); Mon, 6 Feb 2023 21:35:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229608AbjBGCf1 (ORCPT ); Mon, 6 Feb 2023 21:35:27 -0500 Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4500034C1B; Mon, 6 Feb 2023 18:35:23 -0800 (PST) Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 07 Feb 2023 11:35:21 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 31FC12020780; Tue, 7 Feb 2023 11:35:21 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 7 Feb 2023 11:35:31 +0900 Received: from plum.e01.socionext.com (unknown [10.212.243.119]) by kinkan2.css.socionext.com (Postfix) with ESMTP id 87232A8556; Tue, 7 Feb 2023 11:35:20 +0900 (JST) From: Kunihiko Hayashi To: soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Rob Herring , Krzysztof Kozlowski , Masami Hiramatsu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 5/8] arm64: dts: uniphier: Align node names for SoC-dependent controller and PHYs with bindings Date: Tue, 7 Feb 2023 11:35:11 +0900 Message-Id: <20230207023514.29783-6-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230207023514.29783-1-hayashi.kunihiko@socionext.com> References: <20230207023514.29783-1-hayashi.kunihiko@socionext.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The node names for SoC-dependent controllers and PHYs should be generic ones according to the DT schemas. Signed-off-by: Kunihiko Hayashi --- .../boot/dts/socionext/uniphier-ld11.dtsi | 32 +++++++-------- .../boot/dts/socionext/uniphier-ld20.dtsi | 40 +++++++++---------- .../boot/dts/socionext/uniphier-pxs3.dtsi | 40 +++++++++---------- 3 files changed, 56 insertions(+), 56 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/= boot/dts/socionext/uniphier-ld11.dtsi index 1c76b4375b2e..148d9092572a 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -313,12 +313,12 @@ evea_hp: endpoint { }; }; =20 - adamv@57920000 { + syscon@57920000 { compatible =3D "socionext,uniphier-ld11-adamv", "simple-mfd", "syscon"; reg =3D <0x57920000 0x1000>; =20 - adamv_rst: reset { + adamv_rst: reset-controller { compatible =3D "socionext,uniphier-ld11-adamv-reset"; #reset-cells =3D <1>; }; @@ -417,28 +417,28 @@ smpctrl@59801000 { reg =3D <0x59801000 0x400>; }; =20 - sdctrl@59810000 { + syscon@59810000 { compatible =3D "socionext,uniphier-ld11-sdctrl", "simple-mfd", "syscon"; reg =3D <0x59810000 0x400>; =20 - sd_rst: reset { + sd_rst: reset-controller { compatible =3D "socionext,uniphier-ld11-sd-reset"; #reset-cells =3D <1>; }; }; =20 - perictrl@59820000 { + syscon@59820000 { compatible =3D "socionext,uniphier-ld11-perictrl", "simple-mfd", "syscon"; reg =3D <0x59820000 0x200>; =20 - peri_clk: clock { + peri_clk: clock-controller { compatible =3D "socionext,uniphier-ld11-peri-clock"; #clock-cells =3D <1>; }; =20 - peri_rst: reset { + peri_rst: reset-controller { compatible =3D "socionext,uniphier-ld11-peri-reset"; #reset-cells =3D <1>; }; @@ -511,24 +511,24 @@ usb2: usb@5a820100 { has-transaction-translator; }; =20 - mioctrl@5b3e0000 { + syscon@5b3e0000 { compatible =3D "socionext,uniphier-ld11-mioctrl", "simple-mfd", "syscon"; reg =3D <0x5b3e0000 0x800>; =20 - mio_clk: clock { + mio_clk: clock-controller { compatible =3D "socionext,uniphier-ld11-mio-clock"; #clock-cells =3D <1>; }; =20 - mio_rst: reset { + mio_rst: reset-controller { compatible =3D "socionext,uniphier-ld11-mio-reset"; #reset-cells =3D <1>; resets =3D <&sys_rst 7>; }; }; =20 - soc_glue: soc-glue@5f800000 { + soc_glue: syscon@5f800000 { compatible =3D "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; reg =3D <0x5f800000 0x2000>; @@ -537,7 +537,7 @@ pinctrl: pinctrl { compatible =3D "socionext,uniphier-ld11-pinctrl"; }; =20 - usb-controller { + usb-hub { compatible =3D "socionext,uniphier-ld11-usb2-phy"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -559,7 +559,7 @@ usb_phy2: phy@2 { }; }; =20 - soc-glue@5f900000 { + syscon@5f900000 { compatible =3D "socionext,uniphier-ld11-soc-glue-debug", "simple-mfd"; #address-cells =3D <1>; @@ -601,17 +601,17 @@ gic: interrupt-controller@5fe00000 { interrupts =3D ; }; =20 - sysctrl@61840000 { + syscon@61840000 { compatible =3D "socionext,uniphier-ld11-sysctrl", "simple-mfd", "syscon"; reg =3D <0x61840000 0x10000>; =20 - sys_clk: clock { + sys_clk: clock-controller { compatible =3D "socionext,uniphier-ld11-clock"; #clock-cells =3D <1>; }; =20 - sys_rst: reset { + sys_rst: reset-controller { compatible =3D "socionext,uniphier-ld11-reset"; #reset-cells =3D <1>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/= boot/dts/socionext/uniphier-ld20.dtsi index 9308458f9611..c83265c9b520 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -444,12 +444,12 @@ evea_hp: endpoint { }; }; =20 - adamv@57920000 { + syscon@57920000 { compatible =3D "socionext,uniphier-ld20-adamv", "simple-mfd", "syscon"; reg =3D <0x57920000 0x1000>; =20 - adamv_rst: reset { + adamv_rst: reset-controller { compatible =3D "socionext,uniphier-ld20-adamv-reset"; #reset-cells =3D <1>; }; @@ -548,33 +548,33 @@ smpctrl@59801000 { reg =3D <0x59801000 0x400>; }; =20 - sdctrl@59810000 { + syscon@59810000 { compatible =3D "socionext,uniphier-ld20-sdctrl", "simple-mfd", "syscon"; reg =3D <0x59810000 0x400>; =20 - sd_clk: clock { + sd_clk: clock-controller { compatible =3D "socionext,uniphier-ld20-sd-clock"; #clock-cells =3D <1>; }; =20 - sd_rst: reset { + sd_rst: reset-controller { compatible =3D "socionext,uniphier-ld20-sd-reset"; #reset-cells =3D <1>; }; }; =20 - perictrl@59820000 { + syscon@59820000 { compatible =3D "socionext,uniphier-ld20-perictrl", "simple-mfd", "syscon"; reg =3D <0x59820000 0x200>; =20 - peri_clk: clock { + peri_clk: clock-controller { compatible =3D "socionext,uniphier-ld20-peri-clock"; #clock-cells =3D <1>; }; =20 - peri_rst: reset { + peri_rst: reset-controller { compatible =3D "socionext,uniphier-ld20-peri-reset"; #reset-cells =3D <1>; }; @@ -613,7 +613,7 @@ sd: mmc@5a400000 { cap-sd-highspeed; }; =20 - soc_glue: soc-glue@5f800000 { + soc_glue: syscon@5f800000 { compatible =3D "socionext,uniphier-ld20-soc-glue", "simple-mfd", "syscon"; reg =3D <0x5f800000 0x2000>; @@ -623,7 +623,7 @@ pinctrl: pinctrl { }; }; =20 - soc-glue@5f900000 { + syscon@5f900000 { compatible =3D "socionext,uniphier-ld20-soc-glue-debug", "simple-mfd"; #address-cells =3D <1>; @@ -709,17 +709,17 @@ gic: interrupt-controller@5fe00000 { interrupts =3D ; }; =20 - sysctrl@61840000 { + syscon@61840000 { compatible =3D "socionext,uniphier-ld20-sysctrl", "simple-mfd", "syscon"; reg =3D <0x61840000 0x10000>; =20 - sys_clk: clock { + sys_clk: clock-controller { compatible =3D "socionext,uniphier-ld20-clock"; #clock-cells =3D <1>; }; =20 - sys_rst: reset { + sys_rst: reset-controller { compatible =3D "socionext,uniphier-ld20-reset"; #reset-cells =3D <1>; }; @@ -782,7 +782,7 @@ usb-controller@65b00000 { #size-cells =3D <1>; ranges =3D <0 0x65b00000 0x400>; =20 - usb_rst: reset@0 { + usb_rst: reset-controller@0 { compatible =3D "socionext,uniphier-ld20-usb3-reset"; reg =3D <0x0 0x4>; #reset-cells =3D <1>; @@ -828,7 +828,7 @@ usb_vbus3: regulator@130 { resets =3D <&sys_rst 14>; }; =20 - usb_hsphy0: hs-phy@200 { + usb_hsphy0: phy@200 { compatible =3D "socionext,uniphier-ld20-usb3-hsphy"; reg =3D <0x200 0x10>; #phy-cells =3D <0>; @@ -842,7 +842,7 @@ usb_hsphy0: hs-phy@200 { <&usb_hs_i0>; }; =20 - usb_hsphy1: hs-phy@210 { + usb_hsphy1: phy@210 { compatible =3D "socionext,uniphier-ld20-usb3-hsphy"; reg =3D <0x210 0x10>; #phy-cells =3D <0>; @@ -856,7 +856,7 @@ usb_hsphy1: hs-phy@210 { <&usb_hs_i0>; }; =20 - usb_hsphy2: hs-phy@220 { + usb_hsphy2: phy@220 { compatible =3D "socionext,uniphier-ld20-usb3-hsphy"; reg =3D <0x220 0x10>; #phy-cells =3D <0>; @@ -870,7 +870,7 @@ usb_hsphy2: hs-phy@220 { <&usb_hs_i2>; }; =20 - usb_hsphy3: hs-phy@230 { + usb_hsphy3: phy@230 { compatible =3D "socionext,uniphier-ld20-usb3-hsphy"; reg =3D <0x230 0x10>; #phy-cells =3D <0>; @@ -884,7 +884,7 @@ usb_hsphy3: hs-phy@230 { <&usb_hs_i2>; }; =20 - usb_ssphy0: ss-phy@300 { + usb_ssphy0: phy@300 { compatible =3D "socionext,uniphier-ld20-usb3-ssphy"; reg =3D <0x300 0x10>; #phy-cells =3D <0>; @@ -895,7 +895,7 @@ usb_ssphy0: ss-phy@300 { vbus-supply =3D <&usb_vbus0>; }; =20 - usb_ssphy1: ss-phy@310 { + usb_ssphy1: phy@310 { compatible =3D "socionext,uniphier-ld20-usb3-ssphy"; reg =3D <0x310 0x10>; #phy-cells =3D <0>; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/= boot/dts/socionext/uniphier-pxs3.dtsi index b0c29510a7da..dd60cc04d6fb 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -370,33 +370,33 @@ smpctrl@59801000 { reg =3D <0x59801000 0x400>; }; =20 - sdctrl@59810000 { + syscon@59810000 { compatible =3D "socionext,uniphier-pxs3-sdctrl", "simple-mfd", "syscon"; reg =3D <0x59810000 0x400>; =20 - sd_clk: clock { + sd_clk: clock-controller { compatible =3D "socionext,uniphier-pxs3-sd-clock"; #clock-cells =3D <1>; }; =20 - sd_rst: reset { + sd_rst: reset-controller { compatible =3D "socionext,uniphier-pxs3-sd-reset"; #reset-cells =3D <1>; }; }; =20 - perictrl@59820000 { + syscon@59820000 { compatible =3D "socionext,uniphier-pxs3-perictrl", "simple-mfd", "syscon"; reg =3D <0x59820000 0x200>; =20 - peri_clk: clock { + peri_clk: clock-controller { compatible =3D "socionext,uniphier-pxs3-peri-clock"; #clock-cells =3D <1>; }; =20 - peri_rst: reset { + peri_rst: reset-controller { compatible =3D "socionext,uniphier-pxs3-peri-reset"; #reset-cells =3D <1>; }; @@ -439,7 +439,7 @@ sd: mmc@5a400000 { sd-uhs-sdr50; }; =20 - soc_glue: soc-glue@5f800000 { + soc_glue: syscon@5f800000 { compatible =3D "socionext,uniphier-pxs3-soc-glue", "simple-mfd", "syscon"; reg =3D <0x5f800000 0x2000>; @@ -449,7 +449,7 @@ pinctrl: pinctrl { }; }; =20 - soc-glue@5f900000 { + syscon@5f900000 { compatible =3D "socionext,uniphier-pxs3-soc-glue-debug", "simple-mfd"; #address-cells =3D <1>; @@ -535,17 +535,17 @@ gic: interrupt-controller@5fe00000 { interrupts =3D ; }; =20 - sysctrl@61840000 { + syscon@61840000 { compatible =3D "socionext,uniphier-pxs3-sysctrl", "simple-mfd", "syscon"; reg =3D <0x61840000 0x10000>; =20 - sys_clk: clock { + sys_clk: clock-controller { compatible =3D "socionext,uniphier-pxs3-clock"; #clock-cells =3D <1>; }; =20 - sys_rst: reset { + sys_rst: reset-controller { compatible =3D "socionext,uniphier-pxs3-reset"; #reset-cells =3D <1>; }; @@ -707,7 +707,7 @@ usb-controller@65b00000 { #size-cells =3D <1>; ranges =3D <0 0x65b00000 0x400>; =20 - usb0_rst: reset@0 { + usb0_rst: reset-controller@0 { compatible =3D "socionext,uniphier-pxs3-usb3-reset"; reg =3D <0x0 0x4>; #reset-cells =3D <1>; @@ -735,7 +735,7 @@ usb0_vbus1: regulator@110 { resets =3D <&sys_rst 12>; }; =20 - usb0_hsphy0: hs-phy@200 { + usb0_hsphy0: phy@200 { compatible =3D "socionext,uniphier-pxs3-usb3-hsphy"; reg =3D <0x200 0x10>; #phy-cells =3D <0>; @@ -749,7 +749,7 @@ usb0_hsphy0: hs-phy@200 { <&usb_hs_i0>; }; =20 - usb0_hsphy1: hs-phy@210 { + usb0_hsphy1: phy@210 { compatible =3D "socionext,uniphier-pxs3-usb3-hsphy"; reg =3D <0x210 0x10>; #phy-cells =3D <0>; @@ -763,7 +763,7 @@ usb0_hsphy1: hs-phy@210 { <&usb_hs_i0>; }; =20 - usb0_ssphy0: ss-phy@300 { + usb0_ssphy0: phy@300 { compatible =3D "socionext,uniphier-pxs3-usb3-ssphy"; reg =3D <0x300 0x10>; #phy-cells =3D <0>; @@ -774,7 +774,7 @@ usb0_ssphy0: ss-phy@300 { vbus-supply =3D <&usb0_vbus0>; }; =20 - usb0_ssphy1: ss-phy@310 { + usb0_ssphy1: phy@310 { compatible =3D "socionext,uniphier-pxs3-usb3-ssphy"; reg =3D <0x310 0x10>; #phy-cells =3D <0>; @@ -809,7 +809,7 @@ usb-controller@65d00000 { #size-cells =3D <1>; ranges =3D <0 0x65d00000 0x400>; =20 - usb1_rst: reset@0 { + usb1_rst: reset-controller@0 { compatible =3D "socionext,uniphier-pxs3-usb3-reset"; reg =3D <0x0 0x4>; #reset-cells =3D <1>; @@ -837,7 +837,7 @@ usb1_vbus1: regulator@110 { resets =3D <&sys_rst 13>; }; =20 - usb1_hsphy0: hs-phy@200 { + usb1_hsphy0: phy@200 { compatible =3D "socionext,uniphier-pxs3-usb3-hsphy"; reg =3D <0x200 0x10>; #phy-cells =3D <0>; @@ -852,7 +852,7 @@ usb1_hsphy0: hs-phy@200 { <&usb_hs_i2>; }; =20 - usb1_hsphy1: hs-phy@210 { + usb1_hsphy1: phy@210 { compatible =3D "socionext,uniphier-pxs3-usb3-hsphy"; reg =3D <0x210 0x10>; #phy-cells =3D <0>; @@ -867,7 +867,7 @@ usb1_hsphy1: hs-phy@210 { <&usb_hs_i2>; }; =20 - usb1_ssphy0: ss-phy@300 { + usb1_ssphy0: phy@300 { compatible =3D "socionext,uniphier-pxs3-usb3-ssphy"; reg =3D <0x300 0x10>; #phy-cells =3D <0>; --=20 2.25.1