From nobody Wed Nov 13 07:15:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 921F2C05027 for ; Tue, 7 Feb 2023 01:48:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229574AbjBGBsX (ORCPT ); Mon, 6 Feb 2023 20:48:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229707AbjBGBsS (ORCPT ); Mon, 6 Feb 2023 20:48:18 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A056511669; Mon, 6 Feb 2023 17:48:08 -0800 (PST) X-UUID: 75c6aaa4a68911eda06fc9ecc4dadd91-20230207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=C58C6erRFcj0Y1gzWfGeq542Z89QLIHIvaY5QVjo2Tk=; b=CCJWWqxvB0UMpdFPdOyblH00iKv4d+B1EGRMtgburWSk2l965+YG+y7W32MoEIc+mkMGdj0t30zlR643N5ozg44IhuRP4nOB0REUKQzHyZjJm4S20VAHvuj3t2pBmryxl9UeXSM1KsRlLZIKpDlcKJ6Q8XgEDnZO1NxeO/MoTpo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:edd9af3d-b235-494b-99fe-21b5d4effdc3,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:885ddb2,CLOUDID:dd437f56-dd49-462e-a4be-2143a3ddc739,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 75c6aaa4a68911eda06fc9ecc4dadd91-20230207 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1536976094; Tue, 07 Feb 2023 09:48:03 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 7 Feb 2023 09:48:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 7 Feb 2023 09:48:02 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Michael Turquette , Stephen Boyd CC: , , , , , , Moudy Ho Subject: [PATCH v7 1/1] clk: mediatek: remove MT8195 vppsys/0/1 simple_probe Date: Tue, 7 Feb 2023 09:48:00 +0800 Message-ID: <20230207014800.7619-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230207014800.7619-1-moudy.ho@mediatek.com> References: <20230207014800.7619-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8195 VPPSYS0/1 will be probed by the compatible name in the mtk-mmsys driver and then probe its own clock driver as a platform driver. Signed-off-by: Moudy Ho Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8195-vpp0.c | 58 +++++++++++++++++++------- drivers/clk/mediatek/clk-mt8195-vpp1.c | 58 +++++++++++++++++++------- 2 files changed, 86 insertions(+), 30 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/= clk-mt8195-vpp0.c index bf2939c3a0230..debff9a8c071a 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -86,26 +86,54 @@ static const struct mtk_gate vpp0_clks[] =3D { GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_= wpe_vpp", 3), }; =20 -static const struct mtk_clk_desc vpp0_desc =3D { - .clks =3D vpp0_clks, - .num_clks =3D ARRAY_SIZE(vpp0_clks), -}; +static int clk_mt8195_vpp0_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + struct clk_hw_onecell_data *clk_data; + int r; =20 -static const struct of_device_id of_match_clk_mt8195_vpp0[] =3D { - { - .compatible =3D "mediatek,mt8195-vppsys0", - .data =3D &vpp0_desc, - }, { - /* sentinel */ - } -}; + clk_data =3D mtk_alloc_clk_data(CLK_VPP0_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r =3D mtk_clk_register_gates(&pdev->dev, node, vpp0_clks, ARRAY_SIZE(vpp0= _clks), clk_data); + if (r) + goto free_vpp0_data; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_gates; + + platform_set_drvdata(pdev, clk_data); + + return r; + +unregister_gates: + mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); +free_vpp0_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt8195_vpp0_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} =20 static struct platform_driver clk_mt8195_vpp0_drv =3D { - .probe =3D mtk_clk_simple_probe, - .remove =3D mtk_clk_simple_remove, + .probe =3D clk_mt8195_vpp0_probe, + .remove =3D clk_mt8195_vpp0_remove, .driver =3D { .name =3D "clk-mt8195-vpp0", - .of_match_table =3D of_match_clk_mt8195_vpp0, }, }; builtin_platform_driver(clk_mt8195_vpp0_drv); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/= clk-mt8195-vpp1.c index ffd52c7628909..beacbd94ef02a 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -84,26 +84,54 @@ static const struct mtk_gate vpp1_clks[] =3D { GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26), }; =20 -static const struct mtk_clk_desc vpp1_desc =3D { - .clks =3D vpp1_clks, - .num_clks =3D ARRAY_SIZE(vpp1_clks), -}; +static int clk_mt8195_vpp1_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + struct clk_hw_onecell_data *clk_data; + int r; =20 -static const struct of_device_id of_match_clk_mt8195_vpp1[] =3D { - { - .compatible =3D "mediatek,mt8195-vppsys1", - .data =3D &vpp1_desc, - }, { - /* sentinel */ - } -}; + clk_data =3D mtk_alloc_clk_data(CLK_VPP1_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r =3D mtk_clk_register_gates(&pdev->dev, node, vpp1_clks, ARRAY_SIZE(vpp1= _clks), clk_data); + if (r) + goto free_vpp1_data; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_gates; + + platform_set_drvdata(pdev, clk_data); + + return r; + +unregister_gates: + mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); +free_vpp1_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt8195_vpp1_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->parent->of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} =20 static struct platform_driver clk_mt8195_vpp1_drv =3D { - .probe =3D mtk_clk_simple_probe, - .remove =3D mtk_clk_simple_remove, + .probe =3D clk_mt8195_vpp1_probe, + .remove =3D clk_mt8195_vpp1_remove, .driver =3D { .name =3D "clk-mt8195-vpp1", - .of_match_table =3D of_match_clk_mt8195_vpp1, }, }; builtin_platform_driver(clk_mt8195_vpp1_drv); --=20 2.18.0