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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id o13-20020a5d670d000000b002c8476dde7asm12657607wru.114.2023.03.07.05.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:46:38 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 14:46:28 +0100 Subject: [PATCH 3/6] arm64: dts: mediatek: add power domain support for mt8365 SoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230207-iommu-support-v1-3-4f0c81fd52c1@baylibre.com> References: <20230207-iommu-support-v1-0-4f0c81fd52c1@baylibre.com> In-Reply-To: <20230207-iommu-support-v1-0-4f0c81fd52c1@baylibre.com> To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Yong Wu , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following power domain are added to the SoC dts: - MM (MultiMedia) - CONN (Connectivity) - MFG (MFlexGraphics) - Audio - Cam (Camera) - DSP (Digital Signal Processor) - Vdec (Video decoder) - Venc (Video encoder) - APU (AI Processor Unit) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 129 +++++++++++++++++++++++++++= ++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index b5f5c77f7f84..67b375fe2020 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8365"; @@ -282,6 +283,115 @@ syscfg_pctl: syscfg-pctl@10005000 { reg =3D <0 0x10005000 0 0x1000>; }; =20 + scpsys: syscon@10006000 { + compatible =3D "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + reg =3D <0 0x10006000 0 0x1000>; + #power-domain-cells =3D <1>; + + /* System Power Manager */ + spm: power-controller { + compatible =3D "mediatek,mt8365-power-controller"; + #address-cells =3D <1>; + #size-cells =3D <0>; + #power-domain-cells =3D <1>; + + /* power domains of the SoC */ + power-domain@MT8365_POWER_DOMAIN_MM { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MM_SEL>, + <&mmsys CLK_MM_MM_SMI_COMMON>, + <&mmsys CLK_MM_MM_SMI_COMM0>, + <&mmsys CLK_MM_MM_SMI_COMM1>, + <&mmsys CLK_MM_MM_SMI_LARB0>; + clock-names =3D "mm", "mm-0", "mm-1", + "mm-2", "mm-3"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + mediatek,infracfg-nao =3D <&infracfg_nao>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + power-domain@MT8365_POWER_DOMAIN_CAM { + reg =3D ; + clocks =3D <&camsys CLK_CAM_LARB2>, + <&camsys CLK_CAM_SENIF>, + <&camsys CLK_CAMSV0>, + <&camsys CLK_CAMSV1>, + <&camsys CLK_CAM_FDVT>, + <&camsys CLK_CAM_WPE>; + clock-names =3D "cam-0", "cam-1", + "cam-2", "cam-3", + "cam-4", "cam-5"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_VDEC { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_VENC { + reg =3D ; + #power-domain-cells =3D <0>; + }; + + power-domain@MT8365_POWER_DOMAIN_APU { + reg =3D ; + clocks =3D <&infracfg CLK_IFR_APU_AXI>, + <&apu CLK_APU_IPU_CK>, + <&apu CLK_APU_AXI>, + <&apu CLK_APU_JTAG>, + <&apu CLK_APU_IF_CK>, + <&apu CLK_APU_EDMA>, + <&apu CLK_APU_AHB>; + clock-names =3D "apu", "apu-0", + "apu-1", "apu-2", + "apu-3", "apu-4", + "apu-5"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + }; + + power-domain@MT8365_POWER_DOMAIN_CONN { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_CONN_32K>, + <&topckgen CLK_TOP_CONN_26M>; + clock-names =3D "conn", "conn1"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_MFG { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_MFG_SEL>; + clock-names =3D "mfg"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_AUDIO { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_IFR_AUDIO>, + <&infracfg CLK_IFR_AUD_26M_BK>; + clock-names =3D "audio", "audio1", "audio2"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + + power-domain@MT8365_POWER_DOMAIN_DSP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_DSP_SEL>, + <&topckgen CLK_TOP_DSP_26M>; + clock-names =3D "dsp", "dsp1"; + #power-domain-cells =3D <0>; + mediatek,infracfg =3D <&infracfg>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible =3D "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; @@ -592,6 +702,25 @@ u2port1: usb-phy@1000 { #phy-cells =3D <1>; }; }; + + mmsys: syscon@14000000 { + compatible =3D "mediatek,mt8365-mmsys", "syscon"; + reg =3D <0 0x14000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys: syscon@15000000 { + compatible =3D "mediatek,mt8365-imgsys", "syscon"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + apu: syscon@19020000 { + compatible =3D "mediatek,mt8365-apu", "syscon"; + reg =3D <0 0x19020000 0 0x1000>; + #clock-cells =3D <1>; + }; + }; =20 timer { --=20 b4 0.10.1