From nobody Fri Sep 12 22:27:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D97FAC636D3 for ; Mon, 6 Feb 2023 20:15:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229557AbjBFUP3 (ORCPT ); Mon, 6 Feb 2023 15:15:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbjBFUPX (ORCPT ); Mon, 6 Feb 2023 15:15:23 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E15829E20 for ; Mon, 6 Feb 2023 12:15:22 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id o16-20020a17090ad25000b00230759a8c06so9571286pjw.2 for ; Mon, 06 Feb 2023 12:15:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L3E7gTy1SZ/rYCbfPiq6VlVdMXLKt386NsSmOIvpWA4=; b=d7Hb5NLdauK+98+KYLb/5jnKRBJ18m6p1tGFFJIg+5BAzF9yTJrYEN83GG6vZFh36v yr6yVgcyJ0S3/UU5WvW8M1/P37bmvL4Qp6ruOAw+JCf/J5yfqQXc+gcdzmQMVDGFrTIX ajvfH5AbA9VwC8DX/Tz8SjG+NMTj4W8ZCQyWa0DERSaTTLttMrQ+n4U267it20SgXkDw miF94exCJq5BxV7x6FTNeEfXwfzPfrQWoY+YdVLwg5nN9N7XnIOJR77DL4AomYm4z3Hn SPOD+nriiYYT8z1W9e5yUDnA6YrYR7vt0joB6qLOww83G9Z7FYGE8w7rRbAvB21rawh5 A4fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L3E7gTy1SZ/rYCbfPiq6VlVdMXLKt386NsSmOIvpWA4=; b=pJ2bO/9NDm2Amh2WCbtce5NK40nT8BZoQ8PtKKGulGC2FazAnusT2zYHwMH+TkT4BK 9pkpJwTlzpx5AzI7xtlShnaDweZ4Djwc3TVi5Y4dLDZz0IxS1/byrdtnSq1I+NSumec+ qsKmyagx4T0KvejnNZkwHVI5rmnzmTTHkezSt0Z7e5VzJHuwH/8VwjZwh7TEpdDxaz9S 87eFldq5ShDwAFpA8H2hZGmmkPdzL/0kLhiWG06YIvghCRPkjzNpnZAoWjdsh74naxfw D6fM5vs9sqf4ebgcVIOi3sqNu1ruwJtkaSr3EsyNgqTnb8HhQ944SZYi+srcTotcfFN3 l/ng== X-Gm-Message-State: AO0yUKUsPT+50DF2TcDVpW+wREQlNHQ4frM5aDVdPjHHnaYqzB2wnYbY 78wDjNuSKvuqy9J5tgGQ9pBwNw== X-Google-Smtp-Source: AK7set89wInCODEUg3p17p5zHU1W/mDyBIfYFOL5qrDCXusDtTme4YBO8NalJNVzABW6CNbgFZA8XQ== X-Received: by 2002:a05:6a20:8421:b0:bf:bcfb:1fc2 with SMTP id c33-20020a056a20842100b000bfbcfb1fc2mr884580pzd.45.1675714521714; Mon, 06 Feb 2023 12:15:21 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:21 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Anup Patel , Atish Patra , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Qinglin Pan , Randy Dunlap , Sunil V L , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header Date: Mon, 6 Feb 2023 12:14:50 -0800 Message-Id: <20230206201455.1790329-2-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for tracking and exposing microarchitectural details to userspace (like whether or not unaligned accesses are fast), move the riscv_cpuinfo struct out to its own new cpufeatures.h header. It will need to be used by more than just cpu.c. Signed-off-by: Evan Green Reviewed-by: Conor Dooley --- (no changes since v1) arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ arch/riscv/kernel/cpu.c | 8 ++------ 2 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/include/asm/cpufeature.h diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h new file mode 100644 index 000000000000..66c251d98290 --- /dev/null +++ b/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _ASM_CPUFEATURE_H +#define _ASM_CPUFEATURE_H + +/* + * These are probed via a device_initcall(), via either the SBI or directly + * from the cooresponding CSRs. + */ +struct riscv_cpuinfo { + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; +}; + +DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); + +#endif diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..684e5419d37d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, uns= igned long *hartid) return -1; } =20 -struct riscv_cpuinfo { - unsigned long mvendorid; - unsigned long marchid; - unsigned long mimpid; -}; -static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 unsigned long riscv_cached_mvendorid(unsigned int cpu_id) { --=20 2.25.1 From nobody Fri Sep 12 22:27:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC350C636D4 for ; Mon, 6 Feb 2023 20:15:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229787AbjBFUPi (ORCPT ); Mon, 6 Feb 2023 15:15:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230040AbjBFUPa (ORCPT ); Mon, 6 Feb 2023 15:15:30 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ADD820D26 for ; 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charset="utf-8" We don't have enough space for these all in ELF_HWCAP{,2} and there's no system call that quite does this, so let's just provide an arch-specific one to probe for hardware capabilities. This currently just provides m{arch,imp,vendor}id, but with the key-value pairs we can pass more in the future. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v2: - Changed the interface to look more like poll(). Rather than supplying key_offset and getting back an array of values with numerically contiguous keys, have the user pre-fill the key members of the array, and the kernel will fill in the corresponding values. For any key it doesn't recognize, it will set the key of that element to -1. This allows usermode to quickly ask for exactly the elements it cares about, and not get bogged down in a back and forth about newer keys that older kernels might not recognize. In other words, the kernel can communicate that it doesn't recognize some of the keys while still providing the data for the keys it does know. - Added a shortcut to the cpuset parameters that if a size of 0 and NULL is provided for the CPU set, the kernel will use a cpu mask of all online CPUs. This is convenient because I suspect most callers will only want to act on a feature if it's supported on all CPUs, and it's a headache to dynamically allocate an array of all 1s, not to mention a waste to have the kernel loop over all of the offline bits. --- Documentation/riscv/hwprobe.rst | 37 +++++++ Documentation/riscv/index.rst | 1 + arch/riscv/include/asm/hwprobe.h | 13 +++ arch/riscv/include/asm/syscall.h | 3 + arch/riscv/include/uapi/asm/hwprobe.h | 25 +++++ arch/riscv/include/uapi/asm/unistd.h | 8 ++ arch/riscv/kernel/cpu.c | 3 +- arch/riscv/kernel/sys_riscv.c | 146 +++++++++++++++++++++++++- 8 files changed, 234 insertions(+), 2 deletions(-) create mode 100644 Documentation/riscv/hwprobe.rst create mode 100644 arch/riscv/include/asm/hwprobe.h create mode 100644 arch/riscv/include/uapi/asm/hwprobe.h diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst new file mode 100644 index 000000000000..97771090e972 --- /dev/null +++ b/Documentation/riscv/hwprobe.rst @@ -0,0 +1,37 @@ +.. SPDX-License-Identifier: GPL-2.0 + +RISC-V Hardware Probing Interface +--------------------------------- + +The RISC-V hardware probing interface is based around a single syscall, wh= ich +is defined in :: + + struct riscv_hwprobe { + __s64 key; + __u64 value; + }; + + long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, + size_t cpu_count, cpu_set_t *cpus, + unsigned long flags); + +The arguments are split into three groups: an array of key-value pairs, a = CPU +set, and some flags. The key-value pairs are supplied with a count. User= space +must prepopulate the key field for each element, and the kernel will fill = in the +value if the key is recognized. If a key is unknown to the kernel, its key +field will be cleared to -1, and its value set to 0. The CPU set is defin= ed by +CPU_SET(3), the indicated features will be supported on all CPUs in the se= t. +Usermode can supply NULL for cpus and 0 for cpu_count as a shortcut for all +online CPUs. There are currently no flags, this value must be zero for fut= ure +compatibility. + +On success 0 is returned, on failure a negative error code is returned. + +The following keys are defined: + +* :RISCV_HWPROBE_KEY_MVENDORID:: Contains the value of :mvendorid:, as per= the + ISA specifications. +* :RISCV_HWPROBE_KEY_MARCHID:: Contains the value of :marchid:, as per the= ISA + specifications. +* :RISCV_HWPROBE_KEY_MIMPLID:: Contains the value of :mimplid:, as per the= ISA + specifications. diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 2e5b18fbb145..175a91db0200 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -7,6 +7,7 @@ RISC-V architecture =20 boot-image-header vm-layout + hwprobe patch-acceptance uabi =20 diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h new file mode 100644 index 000000000000..08d1c3bdd78a --- /dev/null +++ b/arch/riscv/include/asm/hwprobe.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _ASM_HWPROBE_H +#define _ASM_HWPROBE_H + +#include + +#define RISCV_HWPROBE_MAX_KEY 2 + +#endif diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/sysc= all.h index 384a63b86420..78a6302ef711 100644 --- a/arch/riscv/include/asm/syscall.h +++ b/arch/riscv/include/asm/syscall.h @@ -75,4 +75,7 @@ static inline int syscall_get_arch(struct task_struct *ta= sk) } =20 asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t); + +asmlinkage long sys_riscv_hwprobe(uintptr_t, uintptr_t, uintptr_t, uintptr= _t, + uintptr_t, uintptr_t); #endif /* _ASM_RISCV_SYSCALL_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h new file mode 100644 index 000000000000..591802047460 --- /dev/null +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _UAPI_ASM_HWPROBE_H +#define _UAPI_ASM_HWPROBE_H + +#include + +/* + * Interface for probing hardware capabilities from userspace, see + * Documentation/riscv/hwprobe.rst for more information. + */ +struct riscv_hwprobe { + __s64 key; + __u64 value; +}; + +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 +/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ + +#endif diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi= /asm/unistd.h index 73d7cdd2ec49..37d47302322a 100644 --- a/arch/riscv/include/uapi/asm/unistd.h +++ b/arch/riscv/include/uapi/asm/unistd.h @@ -43,3 +43,11 @@ #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) #endif __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) + +/* + * Allows userspace to probe + */ +#ifndef __NR_riscv_hwprobe +#define __NR_riscv_hwprobe (__NR_arch_specific_syscall + 14) +#endif +__SYSCALL(__NR_riscv_hwprobe, sys_riscv_hwprobe) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 684e5419d37d..d0fb3567cc3d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -4,15 +4,16 @@ */ =20 #include +#include #include #include #include #include #include #include +#include #include #include -#include =20 /* * Returns the hart ID of the given device tree node, or -ENODEV if the no= de diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5d3f2fbeb33c..868a12384f5a 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -6,8 +6,11 @@ */ =20 #include -#include #include +#include +#include +#include +#include #include =20 static long riscv_sys_mmap(unsigned long addr, unsigned long len, @@ -69,3 +72,144 @@ SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, u= intptr_t, end, =20 return 0; } + +/* + * The hwprobe interface, for allowing userspace to probe to see which fea= tures + * are supported by the hardware. See Documentation/riscv/hwprobe.rst for= more + * details. + */ +static int set_hwprobe(struct riscv_hwprobe __user *pair, u64 val) +{ + long ret; + + ret =3D put_user(val, &pair->value); + if (ret < 0) + return ret; + + return 0; +} + +static long hwprobe_mid(struct riscv_hwprobe __user *pair, size_t key, + cpumask_t *cpus) +{ + long cpu, id; + bool first, valid; + + first =3D true; + valid =3D false; + for_each_cpu(cpu, cpus) { + struct riscv_cpuinfo *ci =3D per_cpu_ptr(&riscv_cpuinfo, cpu); + long cpu_id; + + switch (key) { + case RISCV_HWPROBE_KEY_MVENDORID: + cpu_id =3D ci->mvendorid; + break; + case RISCV_HWPROBE_KEY_MIMPID: + cpu_id =3D ci->mimpid; + break; + case RISCV_HWPROBE_KEY_MARCHID: + cpu_id =3D ci->marchid; + break; + } + + if (first) { + id =3D cpu_id; + valid =3D true; + } + + if (id !=3D cpu_id) + valid =3D false; + } + + /* + * put_user() returns 0 on success, so use 1 to indicate it wasn't + * called and we should skip having incremented the output. + */ + if (!valid) + return 1; + + return set_hwprobe(pair, id); +} + +static +long do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, + long cpu_count, unsigned long __user *cpus_user, + unsigned long flags) +{ + size_t out; + s64 key; + long ret; + struct cpumask cpus; + + /* Check the reserved flags. */ + if (flags !=3D 0) + return -EINVAL; + + /* + * The only supported values must be the same on all CPUs. Allow + * userspace to specify NULL and 0 as a shortcut to all online CPUs. + */ + cpumask_clear(&cpus); + if ((cpu_count =3D=3D 0) && (cpus_user =3D=3D NULL)) { + cpumask_copy(&cpus, cpu_online_mask); + } else { + if (cpu_count > cpumask_size()) + cpu_count =3D cpumask_size(); + ret =3D copy_from_user(&cpus, cpus_user, cpu_count); + if (!ret) + return -EFAULT; + + /* + * Userspace must provide at least one online CPU, without that there's + * no way to define what is supported. + */ + cpumask_and(&cpus, &cpus, cpu_online_mask); + if (cpumask_empty(&cpus)) + return -EINVAL; + } + + for (out =3D 0; out < pair_count; out++, pairs++) { + long ret; + + if (get_user(key, &pairs->key)) + return -EFAULT; + + switch (key) { + case RISCV_HWPROBE_KEY_MVENDORID: + case RISCV_HWPROBE_KEY_MARCHID: + case RISCV_HWPROBE_KEY_MIMPID: + ret =3D hwprobe_mid(pairs, key, &cpus); + break; + + /* + * For forward compatibility, unknown keys don't fail the whole + * call, but get their element key set to -1 and value set to 0 + * indicating they're unrecognized. + */ + default: + ret =3D put_user(-1, &pairs->key); + if (ret < 0) + return ret; + + ret =3D set_hwprobe(pairs, 0); + if (ret) + return ret; + + break; + } + + if (ret < 0) + return ret; + } + + return 0; + +} + +SYSCALL_DEFINE5(riscv_hwprobe, uintptr_t, pairs, uintptr_t, pair_count, + uintptr_t, cpu_count, uintptr_t, cpus, uintptr_t, flags) +{ + return do_riscv_hwprobe((void __user *)pairs, pair_count, cpu_count, + (void __user *)cpus, flags); +} --=20 2.25.1 From nobody Fri Sep 12 22:27:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1A8CC636D3 for ; Mon, 6 Feb 2023 20:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229705AbjBFUPn (ORCPT ); Mon, 6 Feb 2023 15:15:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230204AbjBFUPi (ORCPT ); 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Mon, 06 Feb 2023 12:15:30 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Andrew Bresticker , Celeste Liu , Guo Ren , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , dram , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Mon, 6 Feb 2023 12:14:52 -0800 Message-Id: <20230206201455.1790329-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Palmer Dabbelt We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- (no changes since v1) Documentation/riscv/hwprobe.rst | 16 ++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 6 +++++- arch/riscv/kernel/sys_riscv.c | 23 +++++++++++++++++++++++ 4 files changed, 45 insertions(+), 2 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 97771090e972..ce186967861f 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -35,3 +35,19 @@ The following keys are defined: specifications. * :RISCV_HWPROBE_KEY_MIMPLID:: Contains the value of :mimplid:, as per the= ISA specifications. +* :RISCV_HWPROBE_KEY_BASE_BEHAVIOR:: A bitmask containing the base user-vi= sible + behavior that this kernel supports. The following base user ABIs are de= fined: + * :RISCV_HWPROBE_BASE_BEHAVIOR_IMA:: Support for rv32ima or rv64ima, as + defined by version 2.2 of the user ISA and version 1.10 of the privi= leged + ISA, with the following known exceptions (more exceptions may be add= ed, + but only if it can be demonstrated that the user ABI is not broken): + * The :fence.i: instruction cannot be directly executed by userspa= ce + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). +* :RISCV_HWPROBE_KEY_IMA_EXT_0:: A bitmask containing the extensions that = are + compatible with the :RISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavi= or. + * :RISCV_HWPROBE_IMA_FD:: The F and D extensions are supported, as def= ined + by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNum= ber, + not minNum/maxNum") of the RISC-V ISA manual. + * :RISCV_HWPROBE_IMA_C:: The C extension is supported, as defined by + version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 08d1c3bdd78a..7e52f1e1fe10 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 =20 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 591802047460..ce39d6e74103 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,10 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ - #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 868a12384f5a..74e0d72c877d 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,28 @@ long do_riscv_hwprobe(struct riscv_hwprobe __user *pai= rs, long pair_count, ret =3D hwprobe_mid(pairs, key, &cpus); break; =20 + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + ret =3D set_hwprobe(pairs, RISCV_HWPROBE_BASE_BEHAVIOR_IMA); + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + { + u64 val =3D 0; + + if (has_fpu()) + val |=3D RISCV_HWPROBE_IMA_FD; + if (elf_hwcap & RISCV_ISA_EXT_c) + val |=3D RISCV_HWPROBE_IMA_C; + ret =3D set_hwprobe(pairs, val); + } + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 --=20 2.25.1 From nobody Fri Sep 12 22:27:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A42F7C6379F for ; Mon, 6 Feb 2023 20:15:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230178AbjBFUPx (ORCPT ); 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Mon, 06 Feb 2023 12:15:33 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 4/6] dt-bindings: Add RISC-V misaligned access performance Date: Mon, 6 Feb 2023 12:14:53 -0800 Message-Id: <20230206201455.1790329-5-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Palmer Dabbelt This key allows device trees to specify the performance of misaligned accesses to main memory regions from each CPU in the system. Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- (no changes since v1) Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index c6720764e765..2c09bd6f2927 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -85,6 +85,21 @@ properties: $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ =20 + riscv,misaligned-access-performance: + description: + Identifies the performance of misaligned memory accesses to main mem= ory + regions. There are three flavors of unaligned access performance: "= emulated" + means that misaligned accesses are emulated via software and thus + extremely slow, "slow" means that misaligned accesses are supported = by + hardware but still slower that aligned accesses sequences, and "fast" + means that misaligned accesses are as fast or faster than the + cooresponding aligned accesses sequences. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - emulated + - slow + - fast + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false =20 --=20 2.25.1 From nobody Fri Sep 12 22:27:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E28C4C05027 for ; Mon, 6 Feb 2023 20:16:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230302AbjBFUQA (ORCPT ); Mon, 6 Feb 2023 15:16:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230160AbjBFUPx (ORCPT ); Mon, 6 Feb 2023 15:15:53 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E136B298D8 for ; Mon, 6 Feb 2023 12:15:38 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id u9so9137194plf.3 for ; Mon, 06 Feb 2023 12:15:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4NHVkmDL1+Nl1bWyENrxaEG8nDhTyqPy5db4QyUwgAo=; b=e8e+hue89xD8AFuDM03gwXKPLXaajuv/b6VKDvoCoBf/iT/zGbXP5ooZz6ZYbxq6Ol pRMgq09e2uQzEmi3gW2ANefxMoKxdin+1LUdy2mn4NylyIUDGaTWDxyjf1oczOmGaopv ndd3dltEwWjxIEDp1GgserBBoHjJv3C9Pc6EWZJRz/RZNmqctSUvEAebndq63RXZ+k7V /m63PZ0vyxSC7rZCehQpF0Svw1z8LboRIPAztWTftiwt30MEirNTJr2AMxI+5Tj7uC5w Tl2CfBrbUBvVi8ZqW29uwBXyWdzGmZ0ZA5goqX/HCZIg74rzSCOVCE2WwS2IAOgVugOP uEVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4NHVkmDL1+Nl1bWyENrxaEG8nDhTyqPy5db4QyUwgAo=; b=2hLXDrW7KqByb277sfCdJGDwKy0rxjgbwDXY2tB8MOZtA+cEzkffmHe4uR1POo9qBW UXEq/xGPyiblHov/jqxL/rg7g7FXiyUEKIyJp10ZsdrYXSw6dolcpUjAngr8fVJFhRlo zBu6rgRRo7FROVoUCEK5y7c4mzppSrpquKFZeK8fROX61wIESStNK3CPw70ghH4VII9i 3B9g5p3HDVEb9Fb/x+u1oNsRwzQa3g0bBQtWKrKPrqL9KjiStpD2TKiDdtxWryMJgf3m veXFLFT7wOL9teFhNCiZfp67nHO5b0YiU/DCharw7/5D819hWv65uFhIyWaqK7tszC7B eiuw== X-Gm-Message-State: AO0yUKWPnKoiL0pClI2t6q32FCeUnSrusXL+KzqF0pbBONCZ6XtsEKCt 1ZuW3gTVaYfldN4YVggA4cYyDg== X-Google-Smtp-Source: AK7set+JVHNnFfvIUBCDQKktjW0TUQczLdFGPbSNh2d9L/P8+GzUJBG4uu0TKecEvC/h+y8Fy8TFlQ== X-Received: by 2002:a17:90b:3ecc:b0:22b:fff0:f80c with SMTP id rm12-20020a17090b3ecc00b0022bfff0f80cmr1033780pjb.1.1675714538280; Mon, 06 Feb 2023 12:15:38 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:37 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Andrew Bresticker , Andrew Jones , Anup Patel , Arnd Bergmann , Atish Patra , Celeste Liu , Guo Ren , Heinrich Schuchardt , Jisheng Zhang , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , Sunil V L , Tsukasa OI , Xianting Tian , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 5/6] RISC-V: hwprobe: Support probing of misaligned access performance Date: Mon, 6 Feb 2023 12:14:54 -0800 Message-Id: <20230206201455.1790329-6-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This allows userspace to select various routines to use based on the performance of misaligned access on the target hardware. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v2: - Fixed logic error in if(of_property_read_string...) that caused crash - Include cpufeature.h in cpufeature.h to avoid undeclared variable warning. - Added a _MASK define - Fix random checkpatch complaints Documentation/riscv/hwprobe.rst | 13 +++++++++++ arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/asm/smp.h | 9 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 6 ++++++ arch/riscv/kernel/cpufeature.c | 31 +++++++++++++++++++++++++-- arch/riscv/kernel/sys_riscv.c | 23 ++++++++++++++++++++ 7 files changed, 83 insertions(+), 3 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index ce186967861f..0dc75e83e127 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -51,3 +51,16 @@ The following keys are defined: not minNum/maxNum") of the RISC-V ISA manual. * :RISCV_HWPROBE_IMA_C:: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. +* :RISCV_HWPROBE_KEY_PERF_0:: A bitmask that contains performance informat= ion + about the selected set of processors. + * :RISCV_HWPROBE_MISALIGNED_UNKNOWN:: The performance of misaligned + accesses is unknown. + * :RISCV_HWPROBE_MISALIGNED_EMULATED:: Misaligned accesses are emulate= d via + software, either in or below the kernel. These accesses are always + extremely slow. + * :RISCV_HWPROBE_MISALIGNED_SLOW:: Misaligned accesses are supported in + hardware, but are slower than the cooresponding aligned accesses + sequences. + * :RISCV_HWPROBE_MISALIGNED_FAST:: Misaligned accesses are supported in + hardware and are faster than the cooresponding aligned accesses + sequences. diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 66c251d98290..ac51a9e6387a 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -18,4 +18,6 @@ struct riscv_cpuinfo { =20 DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 +DECLARE_PER_CPU(long, misaligned_access_speed); + #endif diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 7e52f1e1fe10..4e45e33015bc 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 4 +#define RISCV_HWPROBE_MAX_KEY 5 =20 #endif diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 3831b638ecab..6c1759091e44 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -26,6 +26,15 @@ struct riscv_ipi_ops { */ extern unsigned long __cpuid_to_hartid_map[NR_CPUS]; #define cpuid_to_hartid_map(cpu) __cpuid_to_hartid_map[cpu] +static inline long hartid_to_cpuid_map(unsigned long hartid) +{ + long i; + + for (i =3D 0; i < NR_CPUS; ++i) + if (cpuid_to_hartid_map(i) =3D=3D hartid) + return i; + return -1; +} =20 /* print IPI stats */ void show_ipi_stats(struct seq_file *p, int prec); diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index ce39d6e74103..5d55e2da2b1f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,5 +25,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (3 << 0) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 93e45560af30..12af6f7a2f53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -32,6 +34,9 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __rea= d_mostly; DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); EXPORT_SYMBOL(riscv_isa_ext_keys); =20 +/* Performance information */ +DEFINE_PER_CPU(long, misaligned_access_speed); + /** * riscv_isa_extension_base() - Get base extension word * @@ -89,11 +94,11 @@ static bool riscv_isa_extension_check(int id) void __init riscv_fill_hwcap(void) { struct device_node *node; - const char *isa; + const char *isa, *misaligned; char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] =3D {0}; - unsigned long hartid; + unsigned long hartid, cpu; =20 isa2hwcap['i' - 'a'] =3D COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] =3D COMPAT_HWCAP_ISA_M; @@ -246,6 +251,28 @@ void __init riscv_fill_hwcap(void) bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + + /* + * Check for the performance of misaligned accesses. + */ + cpu =3D hartid_to_cpuid_map(hartid); + if (cpu < 0) + continue; + + if (!of_property_read_string(node, "riscv,misaligned-access-performance", + &misaligned)) { + if (strcmp(misaligned, "emulated") =3D=3D 0) + per_cpu(misaligned_access_speed, cpu) =3D + RISCV_HWPROBE_MISALIGNED_EMULATED; + + if (strcmp(misaligned, "slow") =3D=3D 0) + per_cpu(misaligned_access_speed, cpu) =3D + RISCV_HWPROBE_MISALIGNED_SLOW; + + if (strcmp(misaligned, "fast") =3D=3D 0) + per_cpu(misaligned_access_speed, cpu) =3D + RISCV_HWPROBE_MISALIGNED_FAST; + } } =20 /* We don't support systems with F but without D, so mask those out diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 74e0d72c877d..73d937c54f4e 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -133,6 +133,25 @@ static long hwprobe_mid(struct riscv_hwprobe __user *p= air, size_t key, return set_hwprobe(pair, id); } =20 +static long hwprobe_misaligned(cpumask_t *cpus) +{ + long cpu, perf =3D -1; + + for_each_cpu(cpu, cpus) { + long this_perf =3D per_cpu(misaligned_access_speed, cpu); + + if (perf =3D=3D -1) + perf =3D this_perf; + + if (perf !=3D this_perf) + perf =3D RISCV_HWPROBE_MISALIGNED_UNKNOWN; + } + + if (perf =3D=3D -1) + return RISCV_HWPROBE_MISALIGNED_UNKNOWN; + return perf; +} + static long do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, long cpu_count, unsigned long __user *cpus_user, @@ -205,6 +224,10 @@ long do_riscv_hwprobe(struct riscv_hwprobe __user *pai= rs, long pair_count, } break; =20 + case RISCV_HWPROBE_KEY_CPUPERF_0: + ret =3D set_hwprobe(pairs, hwprobe_misaligned(&cpus)); + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 --=20 2.25.1 From nobody Fri Sep 12 22:27:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E6DC05027 for ; Mon, 6 Feb 2023 20:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229614AbjBFUQL (ORCPT ); Mon, 6 Feb 2023 15:16:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230270AbjBFUP6 (ORCPT ); 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Mon, 06 Feb 2023 12:15:41 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Catalin Marinas , Mark Brown , Palmer Dabbelt , Paul Walmsley , Shuah Khan , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 6/6] selftests: Test the new RISC-V hwprobe interface Date: Mon, 6 Feb 2023 12:14:55 -0800 Message-Id: <20230206201455.1790329-7-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds a test for the recently added RISC-V interface for probing hardware capabilities. It happens to be the first selftest we have for RISC-V, so I've added some infrastructure for those as well. The build stuff looks pretty straight-forward, but there's also a tiny C library to avoid coupling this to any userspace implementation. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v2: - Updated the selftests to the new API and added some more. - Fixed indentation, comments in .S, and general checkpatch complaints. --- tools/testing/selftests/Makefile | 1 + tools/testing/selftests/riscv/Makefile | 58 ++++++++++++ .../testing/selftests/riscv/hwprobe/Makefile | 10 +++ .../testing/selftests/riscv/hwprobe/hwprobe.c | 89 +++++++++++++++++++ .../selftests/riscv/hwprobe/sys_hwprobe.S | 12 +++ tools/testing/selftests/riscv/libc.S | 46 ++++++++++ 6 files changed, 216 insertions(+) create mode 100644 tools/testing/selftests/riscv/Makefile create mode 100644 tools/testing/selftests/riscv/hwprobe/Makefile create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.c create mode 100644 tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S create mode 100644 tools/testing/selftests/riscv/libc.S diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Mak= efile index 41b649452560..a599ef726310 100644 --- a/tools/testing/selftests/Makefile +++ b/tools/testing/selftests/Makefile @@ -62,6 +62,7 @@ TARGETS +=3D pstore TARGETS +=3D ptrace TARGETS +=3D openat2 TARGETS +=3D resctrl +TARGETS +=3D riscv TARGETS +=3D rlimits TARGETS +=3D rseq TARGETS +=3D rtc diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftes= ts/riscv/Makefile new file mode 100644 index 000000000000..32a72902d045 --- /dev/null +++ b/tools/testing/selftests/riscv/Makefile @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +# Originally tools/testing/arm64/Makefile + +# When ARCH not overridden for crosscompiling, lookup machine +ARCH ?=3D $(shell uname -m 2>/dev/null || echo not) + +ifneq (,$(filter $(ARCH),riscv)) +RISCV_SUBTARGETS ?=3D hwprobe +else +RISCV_SUBTARGETS :=3D +endif + +CFLAGS :=3D -Wall -O2 -g + +# A proper top_srcdir is needed by KSFT(lib.mk) +top_srcdir =3D $(realpath ../../../../) + +# Additional include paths needed by kselftest.h and local headers +CFLAGS +=3D -I$(top_srcdir)/tools/testing/selftests/ + +CFLAGS +=3D $(KHDR_INCLUDES) + +export CFLAGS +export top_srcdir + +all: + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=3D$(OUTPUT)/$$DIR; \ + mkdir -p $$BUILD_TARGET; \ + $(MAKE) OUTPUT=3D$$BUILD_TARGET -C $$DIR $@; \ + done + +install: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=3D$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=3D$$BUILD_TARGET -C $$DIR $@; \ + done + +run_tests: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=3D$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=3D$$BUILD_TARGET -C $$DIR $@; \ + done + +# Avoid any output on non riscv on emit_tests +emit_tests: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=3D$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=3D$$BUILD_TARGET -C $$DIR $@; \ + done + +clean: + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=3D$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=3D$$BUILD_TARGET -C $$DIR $@; \ + done + +.PHONY: all clean install run_tests emit_tests diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing= /selftests/riscv/hwprobe/Makefile new file mode 100644 index 000000000000..614501584803 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2021 ARM Limited +# Originally tools/testing/arm64/abi/Makefile + +TEST_GEN_PROGS :=3D hwprobe + +include ../../lib.mk + +$(OUTPUT)/hwprobe: hwprobe.c ../libc.S sys_hwprobe.S + $(CC) -o$@ $(CFLAGS) $(LDFLAGS) -nostdlib $^ diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testin= g/selftests/riscv/hwprobe/hwprobe.c new file mode 100644 index 000000000000..ddfb61de2938 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +/* + * Rather than relying on having a new enough libc to define this, just do= it + * ourselves. This way we don't need to be coupled to a new-enough libc to + * contain the call. + */ +long riscv_hwprobe(struct riscv_hwprobe *pairs, long pair_count, + long cpu_count, unsigned long *cpus, unsigned long flags); + +int main(int argc, char **argv) +{ + struct riscv_hwprobe pairs[8]; + unsigned long cpus; + long out; + + /* Fake the CPU_SET ops. */ + cpus =3D -1; + + /* + * Just run a basic test: pass enough pairs to get up to the base + * behavior, and then check to make sure it's sane. + */ + for (long i =3D 0; i < 8; i++) + pairs[i].key =3D i; + out =3D riscv_hwprobe(pairs, 8, 1, &cpus, 0); + if (out !=3D 0) + return -1; + for (long i =3D 0; i < 4; ++i) { + /* Fail if the kernel claims not to recognize a base key. */ + if ((i < 4) && (pairs[i].key !=3D i)) + return -2; + + if (pairs[i].key !=3D RISCV_HWPROBE_KEY_BASE_BEHAVIOR) + continue; + + if (pairs[i].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) + continue; + + return -3; + } + + /* + * This should also work with a NULL CPU set, but should not work + * with an improperly supplied CPU set. + */ + out =3D riscv_hwprobe(pairs, 8, 0, 0, 0); + if (out !=3D 0) + return -4; + + out =3D riscv_hwprobe(pairs, 8, 0, &cpus, 0); + if (out =3D=3D 0) + return -5; + + out =3D riscv_hwprobe(pairs, 8, 1, 0, 0); + if (out =3D=3D 0) + return -6; + + /* + * Check that keys work by providing one that we know exists, and + * checking to make sure the resultig pair is what we asked for. + */ + pairs[0].key =3D RISCV_HWPROBE_KEY_BASE_BEHAVIOR; + out =3D riscv_hwprobe(pairs, 1, 1, &cpus, 0); + if (out !=3D 0) + return -7; + if (pairs[0].key !=3D RISCV_HWPROBE_KEY_BASE_BEHAVIOR) + return -8; + + /* + * Check that an unknown key gets overwritten with -1, + * but doesn't block elements after it. + */ + pairs[0].key =3D 0x5555; + pairs[1].key =3D 1; + pairs[1].value =3D 0xAAAA; + out =3D riscv_hwprobe(pairs, 2, 0, 0, 0); + if (out !=3D 0) + return -9; + + if (pairs[0].key !=3D -1) + return -10; + + if ((pairs[1].key !=3D 1) || (pairs[1].value =3D=3D 0xAAAA)) + return -11; + + return 0; +} diff --git a/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S b/tools/te= sting/selftests/riscv/hwprobe/sys_hwprobe.S new file mode 100644 index 000000000000..ed8d28863b27 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2022 Rivos, Inc */ + +.text +.global riscv_hwprobe +riscv_hwprobe: + # Put __NR_riscv_hwprobe in the syscall number register, then just shim + # back the kernel's return. This doesn't do any sort of errno + # handling, the caller can deal with it. + li a7, 258 + ecall + ret diff --git a/tools/testing/selftests/riscv/libc.S b/tools/testing/selftests= /riscv/libc.S new file mode 100644 index 000000000000..1041bbea9b6b --- /dev/null +++ b/tools/testing/selftests/riscv/libc.S @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2022 Rivos, Inc */ +/* A C library */ + +#if __riscv_xlen =3D=3D 64 +# define REG_S sd +#else +# define REG_S sw +#endif + +.text +.global _start +_start: +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la sp, stack + + la t0, heap + la t1, brk + REG_S t0, 0(t1) + + li a0, 0 + li a1, 0 + + call main + + li a7, 93 + ecall + +1: + j 1b + +.data +brk: + .long 0 + +.global heap +heap: +.rep 65536 +.byte 0 +.endr +.global stack +stack: --=20 2.25.1