From nobody Wed Nov 13 07:17:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56782C05027 for ; Mon, 6 Feb 2023 10:02:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229525AbjBFKB6 (ORCPT ); Mon, 6 Feb 2023 05:01:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229573AbjBFKBW (ORCPT ); Mon, 6 Feb 2023 05:01:22 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAF9C12850; Mon, 6 Feb 2023 02:01:17 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9490B6602F90; Mon, 6 Feb 2023 10:01:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675677676; bh=JSh/wdVnPgjT9XpgJxJRzIiGnPbLZPZnhfU8/MKT0ag=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GwT05yb7Fv6vqjZvaH15YcVpRxZZh8uajUpG9goYDGOs6UNzggUFJhwgzSDtrzmoz uXCVv+5ZNwrfHgsMmrbRsEK76h2rERW4CKrDc63DRiG7xu4xzMufAjVzeAZjXzak9C hIagdfxiyliaiBK3bZ0PR3flyy2C5zLggJJ3+NcU+D2vwNdYvJeg4RVRxtX3R+AG3I 9+y2oahjtUdTmDuK5kG3/62SgI9wjUPgwoyVnhKhTRWLcnNTkmXarn1SmlVncMTnKX zx7MZE9+7MFEwbrLaGlpjCcEkl9pwUCyc2Nu/Tt6WehiCv1z6sDdWOJXvyEEHPTPB4 OXN3ZsX5aRbhw== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 1/7] clk: mediatek: fhctl: Add support for older fhctl register layout Date: Mon, 6 Feb 2023 11:00:59 +0100 Message-Id: <20230206100105.861720-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> References: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Frequency Hopping Controller (FHCTL) seems to have different versions, as it has a slightly different register layout on some older SoCs like MT6795, MT8173, MT8183 (and others). This driver is indeed compatible with at least some of those older IP revisions, so all we need to do is to add a way to select the right register layout at registration time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-fhctl.c | 26 +++++++++++++++++--- drivers/clk/mediatek/clk-fhctl.h | 9 ++++++- drivers/clk/mediatek/clk-mt8186-apmixedsys.c | 2 ++ drivers/clk/mediatek/clk-pllfh.c | 23 +++++++++++++---- drivers/clk/mediatek/clk-pllfh.h | 1 + 5 files changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/clk/mediatek/clk-fhctl.c b/drivers/clk/mediatek/clk-fh= ctl.c index 4f271acef5fe..45e4842cbf04 100644 --- a/drivers/clk/mediatek/clk-fhctl.c +++ b/drivers/clk/mediatek/clk-fhctl.c @@ -14,7 +14,20 @@ #define PERCENT_TO_DDSLMT(dds, percent_m10) \ ((((dds) * (percent_m10)) >> 5) / 100) =20 -static const struct fhctl_offset fhctl_offset =3D { +const struct fhctl_offset fhctl_offset_v1 =3D { + .offset_hp_en =3D 0x0, + .offset_clk_con =3D 0x4, + .offset_rst_con =3D 0x8, + .offset_slope0 =3D 0xc, + .offset_slope1 =3D 0x10, + .offset_cfg =3D 0x0, + .offset_updnlmt =3D 0x4, + .offset_dds =3D 0x8, + .offset_dvfs =3D 0xc, + .offset_mon =3D 0x10, +}; + +const struct fhctl_offset fhctl_offset_v2 =3D { .offset_hp_en =3D 0x0, .offset_clk_con =3D 0x8, .offset_rst_con =3D 0xc, @@ -27,9 +40,16 @@ static const struct fhctl_offset fhctl_offset =3D { .offset_mon =3D 0x10, }; =20 -const struct fhctl_offset *fhctl_get_offset_table(void) +const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v) { - return &fhctl_offset; + switch (v) { + case FHCTL_PLLFH_V1: + return &fhctl_offset_v1; + case FHCTL_PLLFH_V2: + return &fhctl_offset_v2; + default: + return ERR_PTR(-EINVAL); + }; } =20 static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs, diff --git a/drivers/clk/mediatek/clk-fhctl.h b/drivers/clk/mediatek/clk-fh= ctl.h index 51275febf086..bfa6d281a3ee 100644 --- a/drivers/clk/mediatek/clk-fhctl.h +++ b/drivers/clk/mediatek/clk-fhctl.h @@ -7,6 +7,13 @@ #ifndef __CLK_FHCTL_H #define __CLK_FHCTL_H =20 +#include "clk-pllfh.h" + +enum fhctl_variant { + FHCTL_PLLFH_V1, + FHCTL_PLLFH_V2, +}; + struct fhctl_offset { u32 offset_hp_en; u32 offset_clk_con; @@ -19,7 +26,7 @@ struct fhctl_offset { u32 offset_dvfs; u32 offset_mon; }; -const struct fhctl_offset *fhctl_get_offset_table(void); +const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v); const struct fh_operation *fhctl_get_ops(void); void fhctl_hw_init(struct mtk_fh *fh); =20 diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8186-apmixedsys.c index 1d673c6278a9..9fded5020ca4 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -7,6 +7,7 @@ #include #include =20 +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" #include "clk-pllfh.h" @@ -98,6 +99,7 @@ enum fh_pll_id { .data =3D { \ .pll_id =3D _pllid, \ .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ .fhx_offset =3D _offset, \ .dds_mask =3D GENMASK(21, 0), \ .slope0_value =3D 0x6003c97, \ diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index f48780bec507..b9297726f5a0 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -104,14 +104,16 @@ void fhctl_parse_dt(const u8 *compatible_node, struct= mtk_pllfh_data *pllfhs, } } =20 -static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_dat= a) +static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) { struct fh_pll_regs *regs =3D &fh->regs; const struct fhctl_offset *offset; void __iomem *base =3D pllfh_data->state.base; void __iomem *fhx_base =3D base + pllfh_data->data.fhx_offset; =20 - offset =3D fhctl_get_offset_table(); + offset =3D fhctl_get_offset_table(pllfh_data->data.fh_ver); + if (IS_ERR(offset)) + return PTR_ERR(offset); =20 regs->reg_hp_en =3D base + offset->offset_hp_en; regs->reg_clk_con =3D base + offset->offset_clk_con; @@ -129,6 +131,8 @@ static void pllfh_init(struct mtk_fh *fh, struct mtk_pl= lfh_data *pllfh_data) fh->lock =3D &pllfh_lock; =20 fh->ops =3D fhctl_get_ops(); + + return 0; } =20 static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pl= lfh) @@ -142,20 +146,29 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll= _data, { struct clk_hw *hw; struct mtk_fh *fh; + int ret; =20 fh =3D kzalloc(sizeof(*fh), GFP_KERNEL); if (!fh) return ERR_PTR(-ENOMEM); =20 - pllfh_init(fh, pllfh_data); + ret =3D pllfh_init(fh, pllfh_data); + if (ret) { + hw =3D ERR_PTR(ret); + goto out; + } =20 hw =3D mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, &mtk_pllfh_ops); =20 + if (IS_ERR(hw)) + goto out; + + fhctl_hw_init(fh); + +out: if (IS_ERR(hw)) kfree(fh); - else - fhctl_hw_init(fh); =20 return hw; } diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pl= lfh.h index c0a6e1537034..5f419c2ec01f 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -18,6 +18,7 @@ struct fh_pll_state { struct fh_pll_data { int pll_id; int fh_id; + int fh_ver; u32 fhx_offset; u32 dds_mask; u32 slope0_value; --=20 2.39.1 From nobody Wed Nov 13 07:17:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 059F7C05027 for ; Mon, 6 Feb 2023 10:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230070AbjBFKBz (ORCPT ); Mon, 6 Feb 2023 05:01:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230093AbjBFKBW (ORCPT ); Mon, 6 Feb 2023 05:01:22 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 238D71EFEE; Mon, 6 Feb 2023 02:01:18 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9E5F86602FAE; Mon, 6 Feb 2023 10:01:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675677677; bh=SUI34CS1BrJFmIaipPdxWm70cNWYkj8EhbTlIi7RZKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iRYJBOAsI4wIgnf2YkdFZADBhOfijn33uRNwDyexhlxJw7+ZfNe4ELRmzUAGiAckl x/5869CPo/hg5dgqSijs1I2ggAIs1xzVw97/Ta/2FmLhYpWBzDkLm2aLXXi2iqrNi8 csLUh+PB04G8Sg+0QfPGcgsd8GfSIyFlGfbH/Musk+0tLQNjYmLtFTlzjmfN4KWOuT TAx02L1Wv/C2eGZSfktGALCo/K130v25tUNyMHpxp99NiJwuMKRiOQwPWXeKRdtjzd ouiYnuvCsyaeoQMPPlajdcNHgUqcRxOjXEJQkKW4Nodhd72AXt1O6lASdZl8/iVno5 Aii5GC4Cq85Hw== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 2/7] clk: mediatek: clk-pllfh: Export register/unregister/parse functions Date: Mon, 6 Feb 2023 11:01:00 +0100 Message-Id: <20230206100105.861720-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> References: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These functions are used by the various MediaTek apmixed clock drivers that may be built as modules: export the common functions used to parse related devicetree properties, register and unregister the PLLFH clocks. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-pllfh.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pl= lfh.c index b9297726f5a0..7b6e051443f4 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -103,6 +103,7 @@ void fhctl_parse_dt(const u8 *compatible_node, struct m= tk_pllfh_data *pllfhs, pllfh->state.base =3D base; } } +EXPORT_SYMBOL_GPL(fhctl_parse_dt); =20 static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) { @@ -247,6 +248,7 @@ int mtk_clk_register_pllfhs(struct device_node *node, =20 return PTR_ERR(hw); } +EXPORT_SYMBOL_GPL(mtk_clk_register_pllfhs); =20 void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_pl= ls, struct mtk_pllfh_data *pllfhs, int num_fhs, @@ -286,3 +288,4 @@ void mtk_clk_unregister_pllfhs(const struct mtk_pll_dat= a *plls, int num_plls, =20 iounmap(base); } +EXPORT_SYMBOL_GPL(mtk_clk_unregister_pllfhs); --=20 2.39.1 From nobody Wed Nov 13 07:17:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1EB5C64EC5 for ; Mon, 6 Feb 2023 10:01:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229661AbjBFKBl (ORCPT ); Mon, 6 Feb 2023 05:01:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230087AbjBFKBV (ORCPT ); Mon, 6 Feb 2023 05:01:21 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23CA41F487; Mon, 6 Feb 2023 02:01:19 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A6ABA6602FA0; Mon, 6 Feb 2023 10:01:17 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675677678; bh=u7Y8n/T80FWNXiD40Mx6s06d8MGoJpyrDLmIqXuDbtM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HbO+scaczhc4zrIb+JeSoZxSJKgzEGwFlMZVTp5fkRD8QgTGlHdx6c75PhiooPdcN 5NZXcb5/yQawZjTfupEUvKMlflUiYTvC+aV7zXs441xF7s+OSQVGqaPpn+6PYXyRdF dei+PIFgU1UkGnU0YAKrVr38VzhnkaVcuyapDP/yMYhxEueH2q5QAPJneE+gXXjj6y X03gAD61BZup9byr8GUJJcnz8dLep2xSHjpHOUrv701ff+H3NWECBDroEG4Uw+Ip6X 5XPLMeHA8wlNZIt9HS64jF/BIgvXQM0Bz2pq0VCTePA4FQUSMtCHpdNnrLETUN/UxY l2wn26x2rZJLg== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 3/7] dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795, MT8173/92/95 Date: Mon, 6 Feb 2023 11:01:01 +0100 Message-Id: <20230206100105.861720-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> References: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MT6795, MT8173, MT8192 and MT8195 support Frequency Hopping: add the compatibles for them. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Reviewed-by: Chen-Yu Tsai --- .../devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.= yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml index cfd042ac1e14..d00327d12e1e 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml @@ -16,7 +16,12 @@ description: | =20 properties: compatible: - const: mediatek,mt8186-fhctl + enum: + - mediatek,mt6795-fhctl + - mediatek,mt8173-fhctl + - mediatek,mt8186-fhctl + - mediatek,mt8192-fhctl + - mediatek,mt8195-fhctl =20 reg: maxItems: 1 --=20 2.39.1 From nobody Wed Nov 13 07:17:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45890C61DA4 for ; Mon, 6 Feb 2023 10:02:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229577AbjBFKCM (ORCPT ); Mon, 6 Feb 2023 05:02:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230034AbjBFKBX (ORCPT ); Mon, 6 Feb 2023 05:01:23 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7B797AB5; Mon, 6 Feb 2023 02:01:20 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B20726602FD2; Mon, 6 Feb 2023 10:01:18 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675677679; bh=itE4eZMJemdRprpa0Uu/b/CoO8oJbwlvvA8SntoU+ms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E2sEzKgKi0MkkbK3EExzgt8lOpClv9E2HO3PrS7AgNDymvkA6yRMluUQN2TQ916l1 BERfyl7sHBPn6v6SwQmo8K7Qv0PcHTBaL4c2dnpAwBelBBvb0Gao2fyxc5QmoVatYj qdAG9lzbLB94NS+krbITDDuRLKjJWEb+DseDGzTs2KC9TkCZEwK9hPYPMN4rSMs6A5 ubGFwtZJ9LHb64rAXLgvhMBnFwBdMQTZ25gxP44o075u9YZBKvfTgsJxChji8m6WUD cjtnAGsRLdJ3YrO2LFeaLJAuF6fof1OjI7ITJTNJj/1bayEOnF/9LGq8HmFSXyXGqE W7Fvca9jUAuHA== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 4/7] clk: mediatek: mt6795: Add support for frequency hopping through FHCTL Date: Mon, 6 Feb 2023 11:01:02 +0100 Message-Id: <20230206100105.861720-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> References: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 63 +++++++++++++++++++- 1 file changed, 60 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6795-apmixedsys.c index 59761c72d3bc..03fa30527868 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -7,8 +7,10 @@ #include #include #include +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #define REG_REF2USB 0x8 #define REG_AP_PLL_CON7 0x1c @@ -58,6 +60,56 @@ static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, = 0x2b8, 0), }; =20 +enum fh_pll_id { + FH_CA53PLL_LL, + FH_CA53PLL_BL, + FH_MAINPLL, + FH_MPLL, + FH_MSDCPLL, + FH_MMPLL, + FH_VENCPLL, + FH_TVDPLL, + FH_VCODECPLL, + FH_NR_FH, +}; + +#define _FH(_pllid, _fhid, _slope, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V1, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D _slope, \ + .slope1_value =3D _slope, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +#define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) +#define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ARMCA53PLL, FH_CA53PLL_BL, 0x38), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60), + FH_M(CLK_APMIXED_MPLL, FH_MPLL, 0x74), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c), + FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4), + FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8), +}; + static void clk_mt6795_apmixed_setup_md1(void __iomem *base) { void __iomem *reg =3D base + REG_AP_PLL_CON7; @@ -85,6 +137,7 @@ static int clk_mt6795_apmixed_probe(struct platform_devi= ce *pdev) struct clk_hw_onecell_data *clk_data; struct device *dev =3D &pdev->dev; struct device_node *node =3D dev->of_node; + const u8 *fhctl_node =3D "mediatek,mt6795-fhctl"; void __iomem *base; struct clk_hw *hw; int ret; @@ -97,7 +150,9 @@ static int clk_mt6795_apmixed_probe(struct platform_devi= ce *pdev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + ret =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (ret) goto free_clk_data; =20 @@ -124,7 +179,8 @@ static int clk_mt6795_apmixed_probe(struct platform_dev= ice *pdev) unregister_ref2usb: mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return ret; @@ -137,7 +193,8 @@ static int clk_mt6795_apmixed_remove(struct platform_de= vice *pdev) =20 of_clk_del_provider(node); mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); =20 return 0; --=20 2.39.1 From nobody Wed Nov 13 07:17:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDEB1C05027 for ; Mon, 6 Feb 2023 10:02:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230164AbjBFKCj (ORCPT ); Mon, 6 Feb 2023 05:02:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230088AbjBFKBY (ORCPT ); Mon, 6 Feb 2023 05:01:24 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7ADAC662; Mon, 6 Feb 2023 02:01:22 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BC32B6602FFB; Mon, 6 Feb 2023 10:01:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675677680; bh=O9l7AXT6I2WTwPtME3QSuSOtjzvUE4GewDtvfo0rC5s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MrcMxF94FOzJ2hE8UwccKvTxhsblh8EV7Q1Out1MFm2ZqKPYJvZdHLQpnZz/cp3q9 oZmVCj7I+6D9G9Q/ltnHN/Z2U33SQ/taFfoJfCYqrbrOFhUbV5ArhWu0RZX3uBesLO SmL1e0MOSkVBMmotPWXDVoWAZuJt4AuB3lSbbpJNyXmzPy8F8ln0LDzEZMP+GCOlCt Idrw+NILqUibNSDyV2T9KEUopKcJz2baysaPP7YjgiXBYwqU0HjfMWc77wTOn1YAFD 0skqzH+FFOnrBJcXwzt7ILDC1GEpbyWbc2rpdlKNKefcOGwrYskNxKO6e1DpsYXjvj m4o8ZYd1tO9MA== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 5/7] clk: mediatek: mt8173: Add support for frequency hopping through FHCTL Date: Mon, 6 Feb 2023 11:01:03 +0100 Message-Id: <20230206100105.861720-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> References: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 65 +++++++++++++++++++- 1 file changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8173-apmixedsys.c index a56c5845d07a..0084203e67ad 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -9,8 +9,10 @@ #include #include #include +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #define REGOFF_REF2USB 0x8 #define REGOFF_HDMI_REF 0x40 @@ -77,6 +79,58 @@ static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0= x0, 0x2f4, 0), }; =20 +enum fh_pll_id { + FH_ARMCA7PLL, + FH_ARMCA15PLL, + FH_MAINPLL, + FH_MPLL, + FH_MSDCPLL, + FH_MMPLL, + FH_VENCPLL, + FH_TVDPLL, + FH_VCODECPLL, + FH_LVDSPLL, + FH_MSDC2PLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V1, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38), + FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60), + FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c), + FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4), + FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8), + FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec), + FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100), +}; + static const struct of_device_id of_match_clk_mt8173_apmixed[] =3D { { .compatible =3D "mediatek,mt8173-apmixedsys" }, { /* sentinel */ } @@ -84,6 +138,7 @@ static const struct of_device_id of_match_clk_mt8173_apm= ixed[] =3D { =20 static int clk_mt8173_apmixed_probe(struct platform_device *pdev) { + const u8 *fhctl_node =3D "mediatek,mt8173-fhctl"; struct device_node *node =3D pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; void __iomem *base; @@ -98,7 +153,9 @@ static int clk_mt8173_apmixed_probe(struct platform_devi= ce *pdev) if (IS_ERR_OR_NULL(clk_data)) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_clk_data; =20 @@ -124,7 +181,8 @@ static int clk_mt8173_apmixed_probe(struct platform_dev= ice *pdev) unregister_ref2usb: mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r; @@ -137,7 +195,8 @@ static int clk_mt8173_apmixed_remove(struct platform_de= vice *pdev) =20 of_clk_del_provider(node); mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); =20 return 0; --=20 2.39.1 From nobody Wed Nov 13 07:17:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30E8EC05027 for ; Mon, 6 Feb 2023 10:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230168AbjBFKCp (ORCPT ); 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b=Gqa/WXXJP901ofoih3gid+jeAh+DzxDIPqfukijcH/Qvcg9QDAc2z+NIb64jfz/Gg 5ndPzk0BeFWqkGktkTeC9uEUCW81WRj6ma6J08+BPJPZ0OCS1J+V9Ulmit6uOH9jvq ge7QxMiJy4g5hchU5K1AwIOEdRWqAeat96gMUdJHAx28hWiczx198ADD242Vfaj4C+ SylNINACbmFGg2WW60NoostUoJQv89lG6/Rg/Ix97QS13E5WEq0ZxAJfHQZHVkIXrB Wng2T/KT4NHcYEnR2H9Qnya4eOErcECXmwm+FK0JvrSPtR42rD7AHp4Bmj6rNNxGsh UWoYtPlANJvqw== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 6/7] clk: mediatek: mt8192: Add support for frequency hopping through FHCTL Date: Mon, 6 Feb 2023 11:01:04 +0100 Message-Id: <20230206100105.861720-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> References: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8192.c | 67 ++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 61299960d28a..0f9f10172148 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -12,10 +12,12 @@ #include #include =20 +#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #include #include @@ -1042,6 +1044,57 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), }; =20 +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL0, + FH_ARMPLL_BL1, + FH_ARMPLL_BL2, + FH_ARMPLL_BL3, + FH_CCIPLL, + FH_MFGPLL, + FH_MEMPLL, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_ADSPPLL, + FH_APUPLL, + FH_TVDPLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), +}; + /* Register mux notifier for MFG mux */ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) { @@ -1068,17 +1121,24 @@ static int clk_mt8192_apmixed_probe(struct platform= _device *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node =3D pdev->dev.of_node; + const u8 *fhctl_node =3D "mediatek,mt8192-fhctl"; int r; =20 clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; =20 - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); + if (r) + goto free_clk_data; + r =3D mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); if (r) - goto free_clk_data; + goto unregister_plls; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -1088,6 +1148,9 @@ static int clk_mt8192_apmixed_probe(struct platform_d= evice *pdev) =20 unregister_gates: mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); +unregister_plls: + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r; --=20 2.39.1 From nobody Wed Nov 13 07:17:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98D23C05027 for ; Mon, 6 Feb 2023 10:02:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229718AbjBFKCc (ORCPT ); Mon, 6 Feb 2023 05:02:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230102AbjBFKBZ (ORCPT ); Mon, 6 Feb 2023 05:01:25 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2DEE1353F; Mon, 6 Feb 2023 02:01:23 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D4967660302F; Mon, 6 Feb 2023 10:01:21 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675677682; bh=Obi+vQT5xnaobAxtXIDP6ufWD0ahrxBt2y0sg2Yn4lw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PS6kLO5BoOHCEh7QCx7k5NBBfdXTqFo0TCWhCsb19kjBClbMiS2KQYSeigzDbmqGR UT4yCtLQnDY32M64hpAP3otBPkJd2X5HHQzUeS4fkctwppbm2rBmGYGDkR9g82rcS5 SLgYXwC3fa8zNc/19L+ELDqwVNaGk6Az9NFc9rLvdRW6eQUDZjnftwCzAFA9NLW2qz Yxn8Xvw0dMff2E9MdLN2uaYZZZrGMiD82SHkFca+sruLMC2/ceQdUqrYlwGQzwU6xa 1XXt2TXVR8mtZN6CbcQhC1aNHMpDYTY6cPsKInPvft4iJFQ6oVMmRFBFNIO8MsqbEs kF37EFB3kzwfQ== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v3 7/7] clk: mediatek: mt8195: Add support for frequency hopping through FHCTL Date: Mon, 6 Feb 2023 11:01:05 +0100 Message-Id: <20230206100105.861720-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> References: <20230206100105.861720-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++- 1 file changed, 66 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index 1bc917f2667e..c0db31ce0741 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -3,9 +3,11 @@ // Copyright (c) 2021 MediaTek Inc. // Author: Chun-Jie Chen =20 +#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" =20 #include #include @@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9), }; =20 +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL, + FH_MEMPLL, + FH_ADSPPLL, + FH_NNAPLL, + FH_CCIPLL, + FH_MFGPLL, + FH_TVDPLL2, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_IMGPLL, + FH_VDECPLL, + FH_TVDPLL1, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data =3D { \ + .pll_id =3D _pllid, \ + .fh_id =3D _fhid, \ + .fh_ver =3D FHCTL_PLLFH_V2, \ + .fhx_offset =3D _offset, \ + .dds_mask =3D GENMASK(21, 0), \ + .slope0_value =3D 0x6003c97, \ + .slope1_value =3D 0x6003c97, \ + .sfstrx_en =3D BIT(2), \ + .frddsx_en =3D BIT(1), \ + .fhctlx_en =3D BIT(0), \ + .tgl_org =3D BIT(31), \ + .dvfs_tri =3D BIT(31), \ + .pcwchg =3D BIT(31), \ + .dt_val =3D 0x0, \ + .df_val =3D 0x9, \ + .updnlmt_shft =3D 16, \ + .msk_frddsx_dys =3D GENMASK(23, 20), \ + .msk_frddsx_dts =3D GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] =3D { + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78), + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c), + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c), + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154), +}; + static const struct of_device_id of_match_clk_mt8195_apmixed[] =3D { { .compatible =3D "mediatek,mt8195-apmixedsys", }, {} @@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_d= evice *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node =3D pdev->dev.of_node; + const u8 *fhctl_node =3D "mediatek,mt8195-fhctl"; int r; =20 clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r =3D mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; =20 @@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_dev= ice *pdev) unregister_gates: mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_apmixed_data: mtk_free_clk_data(clk_data); return r; @@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_de= vice *pdev) =20 of_clk_del_provider(node); mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); =20 return 0; --=20 2.39.1