From nobody Wed Feb 11 03:24:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0691C74A5B for ; Fri, 17 Mar 2023 09:13:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231359AbjCQJNO (ORCPT ); Fri, 17 Mar 2023 05:13:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230141AbjCQJNA (ORCPT ); Fri, 17 Mar 2023 05:13:00 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40C812BF34 for ; Fri, 17 Mar 2023 02:12:56 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id r29so3752638wra.13 for ; Fri, 17 Mar 2023 02:12:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679044374; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=jy9Gq9StQdq060iKXKxV7Ee3X06YY4EYtIafip1P6OE=; b=yybmrdoIoTHCR6O3L9hSPD5WZJ3vnaCZV+MIEHRbZ1W6O/KByW9SxGP21FKXu6OI/g vedoFay4HWhnOhIJjMcw+yF3gwv3qyrGCkJBnr9B+P6+frWirokswGctgkH1POTACWoO f1GRpbIPjRuXCXlRsEgHQ4lJBppNyGW2e+BS7X8iXT0N71BlUFTKgeglDTMp0M4dbzwd UtnonkzrFYxsnCquWa5LP1MWjXDbjt4tU4Ik5iXtXJ7vsPHeLIwsVGh0Bs9vHxbqYmyH fRU1knuv6QlfQsm1QNvvlXRTTZkS/BX1MpNu84KyPBel6se+VgJkH6rG7Zd5UPsclF6f XQpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679044374; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jy9Gq9StQdq060iKXKxV7Ee3X06YY4EYtIafip1P6OE=; b=kNSrksoVCgLKlhdvONhWivEwfxN9gAhFoDyxGI+2UMWBkFNclW4xG3H/jENdYSnIEu 3S1eaRzjUUA8p7t4UxkzJY2xXOpldOIAN3uVqns2Nl+Tq+gfLxP6tmafkv1oa3E6ljTq yY1TRYLE0bAMG3vsKb1NYuWeWwZrzxJoiXo5uQCb/fX8M78K4g9Dygx5IokTBt6/Olh1 ssVIAzVc5++WJ/Xaw1Pf/yTV49j80V/9WgoPLePQnblSWGzSAXP/WuDW8no/mecl1siJ tcR/XehnW0dcHNE+bgisepWo3j9w5s4iugi86A8m7LiwLtACHZVQnqUosNnYAxqUXZqD QDGw== X-Gm-Message-State: AO0yUKVXQaMdT4uEpKRsgB9LCwHfEtogFadrfIOIvsfuktuqnoUOy9Th PC7y8ulwo17NvMIFlEzTlNzFIA== X-Google-Smtp-Source: AK7set95vlWcFVN4Fm6dxfm5n4uUbaGDxexR9zizYcucScXRixx+u6Frar/5JNOraZBbCVbJSdmNxQ== X-Received: by 2002:adf:f605:0:b0:2cf:e449:1a9e with SMTP id t5-20020adff605000000b002cfe4491a9emr1747052wrp.30.1679044374779; Fri, 17 Mar 2023 02:12:54 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id j10-20020a5d464a000000b002cea8f07813sm1467976wrs.81.2023.03.17.02.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 02:12:54 -0700 (PDT) From: Neil Armstrong Date: Fri, 17 Mar 2023 10:12:51 +0100 Subject: [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230206-topic-sm8450-upstream-dp-controller-v5-5-a27f1b26ebe8@linaro.org> References: <20230206-topic-sm8450-upstream-dp-controller-v5-0-a27f1b26ebe8@linaro.org> In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v5-0-a27f1b26ebe8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the Display Port controller subnode to the MDSS node. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 79 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 0b5a151ce138..41f5015e615b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint { }; }; =20 + port@2 { + reg =3D <2>; + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + }; =20 mdp_opp_table: opp-table { @@ -2783,6 +2790,78 @@ opp-500000000 { }; }; =20 + mdss_dp0: displayport-controller@ae90000 { + compatible =3D "qcom,sm8450-dp", "qcom,sm8350-dp"; + reg =3D <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents =3D <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys =3D <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SM8450_MMCX>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible =3D "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg =3D <0 0x0ae94000 0 0x400>; --=20 2.34.1