From nobody Sat Sep 13 02:10:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBD83C61DA4 for ; Mon, 6 Feb 2023 10:17:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230309AbjBFKRi (ORCPT ); Mon, 6 Feb 2023 05:17:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230252AbjBFKRZ (ORCPT ); Mon, 6 Feb 2023 05:17:25 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5292116AE5 for ; Mon, 6 Feb 2023 02:17:11 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id bh13-20020a05600c3d0d00b003dff6cd8b7eso3111449wmb.5 for ; Mon, 06 Feb 2023 02:17:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xxHXOpufaFaK69tlU0lBmq/fhKzZKgu1EiJW7yQ+PNo=; b=HSSTHcYzQO3wNiH05mSAVVu5JkYtD5lZcmYvFPgTdEUa+2BKIh4oYukbuhR6NIvKyb urQzDH+NZHgQ2OzFCMZqahRg+ytRQofuqwrENqM6LP7+FhObO3Igavjb0ZFvk7r9UWCk 8B8w6uNAileZxV8ywbcbw8abKg4FYfOXdcaM3pLpVg4rJs5pZkTgqes794V9VoruZSnR OIunKYmdeTUcZVQVpOWWyEBnJB4eEIefmb23qaZrfdRJd5v5FZR8wmwMLU9yioFIhDIq IP1BAPqSVcn23jhTQLVUecvO4560biMEWXcdg3FqI86r17ys/MESAZmML3ivOnqU/0Wv ZyDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xxHXOpufaFaK69tlU0lBmq/fhKzZKgu1EiJW7yQ+PNo=; b=Y25MU4p2lzv/cBQQazed4voLJcJz6qh3rnSFoLseJ9k/s6HgzyCbrxnti166qyUlRT a2eK8ny3ypGSsfqANLvFW2cqpv9lQAfURB8V0B0TmbxATBiuHoY7Lgi6rV1QZoRqJImP i0/pQe9+fv9B8RMyqJdUg761ZOr6VF55KstZ+2CaGwmA93rpnDEiE7IuiRgK58O16px3 MnR8uD7YZT7xlj2f8N4mCzCQLX+JRXE6ApAsfH5HVY9L76duiEIvH67ihtjAwEC8pucW MEE3THIWzsBQO7ats4JG5gqP74vy1QmFWWc0trNDlCRvAP8S2Ar3kNt3IFBDhvLd5Eib vR+w== X-Gm-Message-State: AO0yUKVlxuLmzCrIXQaHfFAASIig8DmcwB98LITiBvoEXpIBbbx/a6bs 87gz6oarhCglLUgQ2EMrdrtz+w== X-Google-Smtp-Source: AK7set+ZNux4+DZLpYsN4jJN72b/mfmMES1nLuAaxTfOCwfe4bppMiVSD5rf6vfeBO4hxbhPLw6L/g== X-Received: by 2002:a05:600c:601b:b0:3dd:1b76:347f with SMTP id az27-20020a05600c601b00b003dd1b76347fmr18520898wmb.18.1675678629847; Mon, 06 Feb 2023 02:17:09 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id w15-20020a05600c474f00b003db0bb81b6asm11314201wmo.1.2023.02.06.02.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 02:17:09 -0800 (PST) From: Neil Armstrong Date: Mon, 06 Feb 2023 11:17:06 +0100 Subject: [PATCH 3/5] arm64: dts: qcom: sm8350: add dp controller MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230206-topic-sm8450-upstream-dp-controller-v1-3-f1345872ed19@linaro.org> References: <20230206-topic-sm8450-upstream-dp-controller-v1-0-f1345872ed19@linaro.org> In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v1-0-f1345872ed19@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the Display Port controller subnode to the MDSS node. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 80 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 78 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 2586321af6df..9d7084934d99 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2865,13 +2865,20 @@ ports { =20 port@0 { reg =3D <0>; - dpu_intf1_out: endpoint { - remote-endpoint =3D <&mdss_dsi0_in>; + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp_in>; }; }; =20 port@1 { reg =3D <1>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@2 { + reg =3D <2>; dpu_intf2_out: endpoint { remote-endpoint =3D <&mdss_dsi1_in>; }; @@ -2879,6 +2886,75 @@ dpu_intf2_out: endpoint { }; }; =20 + mdss_dp: displayport-controller@ae90000 { + compatible =3D "qcom,sm8350-dp"; + reg =3D <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>; + interrupt-parent =3D <&mdss>; + interrupts =3D <12>; + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names =3D "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents =3D <&usb_1_qmpphy 1>, + <&usb_1_qmpphy 2>; + + phys =3D <&usb_1_qmpphy 1>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dp_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-160000000 { + opp-hz =3D /bits/ 64 <160000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible =3D "qcom,mdss-dsi-ctrl"; reg =3D <0 0x0ae94000 0 0x400>; --=20 2.34.1