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Signed-off-by: Neil Armstrong Acked-by: Rob Herring --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | = 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml index 0764cd977e76..52ab7174df85 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml @@ -18,6 +18,8 @@ properties: enum: - qcom,sc8280xp-qmp-usb43dp-phy - qcom,sm6350-qmp-usb3-dp-phy + - qcom,sm8350-qmp-usb3-dp-phy + - qcom,sm8450-qmp-usb3-dp-phy =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sat Sep 13 00:26:53 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFBECC636D6 for ; Mon, 6 Feb 2023 09:59:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230148AbjBFJ7O (ORCPT ); Mon, 6 Feb 2023 04:59:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230082AbjBFJ7E (ORCPT ); Mon, 6 Feb 2023 04:59:04 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA779EC8 for ; Mon, 6 Feb 2023 01:59:03 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id g6so1812214wrv.1 for ; Mon, 06 Feb 2023 01:59:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pc8EGLVDXGbdb5xspq+QC/9/pxt7xL4kJWnSCzdVJ04=; b=GD7kx/836uwB6GxotWhJQ8KSA1wRHTGGXCuP45KgpZGfCpOlP0xUcPseofZ4wBQwP9 68u05G5ohyEjSSQLTYoubHgRcZ9hQNj1JcQ+/cnf2hWK2Rho/VCoCqzxJJJJ4pENlFt0 y3UOwxqpRwiZPQJmG6Kb2iyDr6mw/i3H3wshdeulJcQV0dqzH3wYzdwC/9tudQBdrhAC gK/uvBcCSVywa8o40gcED/gVfzE3GDideySojlojk9NV4pN8831IR91v+djozvarM2qb HpAWfbg/i+hekLHX2jR7rst8AiwInqvkKlmA4JsY6pYuwLGg9jqYCosx+jlZClZ0LmN+ XDsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pc8EGLVDXGbdb5xspq+QC/9/pxt7xL4kJWnSCzdVJ04=; b=lJojU7+oQ/R1GfW593DDPdFGG4arXasc2zT5qKDVFgZYm9xIeYfBkdd+ryWreb28UU buh4ZnYJUBpthFBETWIgXFvogbQrOFSAs1A4Eh5OawFAE56+2RRjybh1qVayMVXXxD4o +lARJNN89XHPCOpqchDBfdC5eZP5dXPJuMa4WWYrq3XCgrUM8hk6me2yqtZC4GAHmjYR 2iFp1GgjyY8YZQgOCt0hsb04q7KTj7Xnc9Aw3TE6BgjGK4b7+8L4Mx8r7ezv5v+x/JIi 7MHKmLbA59D8MAIKKfbT5NCN+SU3dXex12Xfdm2cNuJVL3x2BikOvyXs+sZ3ybLATaNc AXLA== X-Gm-Message-State: AO0yUKVPiX9lP4mn4oOBRGKTgt2Mlyc9AfrpI2lwoA+ccbz9I2f2mKeB xiUOmBOsEugprdXnMnpe1Sl9mzO5etfOrS14e2Q= X-Google-Smtp-Source: AK7set/cj9DHV1m3E22XCLi57cGyxC5BMsJz9bzv0IOGJt1EUcOyKO64ewF4BnS+PMaf0Ll5s4WbqQ== X-Received: by 2002:a05:6000:16c4:b0:2bf:da72:d2d1 with SMTP id h4-20020a05600016c400b002bfda72d2d1mr9688588wrf.48.1675677541545; Mon, 06 Feb 2023 01:59:01 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id i14-20020a0560001ace00b002bfb8f829eesm8839304wry.71.2023.02.06.01.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 01:59:01 -0800 (PST) From: Neil Armstrong Date: Mon, 06 Feb 2023 10:58:57 +0100 Subject: [PATCH 2/2] phy: qcom: com-qmp-combo: add SM8350 & SM8450 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-2-ed849ae6b849@linaro.org> References: <20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-0-ed849ae6b849@linaro.org> In-Reply-To: <20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-0-ed849ae6b849@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Copy the USB tables from the QMP USB3 PHY driver and add the missing DP tables from downstream to enable USB3/DP on the SM8350 and SM8450 platforms. Signed-off-by: Neil Armstrong --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 170 ++++++++++++++++++++++++++= ++++ 1 file changed, 170 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 82b46f4c6df0..9982269b2cd9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -556,6 +556,84 @@ static const struct qmp_phy_init_tbl sm8250_usb3_pcs_u= sb_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), }; =20 +static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), +}; + +static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), +}; + static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), @@ -662,6 +740,20 @@ static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_= tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), }; =20 +static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), +}; + static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), @@ -830,6 +922,27 @@ static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = =3D { { 0x1f, 0xff, 0xff, 0xff } }; =20 +static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] =3D { + { 0x00, 0x0c, 0x15, 0x1b }, + { 0x02, 0x0e, 0x16, 0xff }, + { 0x02, 0x11, 0xff, 0xff }, + { 0x04, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] =3D { + { 0x00, 0x0d, 0x14, 0x1a }, + { 0x00, 0x0e, 0x15, 0xff }, + { 0x00, 0x0d, 0xff, 0xff }, + { 0x03, 0xff, 0xff, 0xff } +}; + +static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] =3D { + { 0x08, 0x0f, 0x16, 0x1f }, + { 0x11, 0x1e, 0x1f, 0xff }, + { 0x16, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] =3D { { 0x20, 0x2c, 0x35, 0x3b }, { 0x22, 0x2e, 0x36, 0xff }, @@ -1344,6 +1457,55 @@ static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg= =3D { .has_pwrdn_delay =3D true, }; =20 +static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg =3D { + .offsets =3D &qmp_combo_offsets_v3, + + .serdes_tbl =3D sm8150_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sm8150_usb3_serdes_tbl), + .tx_tbl =3D sm8350_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_usb3_tx_tbl), + .rx_tbl =3D sm8350_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_usb3_rx_tbl), + .pcs_tbl =3D sm8350_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_usb3_pcs_tbl), + .pcs_usb_tbl =3D sm8350_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), + + .dp_serdes_tbl =3D qmp_v4_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v4_dp_serdes_tbl), + .dp_tx_tbl =3D qmp_v5_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v5_dp_tx_tbl), + + .serdes_tbl_rbr =3D qmp_v4_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v4_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v4_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v4_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), + + .swing_hbr_rbr =3D &qmp_dp_v4_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr =3D &qmp_dp_v4_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 =3D &qmp_dp_v3_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 =3D &qmp_dp_v4_pre_emphasis_hbr3_hbr2, + + .dp_aux_init =3D qmp_v4_dp_aux_init, + .configure_dp_tx =3D qmp_v4_configure_dp_tx, + .configure_dp_phy =3D qmp_v4_configure_dp_phy, + .calibrate_dp_phy =3D qmp_v4_calibrate_dp_phy, + + .clk_list =3D qmp_v4_phy_clk_l, + .num_clks =3D ARRAY_SIZE(qmp_v4_phy_clk_l), + .reset_list =3D msm8996_usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D qmp_v4_usb3phy_regs_layout, + + .has_pwrdn_delay =3D true, +}; + static void qmp_combo_configure_lane(void __iomem *base, const struct qmp_phy_init_tbl tbl[], int num, @@ -2926,6 +3088,14 @@ static const struct of_device_id qmp_combo_of_match_= table[] =3D { .compatible =3D "qcom,sm8250-qmp-usb3-dp-phy", .data =3D &sm8250_usb3dpphy_cfg, }, + { + .compatible =3D "qcom,sm8350-qmp-usb3-dp-phy", + .data =3D &sm8350_usb3dpphy_cfg, + }, + { + .compatible =3D "qcom,sm8450-qmp-usb3-dp-phy", + .data =3D &sm8350_usb3dpphy_cfg, + }, { } }; MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); --=20 2.34.1