From nobody Sat Feb 7 07:10:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CA57C636CC for ; Fri, 3 Feb 2023 08:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232888AbjBCITQ (ORCPT ); Fri, 3 Feb 2023 03:19:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232634AbjBCISf (ORCPT ); Fri, 3 Feb 2023 03:18:35 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69C462B0A0 for ; Fri, 3 Feb 2023 00:18:23 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id q8so3232244wmo.5 for ; Fri, 03 Feb 2023 00:18:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LLtvpmHwMM7vzi6V1fFQQBR0Kdo0pG7gbVXAAYyBGys=; b=GvchRDuKUFGBOTMDqi67GFuWZ63nj6po8KKo0ZEmQilY7KaEJ3qwDMHsN5210+Xr4g W/Z6w41KDrJimFvRW99hHQdco8FeBxwG5yjwJwHKf54EzH2IijjrE6S649JWvis+wN+C 9MIQe6SNcaJ0J4+1l8lxClYQ5Mtkjh3V6AgeIpfvgMzJh7SweY2acnyHrbEgADaZHmMg L8E+z84v/kEIIiwjTAGK8E4CBnigrr/HsBqR7AZ4kTHKouVQYBnJOVyXGK2u8rVUPr4s UxIAHs6LoGz+DFzovwQDuDfDqJyS0J79Et53cUS0+VNKBFhj01HWqT/eTpnSNVYjDGWF Te0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LLtvpmHwMM7vzi6V1fFQQBR0Kdo0pG7gbVXAAYyBGys=; b=KPyOR+RR5y+Y9m/zNwNQJwZ/TX6K4KJQuoSC1MUrhVZEGwMe1jKNmJNZbpHr1XC2DT jvDWNoBcERagHtJBF8ropixbhUsOLEqsk/VIg/zmY1hypvMowzUf5E7SrpQnOxOsDSlG Tq9L3gFoW1KnRXq0c07K1wvheGWFnXK60/XUs1BaZxCYfmmcF9qHx/2aeg2oRK1DYpiq E7IJOJwOEiAsKxKwRu71gSoCOpN7GaJKMiabgqCyzZ5jdQ+6tbBE3hOOGDtbYP1231NE xs9T97Vrp+33uZCT3LHU67G1ReSl6u1iLFPV2ajqVfBJIWPoCpQa23FFWb9Epdl+X7fI ItOQ== X-Gm-Message-State: AO0yUKWby298Aka2s5I4YdmmMrrazxFCnAvPCc7509G7W2SOF0zF5jM3 qI8WCHTd7yRkDngLTgr1CrrrQA== X-Google-Smtp-Source: AK7set/dvS+eO7q45f+v03LWORmgkNosCCZHFS6mdV2ORGjJaii1cn8+i9aMMMWRfVOmWV31P5K+Yw== X-Received: by 2002:a05:600c:4e53:b0:3df:eb5d:fbf with SMTP id e19-20020a05600c4e5300b003dfeb5d0fbfmr583139wmq.38.1675412303017; Fri, 03 Feb 2023 00:18:23 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id az24-20020a05600c601800b003dc4baaedd3sm7316591wmb.37.2023.02.03.00.18.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 00:18:22 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v7 07/12] phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets Date: Fri, 3 Feb 2023 10:18:02 +0200 Message-Id: <20230203081807.2248625-8-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203081807.2248625-1-abel.vesa@linaro.org> References: <20230203081807.2248625-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v6 of this patch is: https://lore.kernel.org/all/20230202123902.3831491-8-abel.vesa@linaro.org/ Changes since v6: * none Changes since v5: * none Changes since v4: * none Changes since v3: * none Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested .../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 2 files changed, 33 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h b/drive= rs/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h new file mode 100644 index 000000000000..86d7d796d5d7 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ +#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_ + +#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0 +#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0 +#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4 +#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8 +#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114 +#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c +#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy= -qcom-qmp.h index e5974e6caf51..148663ee713a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -24,6 +24,7 @@ #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v6_20.h" +#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h" =20 #include "phy-qcom-qmp-qserdes-pll.h" =20 --=20 2.34.1