From nobody Sat Feb 7 07:09:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 939CDC61DA4 for ; Fri, 3 Feb 2023 08:18:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232819AbjBCIS4 (ORCPT ); Fri, 3 Feb 2023 03:18:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232468AbjBCISX (ORCPT ); Fri, 3 Feb 2023 03:18:23 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 911257EF6 for ; Fri, 3 Feb 2023 00:18:20 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id n13so3233783wmr.4 for ; Fri, 03 Feb 2023 00:18:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dMHGcQ3CBg0HU05mYenTzak1Su0/KOAYd0ZTLCm4XbQ=; b=t8DbKyceXe6bOBybxDPagGKRfIJibJkg6JkBckjNRnv+bm8wBLcY6hTbyN0rIal36C IwpF30MD8HUi8VdI3QU8cuOTwF/X2n+TPt/9MRR/8M2onj/agvnxQOSGJ5togVc9/76o HZ02fVAH4Wbj+A9HpUGe0+zwnjXAYWHWiNzkP8m2sFxgycePFEok1fKI7EzS4KYL4/cg k9FbLaAKubBO3w21YbfK4rXGnOGBRFDNYKH2DoopfGVnyJKVXHifeZIMckLjoxChPau0 HRMgn+zinU/X7ubIsj6Rat4FlIBuxJdVPvY2hVfEMN27yIV5LTJp055cf3o3mZ6bkw6f 9F5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dMHGcQ3CBg0HU05mYenTzak1Su0/KOAYd0ZTLCm4XbQ=; b=YKlfY0y7RUXwgIXatEljU5tNNjrM/EN75Hq7uDHabUSGo99lXKMpD5vikjag96pJG4 eCvQhTn9U5x08MgBuT29nyRrMhjJPpqLRCqtbGjK1R62oBUTYR3W9zCkM/hQw8xo8bKE DDs8wNFJNTqBNJLfHBnjhmXb8yeOS+FCtIuowPVyCeQKurznN7c8pdY4Rp/TStpMYlCz dSDJAfNyVGxq3lJwLqJNnBu5/Bmok39NaFaPf/5BNGLUIs3OlHi2XMZwmkZXY25W68V5 SGC4psdqz6nw7o/+bOYQ3n5N0/Gpw5Hk+XrHHElj4havEJTmpOzt6fOA7u0aq6XhkTWp u2kw== X-Gm-Message-State: AO0yUKU9J2pRS0vxvqbo3LzdZzh0op5z4e1Nk5AKjRjv6l7CqaEwXveK c6gX0HandyCvTQvVn11smn6eHw== X-Google-Smtp-Source: AK7set8wiGfvudMRSnc8kgLAJCYQDs5gxMQx3QZduSeo2H0UUiW31BF6Rymra1s7UHf1N0mwqH0boA== X-Received: by 2002:a05:600c:350a:b0:3dc:2af8:83c0 with SMTP id h10-20020a05600c350a00b003dc2af883c0mr8605396wmq.31.1675412300094; Fri, 03 Feb 2023 00:18:20 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id az24-20020a05600c601800b003dc4baaedd3sm7316591wmb.37.2023.02.03.00.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 00:18:19 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Dmitry Baryshkov Subject: [PATCH v7 05/12] phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets Date: Fri, 3 Feb 2023 10:18:00 +0200 Message-Id: <20230203081807.2248625-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203081807.2248625-1-abel.vesa@linaro.org> References: <20230203081807.2248625-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- This patchset relies on the following patchset: https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ The v6 of this patch is: https://lore.kernel.org/all/20230202123902.3831491-6-abel.vesa@linaro.org/ Changes since v6: * none Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 +++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 05b59f261999..907f3f236f05 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -30,6 +30,7 @@ #include "phy-qcom-qmp-pcs-pcie-v5.h" #include "phy-qcom-qmp-pcs-pcie-v5_20.h" #include "phy-qcom-qmp-pcs-pcie-v6.h" +#include "phy-qcom-qmp-pcs-pcie-v6_20.h" #include "phy-qcom-qmp-pcie-qhp.h" =20 /* QPHY_SW_RESET bit */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h new file mode 100644 index 000000000000..e3eb08776339 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_ + +/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 +#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184 +#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c +#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac +#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0 + +#endif --=20 2.34.1