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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id v9-20020a170906338900b0094ee99eeb01sm4209935eja.150.2023.05.11.09.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 09:30:03 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 11 May 2023 18:29:25 +0200 Subject: [PATCH v7 05/11] arm64: dts: mediatek: add mmc support for mt8365-evk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230203-evk-board-support-v7-5-98cbdfac656e@baylibre.com> References: <20230203-evk-board-support-v7-0-98cbdfac656e@baylibre.com> In-Reply-To: <20230203-evk-board-support-v7-0-98cbdfac656e@baylibre.com> To: Catalin Marinas , Will Deacon , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat , Kevin Hilman X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Add EMMC support on mmc0 (internal memory) - Add SD-UHS support on mmc1 (external memory) Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 138 ++++++++++++++++++++++++= ++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts index 6074aa9c1c3e..752007d0598e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -95,6 +95,42 @@ &i2c0 { status =3D "okay"; }; =20 +&mmc0 { + assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL>; + assigned-clocks =3D <&topckgen CLK_TOP_MSDC50_0_SEL>; + bus-width =3D <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay =3D <0x12012>; + max-frequency =3D <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + pinctrl-names =3D "default", "state_uhs"; + vmmc-supply =3D <&mt6357_vemc_reg>; + vqmmc-supply =3D <&mt6357_vio18_reg>; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&pio 76 GPIO_ACTIVE_LOW>; + max-frequency =3D <200000000>; + pinctrl-0 =3D <&mmc1_default_pins>; + pinctrl-1 =3D <&mmc1_uhs_pins>; + pinctrl-names =3D "default", "state_uhs"; + sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply =3D <&mt6357_vmch_reg>; + vqmmc-supply =3D <&mt6357_vio18_reg>; + status =3D "okay"; +}; + &mt6357_pmic { interrupts-extended =3D <&pio 145 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; @@ -118,6 +154,108 @@ pins { }; }; =20 + mmc0_default_pins: mmc0-default-pins { + clk-pins { + pinmux =3D ; + bias-pull-down; + }; + + cmd-dat-pins { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + rst-pins { + pinmux =3D ; + bias-pull-up; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + clk-pins { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + cmd-dat-pins { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + + ds-pins { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + rst-pins { + pinmux =3D ; + drive-strength =3D ; + bias-pull-up; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + cd-pins { + pinmux =3D ; + bias-pull-up; + }; + + clk-pins { + pinmux =3D ; + bias-pull-down =3D ; + }; + + cmd-dat-pins { + pinmux =3D , + , + , + , + ; + input-enable; + bias-pull-up =3D ; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + clk-pins { + pinmux =3D ; + drive-strength =3D ; + bias-pull-down =3D ; + }; + + cmd-dat-pins { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D ; + bias-pull-up =3D ; + }; + }; + uart0_pins: uart0-pins { pins { pinmux =3D , --=20 2.25.1