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([223.178.209.222]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00196077ba463sm12959015plg.123.2023.02.01.23.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 23:32:08 -0800 (PST) From: Sumit Garg To: will@kernel.org, catalin.marinas@arm.com Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, dianders@chromium.org, liwei391@huawei.com, mhiramat@kernel.org, maz@kernel.org, ardb@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v6 1/2] arm64: entry: Skip single stepping into interrupt handlers Date: Thu, 2 Feb 2023 13:01:47 +0530 Message-Id: <20230202073148.657746-2-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202073148.657746-1-sumit.garg@linaro.org> References: <20230202073148.657746-1-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently on systems where the timer interrupt (or any other fast-at-human-scale periodic interrupt) is active then it is impossible to step any code with interrupts unlocked because we will always end up stepping into the timer interrupt instead of stepping the user code. The common user's goal while single stepping is that when they step then the system will stop at PC+4 or PC+I for a branch that gets taken relative to the instruction they are stepping. So, fix broken single step implementation via skipping single stepping into interrupt handlers. The methodology is when we receive an interrupt from EL1, check if we are single stepping (pstate.SS). If yes then we save MDSCR_EL1.SS and clear the register bit if it was set. Then unmask only D and leave I set. On return from the interrupt, set D and restore MDSCR_EL1.SS. Along with this skip reschedule if we were stepping. Suggested-by: Will Deacon Signed-off-by: Sumit Garg Tested-by: Douglas Anderson Acked-by: Daniel Thompson Tested-by: Daniel Thompson --- arch/arm64/kernel/entry-common.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-com= mon.c index cce1167199e3..568481f66977 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -231,11 +231,15 @@ DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_= resched); #define need_irq_preemption() (IS_ENABLED(CONFIG_PREEMPTION)) #endif =20 -static void __sched arm64_preempt_schedule_irq(void) +static void __sched arm64_preempt_schedule_irq(struct pt_regs *regs) { if (!need_irq_preemption()) return; =20 + /* Don't reschedule in case we are single stepping */ + if (regs->pstate & DBG_SPSR_SS) + return; + /* * Note: thread_info::preempt_count includes both thread_info::count * and thread_info::need_resched, and is not equivalent to @@ -471,19 +475,33 @@ static __always_inline void __el1_irq(struct pt_regs = *regs, do_interrupt_handler(regs, handler); irq_exit_rcu(); =20 - arm64_preempt_schedule_irq(); + arm64_preempt_schedule_irq(regs); =20 exit_to_kernel_mode(regs); } + static void noinstr el1_interrupt(struct pt_regs *regs, void (*handler)(struct pt_regs *)) { + unsigned long mdscr; + + /* Disable single stepping within interrupt handler */ + if (regs->pstate & DBG_SPSR_SS) { + mdscr =3D read_sysreg(mdscr_el1); + write_sysreg(mdscr & ~DBG_MDSCR_SS, mdscr_el1); + } + write_sysreg(DAIF_PROCCTX_NOIRQ, daif); =20 if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs)) __el1_pnmi(regs, handler); else __el1_irq(regs, handler); + + if (regs->pstate & DBG_SPSR_SS) { + write_sysreg(DAIF_PROCCTX_NOIRQ | PSR_D_BIT, daif); + write_sysreg(mdscr, mdscr_el1); + } } =20 asmlinkage void noinstr el1h_64_irq_handler(struct pt_regs *regs) --=20 2.34.1 From nobody Sat Sep 13 13:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A136C61DA4 for ; Thu, 2 Feb 2023 07:32:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231725AbjBBHcT (ORCPT ); Thu, 2 Feb 2023 02:32:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229602AbjBBHcO (ORCPT ); Thu, 2 Feb 2023 02:32:14 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A996879F27 for ; Wed, 1 Feb 2023 23:32:13 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id f16-20020a17090a9b1000b0023058bbd7b2so384210pjp.0 for ; Wed, 01 Feb 2023 23:32:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9HVeXriudK8VUfG7IXky8/P1/K4exUTPN02+5x1/aWk=; b=tNE1hOqgyzfZrv+m53QDibjRnzkEoudW+5axJk7qRZPfiNx4ZPtPU43HSR6CGabcyb FfbVdMAMG/ozgNRH5OvsNSFeTJTAlKJwmQ6UJ+ixxNq6Sb8D3WBlnibGhvRFS/e2aQi/ StiPFniJzGkzckBo0I/+nwJk2Lk6tacdFVbhFkdR0vUb65Lv3GBhDpz7dNxdVWmb+Cqo Gla0XpBP+XWOmZu8H01SS/pubQ73Og7aDtYUpQR5X0yhy4z8G32SJb7oFFnmqp4NjIuO 4ycrTWlX56wBMM/mcWZtRCNdbQjwrLDKxRK+aTTfr0UBM5To6KnYk+MUWxF7J3WhIUyK fNRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9HVeXriudK8VUfG7IXky8/P1/K4exUTPN02+5x1/aWk=; b=FaTpDjk+yrNJregIrgu2sYz5j0rOXwh1LGWNCGWI43wOJZsjlu5pRF7nq/nZMZ4XBf dECsWPjVLg/W+nm99ZwJ3StZPJXXfQ7EW6t/elbxqX42aJuD9AbvZzXi3mQ2mAhMgenj Zy1toVabr+ikagK+OTZdBTwMUWPFOQpHsjajasF6w2RKzGlQpYEnZt7h5eO6R/AHZSr2 DUJ7DILHHtREcD96bHW05tWVoBkeKXJ4x7QuVr3O9M3Ah4iUoE37WWInABIQBd53SyJ1 /MJ5tkP5xXijtEXtvdar0xPuCBOGkKKSufYblHiC8EGTCgaTeMzQBeVvR5giJ6PR2gHn Mk4w== X-Gm-Message-State: AO0yUKVucgr4r+5vxhRBJY6D2UbiRf+t67OzGThAC/r7MD6AjblMC7mg 3K0JpcfftIMC0mRBBgklwjVO+w== X-Google-Smtp-Source: AK7set+mw1dHNc9akouI86sKWRtZ8+TxnQMNzD8jTeP64nqqdVQDR6kM1hbsJzaChVbCT91YbraX7Q== X-Received: by 2002:a17:902:ecd1:b0:196:12f1:76f5 with SMTP id a17-20020a170902ecd100b0019612f176f5mr1206670plh.52.1675323133195; Wed, 01 Feb 2023 23:32:13 -0800 (PST) Received: from sumit-X1.. ([223.178.209.222]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00196077ba463sm12959015plg.123.2023.02.01.23.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 23:32:12 -0800 (PST) From: Sumit Garg To: will@kernel.org, catalin.marinas@arm.com Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, dianders@chromium.org, liwei391@huawei.com, mhiramat@kernel.org, maz@kernel.org, ardb@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v6 2/2] arm64: kgdb: Set PSTATE.SS to 1 to re-enable single-step Date: Thu, 2 Feb 2023 13:01:48 +0530 Message-Id: <20230202073148.657746-3-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202073148.657746-1-sumit.garg@linaro.org> References: <20230202073148.657746-1-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently only the first attempt to single-step has any effect. After that all further stepping remains "stuck" at the same program counter value. Refer to the ARM Architecture Reference Manual (ARM DDI 0487E.a) D2.12, PSTATE.SS=3D1 should be set at each step before transferring the PE to the 'Active-not-pending' state. The problem here is PSTATE.SS=3D1 is not set since the second single-step. After the first single-step, the PE transferes to the 'Inactive' state, with PSTATE.SS=3D0 and MDSCR.SS=3D1, thus PSTATE.SS won't be set to 1 due to kernel_active_single_step()=3Dtrue. Then the PE transferes to the 'Active-pending' state when ERET and returns to the debugger by step exception. Before this patch: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Entering kdb (current=3D0xffff3376039f0000, pid 1) on processor 0 due to Ke= yboard Entry [0]kdb> [0]kdb> [0]kdb> bp write_sysrq_trigger Instruction(i) BP #0 at 0xffffa45c13d09290 (write_sysrq_trigger) is enabled addr at ffffa45c13d09290, hardtype=3D0 installed=3D0 [0]kdb> go $ echo h > /proc/sysrq-trigger Entering kdb (current=3D0xffff4f7e453f8000, pid 175) on processor 1 due to = Breakpoint @ 0xffffad651a309290 [1]kdb> ss Entering kdb (current=3D0xffff4f7e453f8000, pid 175) on processor 1 due to = SS trap @ 0xffffad651a309294 [1]kdb> ss Entering kdb (current=3D0xffff4f7e453f8000, pid 175) on processor 1 due to = SS trap @ 0xffffad651a309294 [1]kdb> After this patch: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Entering kdb (current=3D0xffff6851c39f0000, pid 1) on processor 0 due to Ke= yboard Entry [0]kdb> bp write_sysrq_trigger Instruction(i) BP #0 at 0xffffc02d2dd09290 (write_sysrq_trigger) is enabled addr at ffffc02d2dd09290, hardtype=3D0 installed=3D0 [0]kdb> go $ echo h > /proc/sysrq-trigger Entering kdb (current=3D0xffff6851c53c1840, pid 174) on processor 1 due to = Breakpoint @ 0xffffc02d2dd09290 [1]kdb> ss Entering kdb (current=3D0xffff6851c53c1840, pid 174) on processor 1 due to = SS trap @ 0xffffc02d2dd09294 [1]kdb> ss Entering kdb (current=3D0xffff6851c53c1840, pid 174) on processor 1 due to = SS trap @ 0xffffc02d2dd09298 [1]kdb> ss Entering kdb (current=3D0xffff6851c53c1840, pid 174) on processor 1 due to = SS trap @ 0xffffc02d2dd0929c [1]kdb> Fixes: 44679a4f142b ("arm64: KGDB: Add step debugging support") Co-developed-by: Wei Li Signed-off-by: Wei Li Signed-off-by: Sumit Garg Tested-by: Douglas Anderson Acked-by: Daniel Thompson Tested-by: Daniel Thompson --- arch/arm64/include/asm/debug-monitors.h | 1 + arch/arm64/kernel/debug-monitors.c | 5 +++++ arch/arm64/kernel/kgdb.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/a= sm/debug-monitors.h index 7b7e05c02691..13d437bcbf58 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -104,6 +104,7 @@ void user_regs_reset_single_step(struct user_pt_regs *r= egs, void kernel_enable_single_step(struct pt_regs *regs); void kernel_disable_single_step(void); int kernel_active_single_step(void); +void kernel_rewind_single_step(struct pt_regs *regs); =20 #ifdef CONFIG_HAVE_HW_BREAKPOINT int reinstall_suspended_bps(struct pt_regs *regs); diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-m= onitors.c index 3da09778267e..64f2ecbdfe5c 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -438,6 +438,11 @@ int kernel_active_single_step(void) } NOKPROBE_SYMBOL(kernel_active_single_step); =20 +void kernel_rewind_single_step(struct pt_regs *regs) +{ + set_regs_spsr_ss(regs); +} + /* ptrace API */ void user_enable_single_step(struct task_struct *task) { diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c index cda9c1e9864f..4e1f983df3d1 100644 --- a/arch/arm64/kernel/kgdb.c +++ b/arch/arm64/kernel/kgdb.c @@ -224,6 +224,8 @@ int kgdb_arch_handle_exception(int exception_vector, in= t signo, */ if (!kernel_active_single_step()) kernel_enable_single_step(linux_regs); + else + kernel_rewind_single_step(linux_regs); err =3D 0; break; default: --=20 2.34.1