From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F7DAC6FD1F for ; Tue, 7 Mar 2023 12:10:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231435AbjCGMKQ (ORCPT ); Tue, 7 Mar 2023 07:10:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230207AbjCGMKN (ORCPT ); Tue, 7 Mar 2023 07:10:13 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03541574F7; Tue, 7 Mar 2023 04:10:11 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 39EE326F886; Tue, 7 Mar 2023 13:10:10 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:07 +0100 Subject: [PATCH v3 01/15] dt-bindings: power: apple,pmgr-pwrstate: Add t8112 compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-1-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1516; i=j@jannau.net; h=from:subject:message-id; bh=5sGxEKFsM7Xw7GaCGqyKYguwe6Up2BPnOTTHMCNSZ0Y=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zfnTvXRUVznFLBI453MjIrtYbqd0ZvYZN9u48Bf8r /zf3bTqKGVhEONgkBVTZEnSftnBsLpGMab2QRjMHFYmkCEMXJwCMBGNRIb/jqZ5OhcSd0z6Y+Qa oyod++e2Zzvfo18XYwrFeqN5XsV/Z/ifP8fibU1u2wmtKeu9ZQy2r0nfdursZNbqicwTexeZ3Wp iBwA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Hector Martin Add the apple,t8112-pmgr-pwrstate compatible for the Apple M2 SoC. This goes after t8103. The sort order logic here is having SoC numeric code families in release order, and SoCs within each family in release order: - t8xxx (Apple HxxP/G series, "phone"/"tablet" chips) - t8103 (Apple H13G/M1) - t8112 (Apple H14G/M2) - t6xxx (Apple HxxJ series, "desktop" chips) - t6000 (Apple H13J(S)/M1 Pro) - t6001 (Apple H13J(C)/M1 Max) - t6002 (Apple H13J(D)/M1 Ultra) Note that t600[0-2] share the t6000 compatible where the hardware is 100% compatible, which is usually the case in this highly related set of SoCs. Signed-off-by: Hector Martin Reviewed-by: Janne Grunau Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.ya= ml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 94d369eb85de..59a6af735a21 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -32,6 +32,7 @@ properties: items: - enum: - apple,t8103-pmgr-pwrstate + - apple,t8112-pmgr-pwrstate - apple,t6000-pmgr-pwrstate - const: apple,pmgr-pwrstate =20 --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51628C6FD1E for ; Tue, 7 Mar 2023 12:10:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230154AbjCGMKW (ORCPT ); Tue, 7 Mar 2023 07:10:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231386AbjCGMKN (ORCPT ); Tue, 7 Mar 2023 07:10:13 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59EB1574F9; Tue, 7 Mar 2023 04:10:12 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id AE1FB26F887; Tue, 7 Mar 2023 13:10:10 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:08 +0100 Subject: [PATCH v3 02/15] dt-bindings: arm: apple: apple,pmgr: Add t8112-pmgr compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-2-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=853; i=j@jannau.net; h=from:subject:message-id; bh=ybTUXg2wpUrawfnRKcBhuVH8s4zUBgGLXebQhbD7PL0=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zfkuzHGb+qy/+b/v8bn3T/uu64a6pA2Kl2e4b35bV GKdt+l6RykLgxgHg6yYIkuS9ssOhtU1ijG1D8Jg5rAygQxh4OIUgIk0PWdkmHr99XvFzbvPvNvJ t8qKp+LTnh1FXN1CwTHXT2neeSn1+T7DP/X9ubnvo+U9Gu48maR1su7o/2Bv2aqN17ziNb992KZ 1nhEA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The block on Apple M2 SoCs is compatible with the existing driver so just add its per-SoC compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/= Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index 0dc957a56d35..673277a7a224 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -23,6 +23,7 @@ properties: items: - enum: - apple,t8103-pmgr + - apple,t8112-pmgr - apple,t6000-pmgr - const: apple,pmgr - const: syscon --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1D5FC6FD1B for ; Tue, 7 Mar 2023 12:10:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231478AbjCGMK0 (ORCPT ); Tue, 7 Mar 2023 07:10:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231393AbjCGMKN (ORCPT ); Tue, 7 Mar 2023 07:10:13 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CBC8574FD; Tue, 7 Mar 2023 04:10:12 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 1B2CD26F888; Tue, 7 Mar 2023 13:10:11 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:09 +0100 Subject: [PATCH v3 03/15] dt-bindings: watchdog: apple,wdt: Add t8112-wdt compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-3-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=816; i=j@jannau.net; h=from:subject:message-id; bh=ii0IadQVOv7ya4XwtBGFuGJ/mm304g8PFld9ejyrFvc=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQXzY+aFXE9WmPOgUF5Z/1HEMZ8rwlVeL9ZJ9cSuc rDmy9HrKGVhEONgkBVTZEnSftnBsLpGMab2QRjMHFYmkCEMXJwCMBGlKoa/8qWvi7rvPeqc/03i XsDUly/bFh1nevdSv9O67atQqPjBnwz/LFa++Tzt//vljTo/Rfk/Tt76I3TfW7lZtQ5l8idurI2 V5gYA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The block on the Apple M2 SoC is compatible with the existing driver so add its per-SoC compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/watchdog/apple,wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Do= cumentation/devicetree/bindings/watchdog/apple,wdt.yaml index e58c56a6fdf6..3d7e2a2bf1f1 100644 --- a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - apple,t8103-wdt + - apple,t8112-wdt - apple,t6000-wdt - const: apple,wdt =20 --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D2DEC678D4 for ; Tue, 7 Mar 2023 12:10:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231493AbjCGMK3 (ORCPT ); Tue, 7 Mar 2023 07:10:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231392AbjCGMKN (ORCPT ); Tue, 7 Mar 2023 07:10:13 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 036C0574FE; Tue, 7 Mar 2023 04:10:13 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 8FDE326F889; Tue, 7 Mar 2023 13:10:11 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:10 +0100 Subject: [PATCH v3 04/15] dt-bindings: arm: cpus: Add apple,avalanche & blizzard compatibles MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-4-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=726; i=j@jannau.net; h=from:subject:message-id; bh=d7EFnNyp4GW9oyQuCElVq0C558+zBtSSmAZe284c8NY=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQXKk28pHrlt47xJ7++fX6pHO96dFN1WYdBwteCLQ EPBhbcLO0pZGMQ4GGTFFFmStF92MKyuUYypfRAGM4eVCWQIAxenAExEu5Xhf4VcvPotSXd3c70/ 5T4mzvYcbfejzmw7kBPX1CTWWtr2j+En48zzW3d3Ovju9N3k2BbCwnQ7q4tH3X/CM+mkWG/txU3 sAA== X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These are the CPU cores in the Apple silicon M2 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index 01b5a9c689a2..ac79fbb1479d 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -85,6 +85,8 @@ properties: =20 compatible: enum: + - apple,avalanche + - apple,blizzard - apple,icestorm - apple,firestorm - arm,arm710t --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C43DC678D4 for ; Tue, 7 Mar 2023 12:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231508AbjCGMKf (ORCPT ); Tue, 7 Mar 2023 07:10:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231411AbjCGMKP (ORCPT ); Tue, 7 Mar 2023 07:10:15 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CDD9574F7; Tue, 7 Mar 2023 04:10:14 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 12DDF26F88A; Tue, 7 Mar 2023 13:10:12 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:11 +0100 Subject: [PATCH v3 05/15] dt-bindings: interrupt-controller: apple,aic2: Add apple,t8112-aic compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-5-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Marc Zyngier X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1922; i=j@jannau.net; h=from:subject:message-id; bh=AibLTj6QTncN8IwWQQoAipjlxWNMIT6q7M88xOQXxf0=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQUthncWCDB1ey5/vHSNp4X5yh5BVd22sKSpG6tN3 UUY9y7tKGVhEONgkBVTZEnSftnBsLpGMab2QRjMHFYmkCEMXJwCMJHnoYwM3UbKz99cvLSv+sZp 2fOmd2777azoOLCMKUvcvtx4Wc3U2wz/DH/k+a7eoBMnVvteNSjaXjT6if/22nnS1t3fsvY+Zzz HAAA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Apple M2 SoC uses AICv2 and is compatible with the existing driver. Add its per-SoC compatible. Since multi-die versions of the M2 are not expected decrease '#interrupt-cells' to 3 for apple,t8112-aic. This is seamlessly handled inside the driver. Acked-by: Marc Zyngier Signed-off-by: Janne Grunau Reviewed-by: Rob Herring --- .../bindings/interrupt-controller/apple,aic2.yaml | 22 ++++++++++++++++++= +--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic= 2.yaml index 06948c0e36a5..2bde6cc6fe0a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -31,19 +31,22 @@ description: | properties: compatible: items: - - const: apple,t6000-aic + - enum: + - apple,t8112-aic + - apple,t6000-aic - const: apple,aic2 =20 interrupt-controller: true =20 '#interrupt-cells': - const: 4 + minimum: 3 + maximum: 4 description: | The 1st cell contains the interrupt type: - 0: Hardware IRQ - 1: FIQ =20 - The 2nd cell contains the die ID. + The 2nd cell contains the die ID (only present on apple,t6000-aic). =20 The next cell contains the interrupt number. - HW IRQs: interrupt number @@ -109,6 +112,19 @@ additionalProperties: false =20 allOf: - $ref: /schemas/interrupt-controller.yaml# + - if: + properties: + compatible: + contains: + const: apple,t8112-aic + then: + properties: + '#interrupt-cells': + const: 3 + else: + properties: + '#interrupt-cells': + const: 4 =20 examples: - | --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8548C678D5 for ; Tue, 7 Mar 2023 12:10:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230476AbjCGMKc (ORCPT ); Tue, 7 Mar 2023 07:10:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231410AbjCGMKP (ORCPT ); Tue, 7 Mar 2023 07:10:15 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4ECAD574F8; Tue, 7 Mar 2023 04:10:14 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 8697226F88B; Tue, 7 Mar 2023 13:10:12 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:12 +0100 Subject: [PATCH v3 06/15] dt-bindings: iommu: apple,sart: Add apple,t8112-sart compatible string MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-6-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1092; i=j@jannau.net; h=from:subject:message-id; bh=SF0RulFge1KLXxYvCFPks4sDQS0ghvbAM8eYX/qWUvY=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQUu7LeXcGj82rYoseHPxeUl81ZeqNUyCJrp0DJBb OIvp4llHaUsDGIcDLJiiixJ2i87GFbXKMbUPgiDmcPKBDKEgYtTACaSvpDhv/e3BVPOZ6oH/2sL ez3HX+I0M8+zN6JCi77NU34Vt5d3ozbDP4PGirOarQ9aZ06PPbTsWuPpJyZcM4o8P7pN0Kl7fei ULicA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org "apple,t8112-sart" as found on the Apple M2 SoC appears to be SART3 as well. To allow for later discovered incompatibilities use '"apple,t8112-sart", "apple,t6000-sart"' as compatible string. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/iommu/apple,sart.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Docu= mentation/devicetree/bindings/iommu/apple,sart.yaml index 1524fa3094ef..e87c1520fea6 100644 --- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml @@ -28,9 +28,13 @@ description: =20 properties: compatible: - enum: - - apple,t6000-sart - - apple,t8103-sart + oneOf: + - items: + - const: apple,t8112-sart + - const: apple,t6000-sart + - enum: + - apple,t6000-sart + - apple,t8103-sart =20 reg: maxItems: 1 --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14C62C678D4 for ; Tue, 7 Mar 2023 12:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231540AbjCGMKs (ORCPT ); Tue, 7 Mar 2023 07:10:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231432AbjCGMKP (ORCPT ); Tue, 7 Mar 2023 07:10:15 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FC8A574F9; Tue, 7 Mar 2023 04:10:14 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 00CB926F88C; Tue, 7 Mar 2023 13:10:12 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:13 +0100 Subject: [PATCH v3 07/15] dt-bindings: mailbox: apple,mailbox: Add t8112 compatibles MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-7-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1113; i=j@jannau.net; h=from:subject:message-id; bh=N693tafX0qAFE8W6k3tnxNM5n/k2VjZzvqvkRjvhcps=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQX+ixw9///tz98xx6VW4uDn3hCuCE3PPx1cLRsMv jEKWYR1lLIwiHEwyIopsiRpv+xgWF2jGFP7IAxmDisTyBAGLk4BuMn5DP9dXnid5nh35+qZvMU1 LU3RJ95NXJgz6+kzFt2J56p5q3YeZPif+sv65cOCnS1Rx/Iy/9avqkmJON8Xtlbl0KT9S5INyv3 YAA== X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The mailbox hardware remains unchanged on M2 SoCs so just add its per-SoC compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b= /Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 5c5c328b3134..4c0668e5f0bd 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -29,6 +29,7 @@ properties: items: - enum: - apple,t8103-asc-mailbox + - apple,t8112-asc-mailbox - apple,t6000-asc-mailbox - const: apple,asc-mailbox-v4 =20 @@ -39,6 +40,7 @@ properties: items: - enum: - apple,t8103-m3-mailbox + - apple,t8112-m3-mailbox - apple,t6000-m3-mailbox - const: apple,m3-mailbox-v2 =20 --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CFC1C6FA99 for ; Tue, 7 Mar 2023 12:10:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231529AbjCGMKo (ORCPT ); Tue, 7 Mar 2023 07:10:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231433AbjCGMKP (ORCPT ); Tue, 7 Mar 2023 07:10:15 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C61A5574FD; Tue, 7 Mar 2023 04:10:14 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 6FA3A26F88D; Tue, 7 Mar 2023 13:10:13 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:14 +0100 Subject: [PATCH v3 08/15] dt-bindings: nvme: apple: Add apple,t8112-nvme-ans2 compatible string MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-8-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1270; i=j@jannau.net; h=from:subject:message-id; bh=fHBkvAY6XhNS/kXyTd3/WQYda6VSGxdD5gGv92wX0ao=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQWRO9lkI1PuGm+QrNx1Wmp5KtOn5VO2WtxPPfXnd 9H9+9kvO0pZGMQ4GGTFFFmStF92MKyuUYypfRAGM4eVCWQIAxenAExE5TPDH/4bE1fsyZQ57+bN a7wg863npS3aPlNcp9w899KWPdnxwg5GhqnCFhu3G1mzu7xY+39yXnPSb/UTh9S913/9EDnJQft oAzMA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org "apple,t8112-nvme-ans2" as found on Apple M2 SoCs is compatible with the existing driver. Add its SoC specific compatible string to allow special handling if it'll be necessary. t8112 uses only 2 power-domains as no 4 and 8 TB configurations are offered. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml b/D= ocumentation/devicetree/bindings/nvme/apple,nvme-ans.yaml index 34dd1cc67124..fc6555724e18 100644 --- a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml +++ b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - apple,t8103-nvme-ans2 + - apple,t8112-nvme-ans2 - apple,t6000-nvme-ans2 - const: apple,nvme-ans2 =20 @@ -65,7 +66,9 @@ if: properties: compatible: contains: - const: apple,t8103-nvme-ans2 + enum: + - apple,t8103-nvme-ans2 + - apple,t8112-nvme-ans2 then: properties: power-domains: --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B865BC6FA99 for ; Tue, 7 Mar 2023 12:10:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231522AbjCGMKj (ORCPT ); Tue, 7 Mar 2023 07:10:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231434AbjCGMKP (ORCPT ); Tue, 7 Mar 2023 07:10:15 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37AEA574FF; Tue, 7 Mar 2023 04:10:15 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id DC08626F88E; Tue, 7 Mar 2023 13:10:13 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:15 +0100 Subject: [PATCH v3 09/15] dt-bindings: pci: apple,pcie: Add t8112 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-9-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=828; i=j@jannau.net; h=from:subject:message-id; bh=JihawOspwn0Hp3le9Nwk0ot6u82zc3e0l7bsuRo/pPE=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQXnPd+c9GLfMHMhh3vm0+5Kj3tJT2xWiYX3CPF8a Dl9MvBmRykLgxgHg6yYIkuS9ssOhtU1ijG1D8Jg5rAygQxh4OIUgIlsec/wT9VmTmSQ8zPBQ6Vs DBHrju+ccs/xublcY/2P439LBE763mVkWH3hmNwuhz8/M/4Y/ejTPOi4M/Azyw6laKv7598kty7 k5QUA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The block found in the Apple M2 SoC is compatible with the existing driver, and supports 4 downstream ports like the t6000 one. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/pci/apple,pcie.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Docume= ntation/devicetree/bindings/pci/apple,pcie.yaml index aa38680aaaca..215ff9a9c835 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -33,6 +33,7 @@ properties: items: - enum: - apple,t8103-pcie + - apple,t8112-pcie - apple,t6000-pcie - const: apple,pcie =20 --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 943A3C678D5 for ; Tue, 7 Mar 2023 12:10:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231547AbjCGMKx (ORCPT ); Tue, 7 Mar 2023 07:10:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231436AbjCGMKQ (ORCPT ); Tue, 7 Mar 2023 07:10:16 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1C1658C2A; Tue, 7 Mar 2023 04:10:15 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 4140426F88F; Tue, 7 Mar 2023 13:10:14 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:16 +0100 Subject: [PATCH v3 10/15] dt-bindings: pinctrl: apple,pinctrl: Add apple,t8112-pinctrl compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-10-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Linus Walleij , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=885; i=j@jannau.net; h=from:subject:message-id; bh=emwm2BfdpDjLFN5l7U/xhtMosXL+9+W5cMnCWIbIWLU=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQXnXm6ezGyxP6XpSib7J913pqv+y7D7Bvy2N071P d6771JtRykLgxgHg6yYIkuS9ssOhtU1ijG1D8Jg5rAygQxh4OIUgImIeTMyzOeaJvb7/NmpBcXL JjIs2/7+zBWDHfOjWT2Fti5Jn3LhSxDDP7sE9iVXZhRcrai0nHV4cefK5c9ZIrdn3HfsiBP0/tz cyQIA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This new SoC uses the same pinctrl hardware, so just add a new per-SoC compatible. Reviewed-by: Linus Walleij Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b= /Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index d3b11351ca45..684c03a6bd40 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -19,6 +19,7 @@ properties: items: - enum: - apple,t8103-pinctrl + - apple,t8112-pinctrl - apple,t6000-pinctrl - const: apple,pinctrl =20 --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F788C678D4 for ; Tue, 7 Mar 2023 12:10:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231492AbjCGMK6 (ORCPT ); Tue, 7 Mar 2023 07:10:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230207AbjCGMKQ (ORCPT ); Tue, 7 Mar 2023 07:10:16 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DDB35BC98; Tue, 7 Mar 2023 04:10:16 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id B47EA26F890; Tue, 7 Mar 2023 13:10:14 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:17 +0100 Subject: [PATCH v3 11/15] dt-bindings: i2c: apple,i2c: Add apple,t8112-i2c compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-11-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Wolfram Sang , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=844; i=j@jannau.net; h=from:subject:message-id; bh=kZ/WMKcp3dcjJwh2XKtFEVEGisjZv0FjdIXlTV2n8hs=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zQU9yf2zVIrK72lNC5f0uhb0KjVU1pjD0Xpzhl76t T9VP/k6SlkYxDgYZMUUWZK0X3YwrK5RjKl9EAYzh5UJZAgDF6cATETkCyNDx48V7+pEZYqr4kMn 6y9t2c1zNuzNyxm1H6LTfWaxZt/KZPjJGF7999LZTAs15fI9SeorFk1OSdR+YpK0Js/vDmtbexk TAA== X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This block on the Apple M2 is compatible with the existing driver so just add the per-SoC compatible. Acked-by: Wolfram Sang # for I2C Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documen= tation/devicetree/bindings/i2c/apple,i2c.yaml index 4ac61fec90e2..3f0e94189f2d 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -23,6 +23,7 @@ properties: items: - enum: - apple,t8103-i2c + - apple,t8112-i2c - apple,t6000-i2c - const: apple,i2c =20 --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99BA3C678D4 for ; Tue, 7 Mar 2023 12:11:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231469AbjCGMLC (ORCPT ); Tue, 7 Mar 2023 07:11:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231445AbjCGMKS (ORCPT ); Tue, 7 Mar 2023 07:10:18 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 764D2574FD; Tue, 7 Mar 2023 04:10:16 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 1E96A26F891; Tue, 7 Mar 2023 13:10:15 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:18 +0100 Subject: [PATCH v3 12/15] dt-bindings: clock: apple,nco: Add t8112-nco compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-12-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , =?utf-8?q?Martin_Povi=C5=A1er?= , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=855; i=j@jannau.net; h=from:subject:message-id; bh=fMPj5crwscCjCF6wuCOksaYtnate8ApH0BFsWpiUj9Q=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zYUcwvvjZbb+lw5e1NEhlrBVQjHu1OKA1GNhgdu7q 8L0O/g7SlkYxDgYZMUUWZK0X3YwrK5RjKl9EAYzh5UJZAgDF6cATGSVAyPD0l7dbZUrYzdP8nZ5 ePZq8sdjqo3mr8Wnr956eV76gy3Z8xgZbm4xDPu6I6OzeNPBOLOLe5fKTKxVdiu/bDt5/XRr36a THAA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The block found on Apple's M2 SoC is compatible with the existing driver so add its per-SoC compatible. Acked-by: Martin Povi=C5=A1er Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/clock/apple,nco.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/apple,nco.yaml b/Docum= entation/devicetree/bindings/clock/apple,nco.yaml index 74eab5c0d24a..8b8411dc42f6 100644 --- a/Documentation/devicetree/bindings/clock/apple,nco.yaml +++ b/Documentation/devicetree/bindings/clock/apple,nco.yaml @@ -23,6 +23,7 @@ properties: - enum: - apple,t6000-nco - apple,t8103-nco + - apple,t8112-nco - const: apple,nco =20 clocks: --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4EADC678D4 for ; Tue, 7 Mar 2023 12:11:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231589AbjCGMLE (ORCPT ); Tue, 7 Mar 2023 07:11:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231448AbjCGMKS (ORCPT ); Tue, 7 Mar 2023 07:10:18 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D21F75BC91; Tue, 7 Mar 2023 04:10:16 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 786E426F892; Tue, 7 Mar 2023 13:10:15 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:19 +0100 Subject: [PATCH v3 13/15] dt-bindings: dma: apple,admac: Add t8112-admac compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-13-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Vinod Koul , =?utf-8?q?Martin_Povi=C5=A1er?= , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=901; i=j@jannau.net; h=from:subject:message-id; bh=ENxJR/4ec2wFqwP1J+M9quJhlxwuKaKTGKKe7sCvoAk=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zYU2vtOffP8fqyRvuWXyhq/bExaKVr0W9G2+O1Grc HGUe4FrRykLgxgHg6yYIkuS9ssOhtU1ijG1D8Jg5rAygQxh4OIUgIm8esHw30ksd53Fx/gPAUJJ 7k6T3hZfW9eio8Kolhlv+PLHu2LfBUAVJ/d3lm9ROdEspVwfHn95dlpPbuO+f/GT5y78sMFgRwA LAA== X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The block found on Apple's M2 SoC is compatible with the existing driver so add its per-SoC compatible. Acked-by: Vinod Koul Acked-by: Martin Povi=C5=A1er Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/dma/apple,admac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/apple,admac.yaml b/Docum= entation/devicetree/bindings/dma/apple,admac.yaml index 97282469e4af..beb09f115f40 100644 --- a/Documentation/devicetree/bindings/dma/apple,admac.yaml +++ b/Documentation/devicetree/bindings/dma/apple,admac.yaml @@ -26,6 +26,7 @@ properties: - enum: - apple,t6000-admac - apple,t8103-admac + - apple,t8112-admac - const: apple,admac =20 reg: --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84CAEC678D4 for ; Tue, 7 Mar 2023 12:11:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231596AbjCGMLI (ORCPT ); Tue, 7 Mar 2023 07:11:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231451AbjCGMKS (ORCPT ); Tue, 7 Mar 2023 07:10:18 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B00F75DED1; Tue, 7 Mar 2023 04:10:17 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id E84EE26F893; Tue, 7 Mar 2023 13:10:15 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:20 +0100 Subject: [PATCH v3 14/15] dt-bindings: arm: apple: Add t8112 j413/j473/j493 compatibles MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-14-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Krzysztof Kozlowski X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1950; i=j@jannau.net; h=from:subject:message-id; bh=guJnPPQkZPa9Dkc29qdLKw+IvBdbCOqYiRiieX0Cd84=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zYWVpq/rvyx/rF8RoxJn9CYxb7HKmXgj0w5p3t6y2 5778hd0lLIwiHEwyIopsiRpv+xgWF2jGFP7IAxmDisTyBAGLk4BmMi6BQz/fbIV7/sUL3V97+32 9UeOt8nEYwrn328QmrlX5InN7uKfTgz/bL9kXTHN+VK8+ZWJvfpUhlJ18b0+nQpNQgu2JX7pvrS RDQA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the following apple,t8112 platforms: - apple,j413 - MacBook Air (M2, 2022) - apple,j473 - Mac mini (M2, 2023) - apple,j493 - MacBook Pro (13-inch, M2, 2022) The sort order logic here is having SoC numeric code families in release order, and SoCs within each family in release order: - t8xxx (Apple HxxP/G series, "phone"/"tablet" chips) - t8103 (Apple H13G/M1) - t8112 (Apple H14G/M2) - t6xxx (Apple HxxJ series, "desktop" chips) - t6000 (Apple H13J(S)/M1 Pro) - t6001 (Apple H13J(C)/M1 Max) - t6002 (Apple H13J(D)/M1 Ultra) Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau --- Documentation/devicetree/bindings/arm/apple.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentati= on/devicetree/bindings/arm/apple.yaml index da78c69774f2..883fd67e3752 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -19,6 +19,12 @@ description: | - MacBook Air (M1, 2020) - iMac (24-inch, M1, 2021) =20 + Devices based on the "M2" SoC: + + - MacBook Air (M2, 2022) + - MacBook Pro (13-inch, M2, 2022) + - Mac mini (M2, 2023) + And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: =20 - MacBook Pro (14-inch, M1 Pro, 2021) @@ -70,6 +76,15 @@ properties: - const: apple,t8103 - const: apple,arm-platform =20 + - description: Apple M2 SoC based platforms + items: + - enum: + - apple,j413 # MacBook Air (M2, 2022) + - apple,j473 # Mac mini (M2, 2023) + - apple,j493 # MacBook Pro (13-inch, M2, 2022) + - const: apple,t8112 + - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms items: - enum: --=20 2.39.2 From nobody Fri Sep 12 02:08:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B467FC678D4 for ; Tue, 7 Mar 2023 12:11:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbjCGMLN (ORCPT ); Tue, 7 Mar 2023 07:11:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231474AbjCGMKY (ORCPT ); Tue, 7 Mar 2023 07:10:24 -0500 Received: from soltyk.jannau.net (soltyk.jannau.net [144.76.91.90]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 083175BCAA; Tue, 7 Mar 2023 04:10:17 -0800 (PST) Received: from robin.home.jannau.net (p54accbe8.dip0.t-ipconnect.de [84.172.203.232]) by soltyk.jannau.net (Postfix) with ESMTPSA id 4EFD826F894; Tue, 7 Mar 2023 13:10:16 +0100 (CET) From: Janne Grunau Date: Tue, 07 Mar 2023 13:10:21 +0100 Subject: [PATCH v3 15/15] arm64: dts: apple: t8112: Initial t8112 (M2) device trees MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230202-asahi-t8112-dt-v3-15-d1a5f6383d95@jannau.net> References: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> In-Reply-To: <20230202-asahi-t8112-dt-v3-0-d1a5f6383d95@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Mark Kettenis Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=65859; i=j@jannau.net; h=from:subject:message-id; bh=JyJGEuAOMxZlwUx9ZPF3DqbJqAnp76LtIep92BxuBWg=; b=owGbwMvMwCG2UNrmdq9+ahrjabUkhhR2zYVZaskKK19n6vQ+czi3X2c5n3Tje5Gz344eYvFs/ Civt6mio5SFQYyDQVZMkSVJ+2UHw+oaxZjaB2Ewc1iZQIYwcHEKwER2/mH4K2q0efLBg80qAZd6 PPsexfElnzz24WHblo9tcXwz2O+m+DMyNBX8uM54fqZc4y3O7GRHubffXm54H7077oisC3/o7m0 nWAA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Hector Martin This adds device trees for the following devices: - Macbook Air (M2, 2022) - Macbook Pro 13" (M2, 2022) - Mac mini (M2, 2023) This brings the hardware support of the machines to the same level as M1 and M1 Pro / Max / Ultra. Supported hardware include NVMe, PCIe, serial, pinctrl/gpio, I2C, iommu, watchdog, admac, nco, cpufreq, boot framebuffer for laptop panels and the interrupt controller. The ethernet LAN device on the M2 Mac mini is the only working PCIe device. The Wlan/BT devices are powered off and controlled by the not yet supported SMC. The ASMedia xHCI on the M2 Mac mini requires firmware to be loaded at startup. The main missing hardware support to make these devices useful are the integrated USB 2/3/4 controller, keyboard and trackpad on the laptops and SMC to power the PCIe Wlan/BT device on. The M2 Mac mini has currently no working display output. Due to changes in the display pipeline it is currently not possible to initialize the HDMI output in the bootloader. Signed-off-by: Hector Martin Co-developed-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/Makefile | 3 + arch/arm64/boot/dts/apple/t8112-j413.dts | 63 ++ arch/arm64/boot/dts/apple/t8112-j473.dts | 54 ++ arch/arm64/boot/dts/apple/t8112-j493.dts | 52 ++ arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 81 ++ arch/arm64/boot/dts/apple/t8112-pmgr.dtsi | 1141 +++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t8112.dtsi | 912 +++++++++++++++++++++++ 7 files changed, 2306 insertions(+) diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index 5a7506ff5ea3..aec5e29cdfb7 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -10,3 +10,6 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j413.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j473.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j493.dtb diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts= /apple/t8112-j413.dts new file mode 100644 index 000000000000..9e758edeaa82 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (M2, 2022) + * + * target-type: J413 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" + +/ { + compatible =3D "apple,j413", "apple,t8112", "apple,arm-platform"; + model =3D "Apple MacBook Air (13-inch, M2, 2022)"; + + aliases { + bluetooth0 =3D &bluetooth0; + wifi0 =3D &wifi0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range =3D <1 1>; + wifi0: wifi@0,0 { + compatible =3D "pci14e4,4433"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address =3D [00 10 18 00 00 10]; + apple,antenna-sku =3D "XX"; + brcm,board-type =3D "apple,hokkaido"; + }; + + bluetooth0: bluetooth@0,1 { + compatible =3D "pci14e4,5f71"; + reg =3D <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address =3D [00 00 00 00 00 00]; + brcm,board-type =3D "apple,hokkaido"; + }; +}; + +&i2c0 { + /* MagSafe port */ + hpm5: usb-pd@3a { + compatible =3D "apple,cd321x"; + reg =3D <0x3a>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; +}; + +&i2c4 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts= /apple/t8112-j473.dts new file mode 100644 index 000000000000..06fe257f08be --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple Mac mini (M2, 2023) + * + * target-type: J473 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" + +/ { + compatible =3D "apple,j473", "apple,t8112", "apple,arm-platform"; + model =3D "Apple Mac mini (M2, 2023)"; + + aliases { + ethernet0 =3D ðernet0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range =3D <1 1>; +}; + +&port01 { + bus-range =3D <2 2>; + status =3D "okay"; +}; + +&port02 { + bus-range =3D <3 3>; + status =3D "okay"; + ethernet0: ethernet@0,0 { + reg =3D <0x30000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address =3D [00 10 18 00 00 00]; + }; +}; + +&pcie1_dart { + status =3D "okay"; +}; + +&pcie2_dart { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts= /apple/t8112-j493.dts new file mode 100644 index 000000000000..8552c15be265 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Pro (13-inch, M1, 2022) + * + * target-type: J493 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" + +/ { + compatible =3D "apple,j493", "apple,t8112", "apple,arm-platform"; + model =3D "Apple MacBook Pro (13-inch, M2, 2022)"; + + aliases { + bluetooth0 =3D &bluetooth0; + wifi0 =3D &wifi0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range =3D <1 1>; + wifi0: wifi@0,0 { + compatible =3D "pci14e4,4425"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address =3D [00 00 00 00 00 00]; + apple,antenna-sku =3D "XX"; + brcm,board-type =3D "apple,kyushu"; + }; + + bluetooth0: bluetooth@0,1 { + compatible =3D "pci14e4,5f69"; + reg =3D <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address =3D [00 00 00 00 00 00]; + brcm,board-type =3D "apple,kyushu"; + }; +}; + +&i2c4 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8112-jxxx.dtsi new file mode 100644 index 000000000000..f5edf61113e7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple M2 MacBook Air/Pro (M2, 2022) + * + * This file contains parts common to all Apple M2 devices using the t8112. + * + * target-type: J493, J413 + * + * Copyright The Asahi Linux Contributors + */ + +/ { + aliases { + serial0 =3D &serial0; + serial2 =3D &serial2; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0"; + + framebuffer0: framebuffer@0 { + compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; + reg =3D <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status =3D "disabled"; + }; + }; + + memory@800000000 { + device_type =3D "memory"; + reg =3D <0x8 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status =3D "okay"; +}; + +&serial2 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + hpm0: usb-pd@38 { + compatible =3D "apple,cd321x"; + reg =3D <0x38>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + hpm1: usb-pd@3f { + compatible =3D "apple,cd321x"; + reg =3D <0x3f>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; +}; + +&i2c1 { + status =3D "okay"; +}; + +&i2c2 { + status =3D "okay"; +}; + +&i2c3 { + status =3D "okay"; +}; + +&nco_clkref { + clock-frequency =3D <900000000>; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8112-pmgr.dtsi new file mode 100644 index 000000000000..0f2d810921c8 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi @@ -0,0 +1,1141 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8112 "M2" SoC + * + * Copyright The Asahi Linux Contributors + */ + + +&pmgr { + ps_sbr: power-controller@100 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@108 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@110 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + apple,always-on; /* Core device */ + }; + + ps_soc_spmi0: power-controller@118 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "soc_spmi0"; + }; + + ps_gpio: power-controller@120 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pms_busif: power-controller@128 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_busif"; + apple,always-on; /* Core device */ + }; + + ps_pms: power-controller@130 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_pms_c1ppt: power-controller@160 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_c1ppt"; + power-domains =3D <&ps_pms>; + }; + + ps_soc_dpe: power-controller@168 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "soc_dpe"; + apple,always-on; /* Core device */ + }; + + ps_pmgr_soc_ocla: power-controller@170 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmgr_soc_ocla"; + power-domains =3D <&ps_pms>; + }; + + ps_ispsens0: power-controller@178 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens0"; + }; + + ps_ispsens1: power-controller@180 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens1"; + }; + + ps_ispsens2: power-controller@188 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens2"; + }; + + ps_ispsens3: power-controller@190 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ispsens3"; + }; + + ps_pcie_ref: power-controller@198 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_aft0: power-controller@1a0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aft0"; + }; + + ps_imx: power-controller@1a8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "imx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sio_busif: power-controller@1b0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio: power-controller@1b8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + apple,always-on; + power-domains =3D <&ps_sio_busif>; + }; + + ps_sio_cpu: power-controller@1c0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_cpu"; + power-domains =3D <&ps_sio>; + }; + + ps_fpwm0: power-controller@1c8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "fpwm0"; + power-domains =3D <&ps_sio>; + }; + + ps_fpwm1: power-controller@1d0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "fpwm1"; + power-domains =3D <&ps_sio>; + }; + + ps_fpwm2: power-controller@1d8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "fpwm2"; + power-domains =3D <&ps_sio>; + }; + + ps_i2c0: power-controller@1e0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio>; + }; + + ps_i2c1: power-controller@1e8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio>; + }; + + ps_i2c2: power-controller@1f0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio>; + }; + + ps_i2c3: power-controller@1f8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x1f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio>; + }; + + ps_i2c4: power-controller@200 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c4"; + power-domains =3D <&ps_sio>; + }; + + ps_spi_p: power-controller@208 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi_p"; + power-domains =3D <&ps_sio>; + }; + + ps_uart_p: power-controller@210 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart_p"; + power-domains =3D <&ps_sio>; + }; + + ps_audio_p: power-controller@218 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "audio_p"; + power-domains =3D <&ps_sio>; + }; + + ps_aes: power-controller@220 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aes"; + power-domains =3D <&ps_sio>; + }; + + ps_spi0: power-controller@228 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_spi_p>; + }; + + ps_spi1: power-controller@230 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_spi_p>; + }; + + ps_spi2: power-controller@238 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_spi_p>; + }; + + ps_spi3: power-controller@240 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_spi_p>; + }; + + ps_spi4: power-controller@248 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi4"; + power-domains =3D <&ps_spi_p>; + }; + + ps_spi5: power-controller@250 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi5"; + power-domains =3D <&ps_spi_p>; + }; + + ps_uart_n: power-controller@258 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart_n"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart0: power-controller@260 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart1: power-controller@268 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart2: power-controller@270 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart3: power-controller@278 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart4: power-controller@280 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart5: power-controller@288 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart6: power-controller@290 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart7: power-controller@298 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_uart_p>; + }; + + ps_uart8: power-controller@2a0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_uart_p>; + }; + + ps_sio_adma: power-controller@2a8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_adma"; + power-domains =3D <&ps_spi_p>, <&ps_audio_p>; + }; + + ps_dpa0: power-controller@2b0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dpa0"; + power-domains =3D <&ps_audio_p>; + }; + + ps_dpa1: power-controller@2b8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dpa1"; + power-domains =3D <&ps_audio_p>; + }; + + ps_mca0: power-controller@2c0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca1: power-controller@2c8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca2: power-controller@2d0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca3: power-controller@2d8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca4: power-controller@2e0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca5: power-controller@2e8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca5"; + power-domains =3D <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mcc: power-controller@2f0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory controller */ + }; + + ps_dcs0: power-controller@2f8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x2f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@300 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@308 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@310 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@318 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs4"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs5: power-controller@320 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs5"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs6: power-controller@328 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs6"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs7: power-controller@330 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs7"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_smx0: power-controller@338 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x338 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx0"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_smx1: power-controller@340 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x340 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx1"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_apcie: power-controller@348 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x348 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "apcie"; + power-domains =3D <&ps_imx>, <&ps_pcie_ref>; + }; + + ps_rmx0: power-controller@350 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x350 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rmx0"; + /* Apple Fabric, display/image stuff: this can power down */ + }; + + ps_rmx1: power-controller@358 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x358 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rmx1"; + /* Apple Fabric, display/image stuff: this can power down */ + }; + + ps_cmx: power-controller@360 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x360 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cmx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mmx: power-controller@368 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x368 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mmx"; + /* Apple Fabric, media stuff: this can power down */ + }; + + ps_disp0_sys: power-controller@370 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x370 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_sys"; + power-domains =3D <&ps_rmx1>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_disp0_fe: power-controller@378 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x378 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_fe"; + power-domains =3D <&ps_disp0_sys>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_dispext_sys: power-controller@380 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x380 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dispext_sys"; + power-domains =3D <&ps_rmx0>; + }; + + ps_dispext_fe: power-controller@388 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x388 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dispext_fe"; + power-domains =3D <&ps_dispext_sys>; + }; + + ps_dispext_cpu0: power-controller@3c8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x3c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dispext_cpu0"; + power-domains =3D <&ps_dispext_fe>; + apple,min-state =3D <4>; + }; + + ps_dptx_ext_phy: power-controller@3d8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x3d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dptx_ext_phy"; + }; + + ps_dispdfr_fe: power-controller@3e0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x3e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dispdfr_fe"; + power-domains =3D <&ps_rmx0>; + }; + + ps_dispdfr_be: power-controller@3e8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x3e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dispdfr_be"; + power-domains =3D <&ps_dispdfr_fe>; + }; + + ps_mipi_dsi: power-controller@3f0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x3f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_dispdfr_be>; + }; + + ps_jpg: power-controller@3f8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x3f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_cmx>; + }; + + ps_apcie_gp: power-controller@400 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "apcie_gp"; + power-domains =3D <&ps_apcie>; + apple,always-on; /* Breaks things if shut down */ + }; + + ps_msr: power-controller@408 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x408 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_imx>; + }; + + ps_pmp: power-controller@410 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x410 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + apple,always-on; + }; + + ps_pms_sram: power-controller@418 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x418 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + apple,always-on; + }; + + ps_msr_ase_core: power-controller@420 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x420 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr_ase_core"; + power-domains =3D <&ps_msr>; + }; + + ps_ans: power-controller@428 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x428 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ans"; + power-domains =3D <&ps_imx>; + }; + + ps_gfx: power-controller@430 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x430 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_isp_sys: power-controller@438 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x438 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sys"; + power-domains =3D <&ps_rmx1>; + }; + + ps_venc_sys: power-controller@440 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x440 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_sys"; + power-domains =3D <&ps_rmx1>; + }; + + ps_avd_sys: power-controller@448 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x448 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "avd_sys"; + power-domains =3D <&ps_mmx>; + }; + + ps_apcie_st: power-controller@450 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x450 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "apcie_st"; + power-domains =3D <&ps_apcie>, <&ps_ans>; + }; + + ps_atc0_common: power-controller@458 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x458 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc0_common"; + power-domains =3D <&ps_imx>; + }; + + ps_atc0_pcie: power-controller@460 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x460 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc0_pcie"; + power-domains =3D <&ps_atc0_common>; + }; + + ps_atc0_cio: power-controller@468 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x468 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc0_cio"; + power-domains =3D <&ps_atc0_common>; + }; + + ps_atc0_cio_pcie: power-controller@470 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x470 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc0_cio_pcie"; + power-domains =3D <&ps_atc0_cio>; + }; + + ps_atc0_cio_usb: power-controller@478 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x478 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc0_cio_usb"; + power-domains =3D <&ps_atc0_cio>; + }; + + ps_atc1_common: power-controller@480 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x480 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc1_common"; + power-domains =3D <&ps_rmx0>; + }; + + ps_atc1_pcie: power-controller@488 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x488 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc1_pcie"; + power-domains =3D <&ps_atc1_common>; + }; + + ps_atc1_cio: power-controller@490 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x490 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc1_cio"; + power-domains =3D <&ps_atc1_common>; + }; + + ps_atc1_cio_pcie: power-controller@498 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x498 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc1_cio_pcie"; + power-domains =3D <&ps_atc1_cio>; + }; + + ps_atc1_cio_usb: power-controller@4a0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x4a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc1_cio_usb"; + power-domains =3D <&ps_atc1_cio>; + }; + + ps_ane_sys: power-controller@4a8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x4a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "ane_sys"; + power-domains =3D <&ps_mmx>; + }; + + ps_scodec: power-controller@4b0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x4b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "scodec"; + power-domains =3D <&ps_rmx0>; + }; + + ps_sep: power-controller@c00 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0xc00 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; + }; + + ps_venc_dma: power-controller@8000 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x8000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_dma"; + power-domains =3D <&ps_venc_sys>; + }; + + ps_venc_pipe4: power-controller@8008 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x8008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe4"; + power-domains =3D <&ps_venc_dma>; + }; + + ps_venc_pipe5: power-controller@8010 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x8010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe5"; + power-domains =3D <&ps_venc_dma>; + }; + + ps_venc_me0: power-controller@8018 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x8018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + power-domains =3D <&ps_venc_pipe5>, <&ps_venc_pipe4>; + }; + + ps_venc_me1: power-controller@8020 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x8020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + power-domains =3D <&ps_venc_pipe5>, <&ps_venc_pipe4>; + }; + + ps_disp0_cpu0: power-controller@10000 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x10000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0_cpu0"; + power-domains =3D <&ps_disp0_fe>; + apple,min-state =3D <4>; + }; +}; + +&pmgr_mini { + + ps_debug_gated: power-controller@58 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x58 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug_gated"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_spmi0: power-controller@60 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x60 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_spmi0"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_spmi1: power-controller@68 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x68 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_spmi1"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_aon: power-controller@70 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x70 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_msg: power-controller@78 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x78 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msg"; + }; + + ps_nub_gpio: power-controller@80 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_gpio"; + apple,always-on; + }; + + ps_atc0_usb_aon: power-controller@88 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc0_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + ps_atc1_usb_aon: power-controller@90 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x90 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc1_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + ps_atc0_usb: power-controller@98 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x98 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc0_usb"; + power-domains =3D <&ps_atc0_usb_aon>, <&ps_atc0_common>; + }; + + ps_atc1_usb: power-controller@a0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0xa0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "atc1_usb"; + power-domains =3D <&ps_atc1_usb_aon>, <&ps_atc1_common>; + }; + + ps_nub_fabric: power-controller@a8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0xa8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_sram: power-controller@b0 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0xb0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "nub_sram"; + apple,always-on; /* Core AON device */ + }; + + ps_debug_switch: power-controller@b8 { + compatible =3D "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0xb8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug_switch"; + apple,always-on; /* Core AON device */ + }; +}; + diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/app= le/t8112.dtsi new file mode 100644 index 000000000000..698a436e7dac --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8112 "M2" SoC + * + * Other names: H14G + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include + +/ { + compatible =3D "apple,t8112", "apple,arm-platform"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_e0>; + }; + core1 { + cpu =3D <&cpu_e1>; + }; + core2 { + cpu =3D <&cpu_e2>; + }; + core3 { + cpu =3D <&cpu_e3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu_p0>; + }; + core1 { + cpu =3D <&cpu_p1>; + }; + core2 { + cpu =3D <&cpu_p2>; + }; + core3 { + cpu =3D <&cpu_p3>; + }; + }; + }; + + cpu_e0: cpu@0 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x0>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&ecluster_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + }; + + cpu_e1: cpu@1 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x1>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&ecluster_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + }; + + cpu_e2: cpu@2 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x2>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&ecluster_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + }; + + cpu_e3: cpu@3 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x3>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&ecluster_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + }; + + cpu_p0: cpu@10100 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10100>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&pcluster_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p>; + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + }; + + cpu_p1: cpu@10101 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10101>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&pcluster_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p>; + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + }; + + cpu_p2: cpu@10102 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10102>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&pcluster_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p>; + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + }; + + cpu_p3: cpu@10103 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10103>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + operating-points-v2 =3D <&pcluster_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p>; + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + }; + + l2_cache_0: l2-cache-0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x1000000>; + }; + }; + + ecluster_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz =3D /bits/ 64 <600000000>; + opp-level =3D <1>; + clock-latency-ns =3D <7500>; + }; + opp02 { + opp-hz =3D /bits/ 64 <912000000>; + opp-level =3D <2>; + clock-latency-ns =3D <20000>; + }; + opp03 { + opp-hz =3D /bits/ 64 <1284000000>; + opp-level =3D <3>; + clock-latency-ns =3D <22000>; + }; + opp04 { + opp-hz =3D /bits/ 64 <1752000000>; + opp-level =3D <4>; + clock-latency-ns =3D <30000>; + }; + opp05 { + opp-hz =3D /bits/ 64 <2004000000>; + opp-level =3D <5>; + clock-latency-ns =3D <35000>; + }; + opp06 { + opp-hz =3D /bits/ 64 <2256000000>; + opp-level =3D <6>; + clock-latency-ns =3D <39000>; + }; + opp07 { + opp-hz =3D /bits/ 64 <2424000000>; + opp-level =3D <7>; + clock-latency-ns =3D <53000>; + }; + }; + + pcluster_opp: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz =3D /bits/ 64 <660000000>; + opp-level =3D <1>; + clock-latency-ns =3D <9000>; + }; + opp02 { + opp-hz =3D /bits/ 64 <924000000>; + opp-level =3D <2>; + clock-latency-ns =3D <19000>; + }; + opp03 { + opp-hz =3D /bits/ 64 <1188000000>; + opp-level =3D <3>; + clock-latency-ns =3D <22000>; + }; + opp04 { + opp-hz =3D /bits/ 64 <1452000000>; + opp-level =3D <4>; + clock-latency-ns =3D <24000>; + }; + opp05 { + opp-hz =3D /bits/ 64 <1704000000>; + opp-level =3D <5>; + clock-latency-ns =3D <26000>; + }; + opp06 { + opp-hz =3D /bits/ 64 <1968000000>; + opp-level =3D <6>; + clock-latency-ns =3D <28000>; + }; + opp07 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-level =3D <7>; + clock-latency-ns =3D <30000>; + }; + opp08 { + opp-hz =3D /bits/ 64 <2400000000>; + opp-level =3D <8>; + clock-latency-ns =3D <33000>; + }; + opp09 { + opp-hz =3D /bits/ 64 <2568000000>; + opp-level =3D <9>; + clock-latency-ns =3D <34000>; + }; + opp10 { + opp-hz =3D /bits/ 64 <2724000000>; + opp-level =3D <10>; + clock-latency-ns =3D <36000>; + }; + opp11 { + opp-hz =3D /bits/ 64 <2868000000>; + opp-level =3D <11>; + clock-latency-ns =3D <41000>; + }; + opp12 { + opp-hz =3D /bits/ 64 <2988000000>; + opp-level =3D <12>; + clock-latency-ns =3D <42000>; + }; + opp13 { + opp-hz =3D /bits/ 64 <3096000000>; + opp-level =3D <13>; + clock-latency-ns =3D <44000>; + }; + opp14 { + opp-hz =3D /bits/ 64 <3204000000>; + opp-level =3D <14>; + clock-latency-ns =3D <46000>; + }; + /* Not available until CPU deep sleep is implemented */ +#if 0 + opp15 { + opp-hz =3D /bits/ 64 <3324000000>; + opp-level =3D <15>; + clock-latency-ns =3D <62000>; + turbo-mode; + }; + opp16 { + opp-hz =3D /bits/ 64 <3408000000>; + opp-level =3D <16>; + clock-latency-ns =3D <62000>; + turbo-mode; + }; + opp17 { + opp-hz =3D /bits/ 64 <3504000000>; + opp-level =3D <17>; + clock-latency-ns =3D <62000>; + turbo-mode; + }; +#endif + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&aic>; + interrupt-names =3D "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts =3D , + , + , + ; + }; + + pmu-e { + compatible =3D "apple,blizzard-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,avalanche-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + clkref: clock-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "clkref"; + }; + + /* + * This is a fabulated representation of the input clock + * to NCO since we don't know the true clock tree. + */ + nco_clkref: clock-ref-nco { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "nco_ref"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + ranges; + nonposted-mmio; + + cpufreq_e: cpufreq@210e20000 { + compatible =3D "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; + reg =3D <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells =3D <0>; + }; + + cpufreq_p: cpufreq@211e20000 { + compatible =3D "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; + reg =3D <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells =3D <0>; + }; + + sio_dart: iommu@235004000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x2 0x35004000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_sio_cpu>; + }; + + i2c0: i2c@235010000 { + compatible =3D "apple,t8112-i2c", "apple,i2c"; + reg =3D <0x2 0x35010000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + power-domains =3D <&ps_i2c0>; + status =3D "disabled"; + }; + + i2c1: i2c@235014000 { + compatible =3D "apple,t8112-i2c", "apple,i2c"; + reg =3D <0x2 0x35014000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + power-domains =3D <&ps_i2c1>; + status =3D "disabled"; + }; + + i2c2: i2c@235018000 { + compatible =3D "apple,t8112-i2c", "apple,i2c"; + reg =3D <0x2 0x35018000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + power-domains =3D <&ps_i2c2>; + status =3D "disabled"; + }; + + i2c3: i2c@23501c000 { + compatible =3D "apple,t8112-i2c", "apple,i2c"; + reg =3D <0x2 0x3501c000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c3_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + power-domains =3D <&ps_i2c3>; + status =3D "disabled"; + }; + + i2c4: i2c@235020000 { + compatible =3D "apple,t8112-i2c", "apple,i2c"; + reg =3D <0x2 0x35020000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c4_pins>; + pinctrl-names =3D "default"; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + power-domains =3D <&ps_i2c4>; + status =3D "disabled"; + }; + + serial0: serial@235200000 { + compatible =3D "apple,s5l-uart"; + reg =3D <0x2 0x35200000 0x0 0x1000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks =3D <&clkref>, <&clkref>; + clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; + status =3D "disabled"; + }; + + serial2: serial@235208000 { + compatible =3D "apple,s5l-uart"; + reg =3D <0x2 0x35208000 0x0 0x1000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clkref>, <&clkref>; + clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart2>; + status =3D "disabled"; + }; + + admac: dma-controller@238200000 { + compatible =3D "apple,t8112-admac", "apple,admac"; + reg =3D <0x2 0x38200000 0x0 0x34000>; + dma-channels =3D <24>; + interrupts-extended =3D <0>, + <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>; + #dma-cells =3D <1>; + iommus =3D <&sio_dart 2>; + power-domains =3D <&ps_sio_adma>; + resets =3D <&ps_audio_p>; + }; + + mca: i2s@238400000 { + compatible =3D "apple,t8112-mca", "apple,mca"; + reg =3D <0x2 0x38400000 0x0 0x18000>, + <0x2 0x38300000 0x0 0x30000>; + + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + ; + + resets =3D <&ps_audio_p>; + clocks =3D <&nco 0>, <&nco 1>, <&nco 2>, + <&nco 3>, <&nco 4>, <&nco 4>; + power-domains =3D <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; + dmas =3D <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, + <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, + <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; + dma-names =3D "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b", + "tx4a", "rx4a", "tx4b", "rx4b", + "tx5a", "rx5a", "tx5b", "rx5b"; + + #sound-dai-cells =3D <1>; + }; + + nco: clock-controller@23b044000 { + compatible =3D "apple,t8112-nco", "apple,nco"; + reg =3D <0x2 0x3b044000 0x0 0x14000>; + clocks =3D <&nco_clkref>; + #clock-cells =3D <1>; + }; + + aic: interrupt-controller@23b0c0000 { + compatible =3D "apple,t8112-aic", "apple,aic2"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x2 0x3b0c0000 0x0 0x8000>, + <0x2 0x3b0c8000 0x0 0x4>; + reg-names =3D "core", "event"; + power-domains =3D <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; + }; + }; + }; + + pmgr: power-management@23b700000 { + compatible =3D "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x2 0x3b700000 0 0x14000>; + /* child nodes are added in t8103-pmgr.dtsi */ + }; + + pinctrl_ap: pinctrl@23c100000 { + compatible =3D "apple,t8112-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x3c100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_ap 0 0 213>; + apple,npins =3D <213>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + + i2c0_pins: i2c0-pins { + pinmux =3D , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux =3D , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux =3D , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux =3D , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux =3D , + ; + }; + + spi3_pins: spi3-pins { + pinmux =3D , + , + , + ; + }; + + pcie_pins: pcie-pins { + pinmux =3D , + , + ; + // TODO: 1 more CLKREQs + }; + }; + + pinctrl_nub: pinctrl@23d1f0000 { + compatible =3D "apple,t8112-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x3d1f0000 0x0 0x4000>; + power-domains =3D <&ps_nub_gpio>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_nub 0 0 24>; + apple,npins =3D <24>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pmgr_mini: power-management@23d280000 { + compatible =3D "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x2 0x3d280000 0 0x4000>; + /* child nodes are added in t8103-pmgr.dtsi */ + }; + + wdt: watchdog@23d2b0000 { + compatible =3D "apple,t8112-wdt", "apple,wdt"; + reg =3D <0x2 0x3d2b0000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pinctrl_smc: pinctrl@23e820000 { + compatible =3D "apple,t8112-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x3e820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_smc 0 0 18>; + apple,npins =3D <18>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@24a820000 { + compatible =3D "apple,t8112-pinctrl", "apple,pinctrl"; + reg =3D <0x2 0x4a820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_aop 0 0 54>; + apple,npins =3D <54>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + ans_mbox: mbox@277408000 { + compatible =3D "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; + reg =3D <0x2 0x77408000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + ; + interrupt-names =3D "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells =3D <0>; + power-domains =3D <&ps_ans>; + }; + + sart: sart@27bc50000 { + compatible =3D "apple,t8112-sart", "apple,t6000-sart"; + reg =3D <0x2 0x7bc50000 0x0 0x10000>; + power-domains =3D <&ps_ans>; + }; + + nvme@27bcc0000 { + compatible =3D "apple,t8112-nvme-ans2", "apple,nvme-ans2"; + reg =3D <0x2 0x7bcc0000 0x0 0x40000>, + <0x2 0x77400000 0x0 0x4000>; + reg-names =3D "nvme", "ans"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + mboxes =3D <&ans_mbox>; + apple,sart =3D <&sart>; + power-domains =3D <&ps_ans>, <&ps_apcie_st>; + power-domain-names =3D "ans", "apcie0"; + resets =3D <&ps_ans>; + }; + + pcie0_dart: iommu@681008000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x6 0x81008000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp>; + }; + + pcie1_dart: iommu@682008000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x6 0x82008000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp>; + status =3D "disabled"; + }; + + pcie2_dart: iommu@683008000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x6 0x83008000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp>; + status =3D "disabled"; + }; + + pcie3_dart: iommu@684008000 { + compatible =3D "apple,t8110-dart"; + reg =3D <0x6 0x84008000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp>; + status =3D "disabled"; + }; + + pcie0: pcie@690000000 { + compatible =3D "apple,t8112-pcie", "apple,pcie"; + device_type =3D "pci"; + + reg =3D <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x100000>, + <0x6 0x81000000 0x0 0x4000>, + <0x6 0x82000000 0x0 0x4000>, + <0x6 0x83000000 0x0 0x4000>, + <0x6 0x84000000 0x0 0x4000>; + reg-names =3D "config", "rc", "port0", "port1", "port2", "port3"; + + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + ; + + msi-controller; + msi-parent =3D <&pcie0>; + msi-ranges =3D <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map =3D <0x100 &pcie0_dart 0 1>, + <0x200 &pcie1_dart 1 1>, + <0x300 &pcie2_dart 2 1>, + <0x400 &pcie3_dart 3 1>; + iommu-map-mask =3D <0xff00>; + + bus-range =3D <0 4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + power-domains =3D <&ps_apcie_gp>; + pinctrl-0 =3D <&pcie_pins>; + pinctrl-names =3D "default"; + + port00: pci@0,0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + reset-gpios =3D <&pinctrl_ap 166 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + }; + + port01: pci@1,0 { + device_type =3D "pci"; + reg =3D <0x800 0x0 0x0 0x0 0x0>; + reset-gpios =3D <&pinctrl_ap 167 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port01 0 0 0 0>, + <0 0 0 2 &port01 0 0 0 1>, + <0 0 0 3 &port01 0 0 0 2>, + <0 0 0 4 &port01 0 0 0 3>; + + status =3D "disabled"; + }; + + port02: pci@2,0 { + device_type =3D "pci"; + reg =3D <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios =3D <&pinctrl_ap 168 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + + status =3D "disabled"; + }; + + /* TODO: GPIO unknown */ + port03: pci@3,0 { + device_type =3D "pci"; + reg =3D <0x1800 0x0 0x0 0x0 0x0>; + //reset-gpios =3D <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + + status =3D "disabled"; + }; + }; + }; +}; + +#include "t8112-pmgr.dtsi" --=20 2.39.2