From nobody Wed Nov 13 07:52:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A8ADC38142 for ; Wed, 1 Feb 2023 02:15:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231765AbjBACP3 (ORCPT ); Tue, 31 Jan 2023 21:15:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231567AbjBACPQ (ORCPT ); Tue, 31 Jan 2023 21:15:16 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FD0F4B4B7; Tue, 31 Jan 2023 18:15:14 -0800 (PST) X-UUID: 425401a6a1d611eda06fc9ecc4dadd91-20230201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=AljLcemnKAdfrmjxC/s2CRMhH5DsQc4QT4V+1YYAYTU=; b=u0YmEQ/SvwqgDUH5J7kmK9g/HnYgub8R/uzE9WIekZBS70LHyC3Dc7XwksNEwOTon1V3Rpxv9be7eqEga1sdtl9uzk+s73B4BJNKo1RKIGXAGCGqf4d29U+u+ar/9BdRpWZ+SYgE1jjDYf7qWTyvk6uVrmDUVvekIjiuuF5gyic=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:88bb11f6-fb0f-4374-8656-fe80549b035b,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:3ca2d6b,CLOUDID:9f3a14f7-ff42-4fb0-b929-626456a83c14,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: 425401a6a1d611eda06fc9ecc4dadd91-20230201 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 453412885; Wed, 01 Feb 2023 10:15:12 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 1 Feb 2023 10:15:11 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 1 Feb 2023 10:15:09 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Xiangsheng Hou , , , , , , , , AngeloGioacchino Del Regno Subject: [PATCH v6 5/5] mtd: nand: ecc-mtk: Add ECC support fot MT7986 IC Date: Wed, 1 Feb 2023 10:15:00 +0800 Message-ID: <20230201021500.26769-6-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201021500.26769-1-xiangsheng.hou@mediatek.com> References: <20230201021500.26769-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ECC support fot MT7986 IC, and change err_mask value with GENMASK macro. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- drivers/mtd/nand/ecc-mtk.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/ecc-mtk.c b/drivers/mtd/nand/ecc-mtk.c index 9f9b201fe706..c75bb8b80cc1 100644 --- a/drivers/mtd/nand/ecc-mtk.c +++ b/drivers/mtd/nand/ecc-mtk.c @@ -40,6 +40,10 @@ #define ECC_IDLE_REG(op) ((op) =3D=3D ECC_ENCODE ? ECC_ENCIDLE : ECC_DECID= LE) #define ECC_CTL_REG(op) ((op) =3D=3D ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) =20 +#define ECC_ERRMASK_MT7622 GENMASK(4, 0) +#define ECC_ERRMASK_MT2701 GENMASK(5, 0) +#define ECC_ERRMASK_MT2712 GENMASK(6, 0) + struct mtk_ecc_caps { u32 err_mask; u32 err_shift; @@ -79,6 +83,10 @@ static const u8 ecc_strength_mt7622[] =3D { 4, 6, 8, 10, 12 }; =20 +static const u8 ecc_strength_mt7986[] =3D { + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 +}; + enum mtk_ecc_regs { ECC_ENCPAR00, ECC_ENCIRQ_EN, @@ -451,7 +459,7 @@ unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ec= c) EXPORT_SYMBOL(mtk_ecc_get_parity_bits); =20 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 =3D { - .err_mask =3D 0x3f, + .err_mask =3D ECC_ERRMASK_MT2701, .err_shift =3D 8, .ecc_strength =3D ecc_strength_mt2701, .ecc_regs =3D mt2701_ecc_regs, @@ -462,7 +470,7 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = =3D { }; =20 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 =3D { - .err_mask =3D 0x7f, + .err_mask =3D ECC_ERRMASK_MT2712, .err_shift =3D 8, .ecc_strength =3D ecc_strength_mt2712, .ecc_regs =3D mt2712_ecc_regs, @@ -473,7 +481,7 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = =3D { }; =20 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 =3D { - .err_mask =3D 0x1f, + .err_mask =3D ECC_ERRMASK_MT7622, .err_shift =3D 5, .ecc_strength =3D ecc_strength_mt7622, .ecc_regs =3D mt7622_ecc_regs, @@ -483,6 +491,17 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = =3D { .pg_irq_sel =3D 0, }; =20 +static const struct mtk_ecc_caps mtk_ecc_caps_mt7986 =3D { + .err_mask =3D ECC_ERRMASK_MT7622, + .err_shift =3D 8, + .ecc_strength =3D ecc_strength_mt7986, + .ecc_regs =3D mt2712_ecc_regs, + .num_ecc_strength =3D 11, + .ecc_mode_shift =3D 5, + .parity_bits =3D 14, + .pg_irq_sel =3D 1, +}; + static const struct of_device_id mtk_ecc_dt_match[] =3D { { .compatible =3D "mediatek,mt2701-ecc", @@ -493,6 +512,9 @@ static const struct of_device_id mtk_ecc_dt_match[] =3D= { }, { .compatible =3D "mediatek,mt7622-ecc", .data =3D &mtk_ecc_caps_mt7622, + }, { + .compatible =3D "mediatek,mt7986-ecc", + .data =3D &mtk_ecc_caps_mt7986, }, {}, }; --=20 2.25.1