From nobody Wed Nov 13 07:48:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA217C636D7 for ; Wed, 1 Feb 2023 02:15:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231653AbjBACPT (ORCPT ); Tue, 31 Jan 2023 21:15:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229819AbjBACPO (ORCPT ); Tue, 31 Jan 2023 21:15:14 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F11B44861D; Tue, 31 Jan 2023 18:15:09 -0800 (PST) X-UUID: 3eb28d7ea1d611eda06fc9ecc4dadd91-20230201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=JiJwE5UUxcQWEg2lrPPyx/7rePuDQC4iqJtfGYtutHY=; b=qILshXbKI3dY6nBDI01Zxa6boWnRfjOi0QuhyNfvk0Bs5F2BhS6FTeCalF2q+mrm9IQjciDFIayC6CqiVlRawJ37Docg3GgTCiyxhvtj8jQmvY8aJak8l04f6i2LrhOT/U6up8kQAdZw/5C0zek6LLnxToTouQGG7shD2AGTIwY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:6d7dfb0a-ac10-4651-9d18-4b1f805f6ddf,IP:0,U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.18,REQID:6d7dfb0a-ac10-4651-9d18-4b1f805f6ddf,IP:0,URL :25,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:3ca2d6b,CLOUDID:dc39858d-8530-4eff-9f77-222cf6e2895b,B ulkID:2302011015074YT7RQ9R,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,CO L:0,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: 3eb28d7ea1d611eda06fc9ecc4dadd91-20230201 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1200830852; Wed, 01 Feb 2023 10:15:06 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 1 Feb 2023 10:15:05 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 1 Feb 2023 10:15:04 +0800 From: Xiangsheng Hou To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Xiangsheng Hou , , , , , , , , Krzysztof Kozlowski , kernel test robot Subject: [PATCH v6 1/5] dt-bindings: mtd: Split ECC engine with rawnand controller Date: Wed, 1 Feb 2023 10:14:56 +0800 Message-ID: <20230201021500.26769-2-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201021500.26769-1-xiangsheng.hou@mediatek.com> References: <20230201021500.26769-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Split MediaTek ECC engine with rawnand controller and convert to YAML schema. Signed-off-by: Xiangsheng Hou Reviewed-by: Krzysztof Kozlowski Reported-by: kernel test robot --- .../bindings/mtd/mediatek,mtk-nfc.yaml | 155 +++++++++++++++ .../mtd/mediatek,nand-ecc-engine.yaml | 62 ++++++ .../devicetree/bindings/mtd/mtk-nand.txt | 176 ------------------ MAINTAINERS | 2 +- 4 files changed, 218 insertions(+), 177 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.= yaml create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,nand-ecc= -engine.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml b/= Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml new file mode 100644 index 000000000000..a6e7f123eda7 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC) + +maintainers: + - Xiangsheng Hou + +properties: + compatible: + enum: + - mediatek,mt2701-nfc + - mediatek,mt2712-nfc + - mediatek,mt7622-nfc + + reg: + items: + - description: Base physical address and size of NFI. + + interrupts: + items: + - description: NFI interrupt + + clocks: + items: + - description: clock used for the controller + - description: clock used for the pad + + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + ecc-engine: + description: device-tree node of the required ECC engine. + $ref: /schemas/types.yaml#/definitions/phandle + +patternProperties: + "^nand@[a-f0-9]$": + $ref: nand-chip.yaml# + unevaluatedProperties: false + properties: + reg: + maximum: 1 + nand-on-flash-bbt: true + nand-ecc-mode: + const: hw + +allOf: + - $ref: nand-controller.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt2701-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-step-size: + enum: [ 512, 1024 ] + nand-ecc-strength: + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, + 40, 44, 48, 52, 56, 60] + + - if: + properties: + compatible: + contains: + const: mediatek,mt2712-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-step-size: + enum: [ 512, 1024 ] + nand-ecc-strength: + enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, + 40, 44, 48, 52, 56, 60, 68, 72, 80] + + - if: + properties: + compatible: + contains: + const: mediatek,mt7622-nfc + then: + patternProperties: + "^nand@[a-f0-9]$": + properties: + nand-ecc-step-size: + const: 512 + nand-ecc-strength: + enum: [4, 6, 8, 10, 12] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ecc-engine + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + nand-controller@1100d000 { + compatible =3D "mediatek,mt2701-nfc"; + reg =3D <0 0x1100d000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI>, + <&pericfg CLK_PERI_NFI_PAD>; + clock-names =3D "nfi_clk", "pad_clk"; + ecc-engine =3D <&bch>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nand@0 { + reg =3D <0>; + + nand-on-flash-bbt; + nand-ecc-mode =3D "hw"; + nand-ecc-step-size =3D <1024>; + nand-ecc-strength =3D <24>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + preloader@0 { + label =3D "pl"; + read-only; + reg =3D <0x0 0x400000>; + }; + android@400000 { + label =3D "android"; + reg =3D <0x400000 0x12c00000>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine= .yaml b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml new file mode 100644 index 000000000000..b13d801eda76 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek(MTK) SoCs NAND ECC engine + +maintainers: + - Xiangsheng Hou + +description: | + MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. + +properties: + compatible: + enum: + - mediatek,mt2701-ecc + - mediatek,mt2712-ecc + - mediatek,mt7622-ecc + + reg: + items: + - description: Base physical address and size of ECC. + + interrupts: + items: + - description: ECC interrupt + + clocks: + maxItems: 1 + + clock-names: + const: nfiecc_clk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + bch: ecc@1100e000 { + compatible =3D "mediatek,mt2701-ecc"; + reg =3D <0 0x1100e000 0 0x1000>; + interrupts =3D ; + clocks =3D <&pericfg CLK_PERI_NFI_ECC>; + clock-names =3D "nfiecc_clk"; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documenta= tion/devicetree/bindings/mtd/mtk-nand.txt deleted file mode 100644 index 839ea2f93d04..000000000000 --- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt +++ /dev/null @@ -1,176 +0,0 @@ -MTK SoCs NAND FLASH controller (NFC) DT binding - -This file documents the device tree bindings for MTK SoCs NAND controllers. -The functional split of the controller requires two drivers to operate: -the nand controller interface driver and the ECC engine driver. - -The hardware description for both devices must be captured as device -tree nodes. - -1) NFC NAND Controller Interface (NFI): -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The first part of NFC is NAND Controller Interface (NFI) HW. -Required NFI properties: -- compatible: Should be one of - "mediatek,mt2701-nfc", - "mediatek,mt2712-nfc", - "mediatek,mt7622-nfc". -- reg: Base physical address and size of NFI. -- interrupts: Interrupts of NFI. -- clocks: NFI required clocks. -- clock-names: NFI clocks internal name. -- ecc-engine: Required ECC Engine node. -- #address-cells: NAND chip index, should be 1. -- #size-cells: Should be 0. - -Example: - - nandc: nfi@1100d000 { - compatible =3D "mediatek,mt2701-nfc"; - reg =3D <0 0x1100d000 0 0x1000>; - interrupts =3D ; - clocks =3D <&pericfg CLK_PERI_NFI>, - <&pericfg CLK_PERI_NFI_PAD>; - clock-names =3D "nfi_clk", "pad_clk"; - ecc-engine =3D <&bch>; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - -Platform related properties, should be set in {platform_name}.dts: -- children nodes: NAND chips. - -Children nodes properties: -- reg: Chip Select Signal, default 0. - Set as reg =3D <0>, <1> when need 2 CS. -Optional: -- nand-on-flash-bbt: Store BBT on NAND Flash. -- nand-ecc-mode: the NAND ecc mode (check driver for supported modes) -- nand-ecc-step-size: Number of data bytes covered by a single ECC step. - valid values: - 512 and 1024 on mt2701 and mt2712. - 512 only on mt7622. - 1024 is recommended for large page NANDs. -- nand-ecc-strength: Number of bits to correct per ECC step. - The valid values that each controller supports: - mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60. - mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, - 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80. - mt7622: 4, 6, 8, 10, 12, 14, 16. - The strength should be calculated as follows: - E =3D (S - F) * 8 / B - S =3D O / (P / Q) - E : nand-ecc-strength. - S : spare size per sector. - F : FDM size, should be in the range [1,8]. - It is used to store free oob data. - O : oob size. - P : page size. - Q : nand-ecc-step-size. - B : number of parity bits needed to correct - 1 bitflip. - According to MTK NAND controller design, - this number depends on max ecc step size - that MTK NAND controller supports. - If max ecc step size supported is 1024, - then it should be always 14. And if max - ecc step size is 512, then it should be - always 13. - If the result does not match any one of the listed - choices above, please select the smaller valid value from - the list. - (otherwise the driver will do the adjustment at runtime) -- pinctrl-names: Default NAND pin GPIO setting name. -- pinctrl-0: GPIO setting node. - -Example: - &pio { - nand_pins_default: nanddefault { - pins_dat { - pinmux =3D , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength =3D ; - bias-pull-up; - }; - - pins_we { - pinmux =3D ; - drive-strength =3D ; - bias-pull-up =3D ; - }; - - pins_ale { - pinmux =3D ; - drive-strength =3D ; - bias-pull-down =3D ; - }; - }; - }; - - &nandc { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&nand_pins_default>; - nand@0 { - reg =3D <0>; - nand-on-flash-bbt; - nand-ecc-mode =3D "hw"; - nand-ecc-strength =3D <24>; - nand-ecc-step-size =3D <1024>; - }; - }; - -NAND chip optional subnodes: -- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml - -Example: - nand@0 { - partitions { - compatible =3D "fixed-partitions"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - preloader@0 { - label =3D "pl"; - read-only; - reg =3D <0x00000000 0x00400000>; - }; - android@00400000 { - label =3D "android"; - reg =3D <0x00400000 0x12c00000>; - }; - }; - }; - -2) ECC Engine: -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -Required BCH properties: -- compatible: Should be one of - "mediatek,mt2701-ecc", - "mediatek,mt2712-ecc", - "mediatek,mt7622-ecc". -- reg: Base physical address and size of ECC. -- interrupts: Interrupts of ECC. -- clocks: ECC required clocks. -- clock-names: ECC clocks internal name. - -Example: - - bch: ecc@1100e000 { - compatible =3D "mediatek,mt2701-ecc"; - reg =3D <0 0x1100e000 0 0x1000>; - interrupts =3D ; - clocks =3D <&pericfg CLK_PERI_NFI_ECC>; - clock-names =3D "nfiecc_clk"; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 263d37a129b1..6994757da949 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13088,7 +13088,7 @@ F: drivers/phy/ralink/phy-mt7621-pci.c MEDIATEK NAND CONTROLLER DRIVER L: linux-mtd@lists.infradead.org S: Orphan -F: Documentation/devicetree/bindings/mtd/mtk-nand.txt +F: Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml F: drivers/mtd/nand/raw/mtk_* =20 MEDIATEK PMIC LED DRIVER --=20 2.25.1