From nobody Sun Sep 14 03:05:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE22EC38142 for ; Tue, 31 Jan 2023 23:45:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230268AbjAaXpB (ORCPT ); Tue, 31 Jan 2023 18:45:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229907AbjAaXo5 (ORCPT ); Tue, 31 Jan 2023 18:44:57 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E70B74C6EF; Tue, 31 Jan 2023 15:44:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675208696; x=1706744696; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RJlwSFVpT1cewwIwRvUfBxfg5OygWbxR/zFOIt+ZgzQ=; b=H0Bz/4BMZ9c6loNizuD1/ey0E+v97kR7DYOxwAXEwSIoyWb7GoljGFlC 9Crv29lOZ+4h3JeIfuNnq3w25PNhjF5CGpLje1iTJmbJWN5XdBC+qtqdD 9bzn7W7ckOSFosGVEJcZcQOpAvNtL2sC5vsok0g0Emn5k9Qna1Gu8l/wu VQv/Nq40EpUJFwDrNCc8RL7Z9IlhJFQ8NQ6J9iTuVtNcnQSnUbPaAIoGr eCsWj62EyRYxlQf5d4cdQuYQPakChQgrct7hrv/x2UVV6lwjT7YUCw5co C7E6OpzDr9AQTI1MkJcVrjlFWpShm8qt5o3z4ENbIGzgQY4Iuy0hWThJh A==; X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="390360415" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="390360415" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="773192024" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="773192024" Received: from jithujos.sc.intel.com ([172.25.103.66]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 From: Jithu Joseph To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH 1/5] x86/include/asm/msr-index.h: Add IFS Array test bits Date: Tue, 31 Jan 2023 15:42:58 -0800 Message-Id: <20230131234302.3997223-2-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230131234302.3997223-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Define MSR bitfields for enumerating support for Array BIST test. Signed-off-by: Jithu Joseph Reviewed-by: Tony Luck --- arch/x86/include/asm/msr-index.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index d3fe82c5d6b6..ad8997773ad3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -197,6 +197,8 @@ =20 /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ #define MSR_INTEGRITY_CAPS 0x000002d9 +#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 +#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRA= Y_BIST_BIT) #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_B= IST_BIT) =20 --=20 2.25.1 From nobody Sun Sep 14 03:05:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBE73C636D3 for ; Tue, 31 Jan 2023 23:45:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230366AbjAaXpE (ORCPT ); Tue, 31 Jan 2023 18:45:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230011AbjAaXo6 (ORCPT ); Tue, 31 Jan 2023 18:44:58 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B8744DE03; Tue, 31 Jan 2023 15:44:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675208697; x=1706744697; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mvhv6zkaH9H97cKt0p0n94x4bwBzoDv9AW5TNmZ4ZsU=; b=T+/5KMmazvK4W1YlOvzqkYJ9oBt8KMXf/DCduU0FCxDTrUIdfJ6KjiZ8 plEmjFj5n75xDgcb1QF/ypZIIVWE6NY5m4/Xx1fH3qtm0eUUyKDfGSmtJ ISUpjFpVvJ1jhwRvwgu6ChzQqzyTmkgh3LagLKnNg/+f3yKZ8GPjfSKR2 xWkBJfP5fysz2A71BONdA403MMeRZk3K9Eft39nW5ncqKAFr9k11pVqhX n+s7CvHpiDn3MDg0pmdc7XWag66psftJY9dHoVLeD/agItXDj7JhzDH5t mm9RaqvwSmmx+Y/Bpd5BCAzjWyfLugPNyRHe9Wz4+Em1qxdT91RjiW5CY A==; X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="390360422" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="390360422" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="773192027" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="773192027" Received: from jithujos.sc.intel.com ([172.25.103.66]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 From: Jithu Joseph To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH 2/5] platform/x86/intel/ifs: Introduce Array Scan test to IFS Date: Tue, 31 Jan 2023 15:42:59 -0800 Message-Id: <20230131234302.3997223-3-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230131234302.3997223-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Array BIST is a new type of core test introduced under the Intel Infield Scan (IFS) suite of tests. Emerald Rapids (EMR) is the first CPU to support Array BIST. Array BIST performs tests on some portions of the core logic such as caches and register files. These are different portions of the silicon compared to the parts tested by the first test type i.e Scan at Field (SAF). Make changes in the device driver init flow to register this new test type with the device driver framework. Each test will have its own sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to accommodate for the differences in test type and how they are initiated. Upcoming patches will add actual support. Signed-off-by: Jithu Joseph Reviewed-by: Tony Luck --- drivers/platform/x86/intel/ifs/ifs.h | 5 ++ drivers/platform/x86/intel/ifs/core.c | 70 ++++++++++++++++++--------- 2 files changed, 52 insertions(+), 23 deletions(-) diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/in= tel/ifs/ifs.h index 046e39304fd5..2cef88a88aa9 100644 --- a/drivers/platform/x86/intel/ifs/ifs.h +++ b/drivers/platform/x86/intel/ifs/ifs.h @@ -137,6 +137,11 @@ #define SCAN_TEST_PASS 1 #define SCAN_TEST_FAIL 2 =20 +enum test_types { + IFS_SAF, + IFS_ARRAY, +}; + /* MSR_SCAN_HASHES_STATUS bit fields */ union ifs_scan_hashes_status { u64 data; diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/i= ntel/ifs/core.c index 206a617c2e02..ab234620ef4c 100644 --- a/drivers/platform/x86/intel/ifs/core.c +++ b/drivers/platform/x86/intel/ifs/core.c @@ -16,27 +16,44 @@ =20 static const struct x86_cpu_id ifs_cpu_ids[] __initconst =3D { X86_MATCH(SAPPHIRERAPIDS_X), + X86_MATCH(EMERALDRAPIDS_X), {} }; MODULE_DEVICE_TABLE(x86cpu, ifs_cpu_ids); =20 -static struct ifs_device ifs_device =3D { - .data =3D { - .integrity_cap_bit =3D MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT, - .test_num =3D 0, +static struct ifs_device ifs_devices[] =3D { + [IFS_SAF] =3D { + .data =3D { + .integrity_cap_bit =3D MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT, + .test_num =3D IFS_SAF, + }, + .misc =3D { + .name =3D "intel_ifs_0", + .nodename =3D "intel_ifs/0", + .minor =3D MISC_DYNAMIC_MINOR, + }, }, - .misc =3D { - .name =3D "intel_ifs_0", - .nodename =3D "intel_ifs/0", - .minor =3D MISC_DYNAMIC_MINOR, + [IFS_ARRAY] =3D { + .data =3D { + .integrity_cap_bit =3D MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT, + .test_num =3D IFS_ARRAY, + }, + .misc =3D { + .name =3D "intel_ifs_1", + .nodename =3D "intel_ifs/1", + .minor =3D MISC_DYNAMIC_MINOR, + }, }, }; =20 +#define IFS_NUMTESTS ARRAY_SIZE(ifs_devices) + static int __init ifs_init(void) { const struct x86_cpu_id *m; + int ndevices =3D 0; u64 msrval; - int ret; + int i; =20 m =3D x86_match_cpu(ifs_cpu_ids); if (!m) @@ -51,28 +68,35 @@ static int __init ifs_init(void) if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval)) return -ENODEV; =20 - ifs_device.misc.groups =3D ifs_get_groups(); - - if (!(msrval & BIT(ifs_device.data.integrity_cap_bit))) - return -ENODEV; + for (i =3D 0; i < IFS_NUMTESTS; i++) { + if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit))) + continue; =20 - ifs_device.data.pkg_auth =3D kmalloc_array(topology_max_packages(), sizeo= f(bool), GFP_KERNEL); - if (!ifs_device.data.pkg_auth) - return -ENOMEM; + ifs_devices[i].data.pkg_auth =3D kmalloc_array(topology_max_packages(), + sizeof(bool), GFP_KERNEL); + if (!ifs_devices[i].data.pkg_auth) + continue; + ifs_devices[i].misc.groups =3D ifs_get_groups(); =20 - ret =3D misc_register(&ifs_device.misc); - if (ret) { - kfree(ifs_device.data.pkg_auth); - return ret; + if (misc_register(&ifs_devices[i].misc)) + kfree(ifs_devices[i].data.pkg_auth); + else + ndevices++; } =20 - return 0; + return ndevices ? 0 : -ENODEV; } =20 static void __exit ifs_exit(void) { - misc_deregister(&ifs_device.misc); - kfree(ifs_device.data.pkg_auth); + int i; + + for (i =3D 0; i < IFS_NUMTESTS; i++) { + if (ifs_devices[i].misc.this_device) { + misc_deregister(&ifs_devices[i].misc); + kfree(ifs_devices[i].data.pkg_auth); + } + } } =20 module_init(ifs_init); --=20 2.25.1 From nobody Sun Sep 14 03:05:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02662C636CC for ; Tue, 31 Jan 2023 23:45:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230411AbjAaXpG (ORCPT ); Tue, 31 Jan 2023 18:45:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230200AbjAaXo7 (ORCPT ); Tue, 31 Jan 2023 18:44:59 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A56E32B619; Tue, 31 Jan 2023 15:44:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675208697; x=1706744697; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f9j1tac3fXJ7zWWtJKdbIWJZZUO6h9XAWqOwYcAGIU0=; b=AORAxdgr/PRbTMMk44zmmftLJ1g4sXfqXgsCD+1C4NWYy4w+HI5lHxEV PmMfIqBtcBTzeLobgnVtcqrqj3U28pwx6u0dxm2oprmUInq5U1jdn4fFR 0BS+nf9x/jgtMgEc5fSO1f8IrhAUBl/s5iTj8oirNYnsbGZxJAOlvjrB0 iXZd/QnBbOYkCJng5jFbqH/HwuT6erC2JlYeaHpju39OxxgwtTifo5r/t lrPzSaMianq/38kXgGxS+k3JZUoG/q3a979Sc6mFkK+I3GrXBc4b7vKxw oTopSfR6fghtgNxksMl7NaINMAuUpG7bv3lnxQTUqckTpydC97uJfK5gQ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="390360430" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="390360430" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="773192030" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="773192030" Received: from jithujos.sc.intel.com ([172.25.103.66]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 From: Jithu Joseph To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH 3/5] platform/x86/intel/ifs: Sysfs interface for Array BIST Date: Tue, 31 Jan 2023 15:43:00 -0800 Message-Id: <20230131234302.3997223-4-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230131234302.3997223-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The interface to trigger Array BIST test and obtain its result is similar to the existing scan test. The only notable difference is that, Array BIST doesn't require any test content to be loaded. So binary load related options are not needed for this test. Add sysfs interface array BIST test, the testing support will be added by subsequent patch. Signed-off-by: Jithu Joseph Reviewed-by: Tony Luck --- drivers/platform/x86/intel/ifs/ifs.h | 1 + drivers/platform/x86/intel/ifs/core.c | 18 +++++++++++++----- drivers/platform/x86/intel/ifs/runtest.c | 11 ++++++++++- drivers/platform/x86/intel/ifs/sysfs.c | 17 ++++++++++++++++- 4 files changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/in= tel/ifs/ifs.h index 2cef88a88aa9..07423bc4e368 100644 --- a/drivers/platform/x86/intel/ifs/ifs.h +++ b/drivers/platform/x86/intel/ifs/ifs.h @@ -249,5 +249,6 @@ static inline struct ifs_data *ifs_get_data(struct devi= ce *dev) int ifs_load_firmware(struct device *dev); int do_core_test(int cpu, struct device *dev); const struct attribute_group **ifs_get_groups(void); +const struct attribute_group **ifs_get_array_groups(void); =20 #endif diff --git a/drivers/platform/x86/intel/ifs/core.c b/drivers/platform/x86/i= ntel/ifs/core.c index ab234620ef4c..2b7a49fd473d 100644 --- a/drivers/platform/x86/intel/ifs/core.c +++ b/drivers/platform/x86/intel/ifs/core.c @@ -25,6 +25,7 @@ static struct ifs_device ifs_devices[] =3D { [IFS_SAF] =3D { .data =3D { .integrity_cap_bit =3D MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT, + .pkg_auth =3D NULL, .test_num =3D IFS_SAF, }, .misc =3D { @@ -36,6 +37,7 @@ static struct ifs_device ifs_devices[] =3D { [IFS_ARRAY] =3D { .data =3D { .integrity_cap_bit =3D MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT, + .pkg_auth =3D NULL, .test_num =3D IFS_ARRAY, }, .misc =3D { @@ -72,11 +74,17 @@ static int __init ifs_init(void) if (!(msrval & BIT(ifs_devices[i].data.integrity_cap_bit))) continue; =20 - ifs_devices[i].data.pkg_auth =3D kmalloc_array(topology_max_packages(), - sizeof(bool), GFP_KERNEL); - if (!ifs_devices[i].data.pkg_auth) - continue; - ifs_devices[i].misc.groups =3D ifs_get_groups(); + switch (ifs_devices[i].data.test_num) { + case IFS_SAF: + ifs_devices[i].data.pkg_auth =3D kmalloc_array(topology_max_packages(), + sizeof(bool), GFP_KERNEL); + if (!ifs_devices[i].data.pkg_auth) + continue; + ifs_devices[i].misc.groups =3D ifs_get_groups(); + break; + case IFS_ARRAY: + ifs_devices[i].misc.groups =3D ifs_get_array_groups(); + } =20 if (misc_register(&ifs_devices[i].misc)) kfree(ifs_devices[i].data.pkg_auth); diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x8= 6/intel/ifs/runtest.c index 0bfd8fcdd7e8..65e08af70994 100644 --- a/drivers/platform/x86/intel/ifs/runtest.c +++ b/drivers/platform/x86/intel/ifs/runtest.c @@ -236,6 +236,7 @@ static void ifs_test_core(int cpu, struct device *dev) */ int do_core_test(int cpu, struct device *dev) { + struct ifs_data *ifsd =3D ifs_get_data(dev); int ret =3D 0; =20 /* Prevent CPUs from being taken offline during the scan test */ @@ -247,7 +248,15 @@ int do_core_test(int cpu, struct device *dev) goto out; } =20 - ifs_test_core(cpu, dev); + switch (ifsd->test_num) { + case IFS_SAF: + ifs_test_core(cpu, dev); + break; + case IFS_ARRAY: + default: + return -EINVAL; + } + out: cpus_read_unlock(); return ret; diff --git a/drivers/platform/x86/intel/ifs/sysfs.c b/drivers/platform/x86/= intel/ifs/sysfs.c index ee636a76b083..7cf32184ce6a 100644 --- a/drivers/platform/x86/intel/ifs/sysfs.c +++ b/drivers/platform/x86/intel/ifs/sysfs.c @@ -75,7 +75,7 @@ static ssize_t run_test_store(struct device *dev, if (down_interruptible(&ifs_sem)) return -EINTR; =20 - if (!ifsd->loaded) + if (ifsd->test_num !=3D IFS_ARRAY && !ifsd->loaded) rc =3D -EPERM; else rc =3D do_core_test(cpu, dev); @@ -156,3 +156,18 @@ const struct attribute_group **ifs_get_groups(void) { return plat_ifs_groups; } + +/* global array sysfs attributes */ +static struct attribute *plat_ifs_array_attrs[] =3D { + &dev_attr_details.attr, + &dev_attr_status.attr, + &dev_attr_run_test.attr, + NULL +}; + +ATTRIBUTE_GROUPS(plat_ifs_array); + +const struct attribute_group **ifs_get_array_groups(void) +{ + return plat_ifs_array_groups; +} --=20 2.25.1 From nobody Sun Sep 14 03:05:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA4CFC636CC for ; Tue, 31 Jan 2023 23:45:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230444AbjAaXpJ (ORCPT ); Tue, 31 Jan 2023 18:45:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230213AbjAaXo7 (ORCPT ); Tue, 31 Jan 2023 18:44:59 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 276804C6EF; Tue, 31 Jan 2023 15:44:58 -0800 (PST) DKIM-Signature: v=1; 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d="scan'208";a="773192033" Received: from jithujos.sc.intel.com ([172.25.103.66]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 From: Jithu Joseph To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH 4/5] platform/x86/intel/ifs: Implement Array BIST test Date: Tue, 31 Jan 2023 15:43:01 -0800 Message-Id: <20230131234302.3997223-5-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230131234302.3997223-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Array BIST test (for a particlular core) is triggered by writing to MSR_ARRAY_BIST from one sibling of the core. This will initiate a test for all supported arrays on that CPU. Array BIST test may be aborted before completing all the arrays in the event of an interrupt or other reasons. In this case, kernel will restart the test from that point onwards. Array test will also be aborted when the test fails, in which case the test is stopped immediately without further retry. Signed-off-by: Jithu Joseph Reviewed-by: Tony Luck --- drivers/platform/x86/intel/ifs/ifs.h | 12 ++++ drivers/platform/x86/intel/ifs/runtest.c | 92 ++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/in= tel/ifs/ifs.h index 07423bc4e368..b1a997e39216 100644 --- a/drivers/platform/x86/intel/ifs/ifs.h +++ b/drivers/platform/x86/intel/ifs/ifs.h @@ -127,6 +127,7 @@ #include #include =20 +#define MSR_ARRAY_BIST 0x00000105 #define MSR_COPY_SCAN_HASHES 0x000002c2 #define MSR_SCAN_HASHES_STATUS 0x000002c3 #define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4 @@ -194,6 +195,17 @@ union ifs_status { }; }; =20 +/* MSR_ARRAY_BIST bit fields */ +union ifs_array { + u64 data; + struct { + u32 array_bitmask :32; + u32 array_bank :16; + u32 rsvd :15; + u32 ctrl_result :1; + }; +}; + /* * Driver populated error-codes * 0xFD: Test timed out before completing all the chunks. diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x8= 6/intel/ifs/runtest.c index 65e08af70994..ec0ceb6b5890 100644 --- a/drivers/platform/x86/intel/ifs/runtest.c +++ b/drivers/platform/x86/intel/ifs/runtest.c @@ -229,6 +229,96 @@ static void ifs_test_core(int cpu, struct device *dev) } } =20 +#define SPINUNIT 100 /* 100 nsec */ +static atomic_t array_cpus_out; + +/* + * Simplified cpu sibling rendezvous loop based on microcode loader __wait= _for_cpus() + */ +static void wait_for_sibling_cpu(atomic_t *t, long long timeout) +{ + int cpu =3D smp_processor_id(); + const struct cpumask *smt_mask =3D cpu_smt_mask(cpu); + int all_cpus =3D cpumask_weight(smt_mask); + + atomic_inc(t); + while (atomic_read(t) < all_cpus) { + if (timeout < SPINUNIT) + return; + ndelay(SPINUNIT); + timeout -=3D SPINUNIT; + touch_nmi_watchdog(); + } +} + +static int do_array_test(void *data) +{ + int cpu =3D smp_processor_id(); + u64 *msrs =3D data; + int first; + + /* + * Only one logical CPU on a core needs to trigger the Array test via MSR= write. + */ + first =3D cpumask_first(cpu_smt_mask(cpu)); + + if (cpu =3D=3D first) { + wrmsrl(MSR_ARRAY_BIST, msrs[0]); + /* Pass back the result of the test */ + rdmsrl(MSR_ARRAY_BIST, msrs[1]); + } + + /* Tests complete faster if the sibling is spinning here */ + wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC); + + return 0; +} + +static void ifs_array_test_core(int cpu, struct device *dev) +{ + union ifs_array activate, status; + bool timed_out =3D false; + struct ifs_data *ifsd; + unsigned long timeout; + u64 msrvals[2]; + + ifsd =3D ifs_get_data(dev); + + activate.data =3D 0; + activate.array_bitmask =3D ~0U; + activate.ctrl_result =3D 0; + timeout =3D jiffies + HZ / 2; + + do { + if (time_after(jiffies, timeout)) { + timed_out =3D true; + break; + } + + msrvals[0] =3D activate.data; + + atomic_set(&array_cpus_out, 0); + stop_core_cpuslocked(cpu, do_array_test, msrvals); + status.data =3D msrvals[1]; + + if (status.ctrl_result) + break; + + activate.array_bitmask =3D status.array_bitmask; + activate.array_bank =3D status.array_bank; + + } while (status.array_bitmask); + + ifsd->scan_details =3D status.data; + + if (status.ctrl_result) + ifsd->status =3D SCAN_TEST_FAIL; + else if (timed_out || status.array_bitmask) + ifsd->status =3D SCAN_NOT_TESTED; + else + ifsd->status =3D SCAN_TEST_PASS; +} + /* * Initiate per core test. It wakes up work queue threads on the target cp= u and * its sibling cpu. Once all sibling threads wake up, the scan test gets e= xecuted and @@ -253,6 +343,8 @@ int do_core_test(int cpu, struct device *dev) ifs_test_core(cpu, dev); break; case IFS_ARRAY: + ifs_array_test_core(cpu, dev); + break; default: return -EINVAL; } --=20 2.25.1 From nobody Sun Sep 14 03:05:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF209C636CC for ; Tue, 31 Jan 2023 23:45:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230496AbjAaXpL (ORCPT ); Tue, 31 Jan 2023 18:45:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230214AbjAaXo7 (ORCPT ); Tue, 31 Jan 2023 18:44:59 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 597714ED07; Tue, 31 Jan 2023 15:44:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675208698; x=1706744698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=by5qRdZTxe0QTHHwMBIcWAw1uHYiJKW6XwzKCf+gNJo=; b=A15JtwrfA3ghpprrnQuDEzlAjBxflazXs/OwFmuqPrLseaL5kvvX9TUC hcVg4qSwL7O22utSKEyxe3jPHm4jTYOfc5opkI6VAve5cq7z/8pOyHnxm 8uExTXO0KAuv5mUoWZNb3/ky8tUH6p0ECJcHpWX632ctFmpQLpxiNbDxg NOAFDZsPhIiTUcKzexkN7HzfkOr9Xiw+n8Ie08fOmQ7RZifj0gq/zXw9a nM+y5UpSdEwVMDMKujD/83y79Do9wwGm6AYZ6PJtd4HRtFbRpz2EkBgLm //FwtzC6jvo98SM/tkIJtbICRO1gPnRm049yM1hXxneWV4oYkokDlQpA6 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="390360446" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="390360446" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:56 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10607"; a="773192036" X-IronPort-AV: E=Sophos;i="5.97,261,1669104000"; d="scan'208";a="773192036" Received: from jithujos.sc.intel.com ([172.25.103.66]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 15:44:55 -0800 From: Jithu Joseph To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH 5/5] platform/x86/intel/ifs: Trace support for array test Date: Tue, 31 Jan 2023 15:43:02 -0800 Message-Id: <20230131234302.3997223-6-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230131234302.3997223-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable tracing support in array test flow. Signed-off-by: Jithu Joseph Reviewed-by: Tony Luck --- include/trace/events/intel_ifs.h | 27 ++++++++++++++++++++++++ drivers/platform/x86/intel/ifs/runtest.c | 1 + 2 files changed, 28 insertions(+) diff --git a/include/trace/events/intel_ifs.h b/include/trace/events/intel_= ifs.h index d7353024016c..db43df4139a2 100644 --- a/include/trace/events/intel_ifs.h +++ b/include/trace/events/intel_ifs.h @@ -35,6 +35,33 @@ TRACE_EVENT(ifs_status, __entry->status) ); =20 +TRACE_EVENT(ifs_array, + + TP_PROTO(int cpu, union ifs_array activate, union ifs_array status), + + TP_ARGS(cpu, activate, status), + + TP_STRUCT__entry( + __field( u64, status ) + __field( int, cpu ) + __field( u32, arrays ) + __field( u16, bank ) + ), + + TP_fast_assign( + __entry->cpu =3D cpu; + __entry->arrays =3D activate.array_bitmask; + __entry->bank =3D activate.array_bank; + __entry->status =3D status.data; + ), + + TP_printk("cpu: %d, array_list: %.8x, array_bank: %.4x, status: %.16llx", + __entry->cpu, + __entry->arrays, + __entry->bank, + __entry->status) +); + #endif /* _TRACE_IFS_H */ =20 /* This part must be outside protection */ diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x8= 6/intel/ifs/runtest.c index ec0ceb6b5890..4fd80d91ea29 100644 --- a/drivers/platform/x86/intel/ifs/runtest.c +++ b/drivers/platform/x86/intel/ifs/runtest.c @@ -301,6 +301,7 @@ static void ifs_array_test_core(int cpu, struct device = *dev) stop_core_cpuslocked(cpu, do_array_test, msrvals); status.data =3D msrvals[1]; =20 + trace_ifs_array(cpu, activate, status); if (status.ctrl_result) break; =20 --=20 2.25.1