From nobody Thu Nov 14 06:56:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48EA2C636CC for ; Mon, 30 Jan 2023 03:33:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235473AbjA3DdU (ORCPT ); Sun, 29 Jan 2023 22:33:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235315AbjA3DdQ (ORCPT ); Sun, 29 Jan 2023 22:33:16 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0CB913D5B; Sun, 29 Jan 2023 19:33:14 -0800 (PST) X-UUID: d0f265b2a04e11eda06fc9ecc4dadd91-20230130 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=S7zFVnLR8eXEvS0Y7l7+sbTIVYZrc5SlkBvc9Y6wViE=; b=YhZxEBoNyySQVS/iNrMJM60UwLc2Jdp8T7jSf3Wk3G/EPjQGQY2BewFBW/YkLe1gkZEkZFrinU9wG6kEV8UxMD4evc95nEWtYMwAJjQ2G6rSfzPmlc0WCxsYlk6UNFmYmDpciTF44EhwE9wU69eY0O87nqghpKjPSNfYUBWnZ1Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:89c74771-33d5-4945-b985-f63fbd14af5a,IP:0,U RL:0,TC:0,Content:-25,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:-55 X-CID-META: VersionHash:3ca2d6b,CLOUDID:2733b355-dd49-462e-a4be-2143a3ddc739,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: d0f265b2a04e11eda06fc9ecc4dadd91-20230130 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1618978660; Mon, 30 Jan 2023 11:33:09 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 30 Jan 2023 11:33:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 30 Jan 2023 11:33:07 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH 1/6] media: dt-bindings: media: mediatek: Rename child node names for decoder Date: Mon, 30 Jan 2023 11:33:00 +0800 Message-ID: <20230130033305.31830-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> References: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to make the names of the child nodes more generic, we rename "vcodec-lat" and "vcodec-core" to "video-codec" for decoder in patternProperties and example. Signed-off-by: Allen-KH Cheng Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- .../media/mediatek,vcodec-subdev-decoder.yaml | 61 ++----------------- 1 file changed, 5 insertions(+), 56 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index c4f20acdc1f8..46308cdaacc0 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -91,12 +91,13 @@ properties: =20 # Required child node: patternProperties: - '^vcodec-lat@[0-9a-f]+$': + '^video-codec@[0-9a-f]+$': type: object =20 properties: compatible: enum: + - mediatek,mtk-vcodec-core - mediatek,mtk-vcodec-lat - mediatek,mtk-vcodec-lat-soc =20 @@ -145,59 +146,6 @@ patternProperties: =20 additionalProperties: false =20 - '^vcodec-core@[0-9a-f]+$': - type: object - - properties: - compatible: - const: mediatek,mtk-vcodec-core - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - iommus: - minItems: 1 - maxItems: 32 - description: | - List of the hardware port in respective IOMMU block for current = Socs. - Refer to bindings/iommu/mediatek,iommu.yaml. - - clocks: - maxItems: 5 - - clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top - - assigned-clocks: - maxItems: 1 - - assigned-clock-parents: - maxItems: 1 - - power-domains: - maxItems: 1 - - required: - - compatible - - reg - - interrupts - - iommus - - clocks - - clock-names - - assigned-clocks - - assigned-clock-parents - - power-domains - - additionalProperties: false - required: - compatible - reg @@ -211,6 +159,7 @@ if: compatible: contains: enum: + - mediatek,mtk-vcodec-core - mediatek,mtk-vcodec-lat =20 then: @@ -241,7 +190,7 @@ examples: #size-cells =3D <2>; ranges =3D <0 0 0 0x16000000 0 0x40000>; reg =3D <0 0x16000000 0 0x1000>; /* VDEC_SYS */ - vcodec-lat@10000 { + video-codec@10000 { compatible =3D "mediatek,mtk-vcodec-lat"; reg =3D <0 0x10000 0 0x800>; interrupts =3D ; @@ -264,7 +213,7 @@ examples: power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; }; =20 - vcodec-core@25000 { + video-codec@25000 { compatible =3D "mediatek,mtk-vcodec-core"; reg =3D <0 0x25000 0 0x1000>; interrupts =3D ; --=20 2.18.0 From nobody Thu Nov 14 06:56:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91D09C54EED for ; Mon, 30 Jan 2023 03:33:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235491AbjA3DdY (ORCPT ); Sun, 29 Jan 2023 22:33:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235398AbjA3DdR (ORCPT ); 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Mon, 30 Jan 2023 11:33:10 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 30 Jan 2023 11:33:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 30 Jan 2023 11:33:08 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH 2/6] media: dt-bindings: media: mediatek: Remove "dma-ranges" property for decoder Date: Mon, 30 Jan 2023 11:33:01 +0800 Message-ID: <20230130033305.31830-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> References: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Because the decoder nodes already make use of the iommus property to configure the IOMMU for address translations, having a dma-ranges property makes no sense. In fact, after commit f1ad5338a4d5 ("of: Fix "dma-ranges" handling for bus controllers"), having a dma-ranges property causes IOMMU faults. Remove the dma-ranges property and update the example. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 7 ------- 1 file changed, 7 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index 46308cdaacc0..7efc70ae4406 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -76,11 +76,6 @@ properties: The node of system control processor (SCP), using the remoteproc & rpmsg framework. =20 - dma-ranges: - maxItems: 1 - description: | - Describes the physical address space of IOMMU maps to memory. - "#address-cells": const: 2 =20 @@ -151,7 +146,6 @@ required: - reg - iommus - mediatek,scp - - dma-ranges - ranges =20 if: @@ -185,7 +179,6 @@ examples: compatible =3D "mediatek,mt8192-vcodec-dec"; mediatek,scp =3D <&scp>; iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; - dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; #address-cells =3D <2>; #size-cells =3D <2>; ranges =3D <0 0 0 0x16000000 0 0x40000>; --=20 2.18.0 From nobody Thu Nov 14 06:56:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 648F1C636CB for ; Mon, 30 Jan 2023 03:33:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235586AbjA3Dd1 (ORCPT ); Sun, 29 Jan 2023 22:33:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229476AbjA3DdS (ORCPT ); Sun, 29 Jan 2023 22:33:18 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E10BAEB40; Sun, 29 Jan 2023 19:33:16 -0800 (PST) X-UUID: d220bb28a04e11eda06fc9ecc4dadd91-20230130 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8s/AqyTRERfWJlTbr4EDA6icF7A3Ta2JpnFPfdFaA74=; b=krg7yR/fxW5b4a9GOZJlZc7vIBi9ck0mk2PWXLEwkdSIvWE+OCQ3Asx9A7iyPQIX9WhN0PghPbgBQx5zUOQtREGhYYlTFo8H45OfEd3ZsJu7d6PHZmFZDYFv4W4XPalj6+U2k1BwhqlsU5JNzOokeZnW1lctlh0r6pf6OWe2dTA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:045eea9f-7b76-4d24-a526-faf4e1f82240,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:3ca2d6b,CLOUDID:53ff4d8d-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: d220bb28a04e11eda06fc9ecc4dadd91-20230130 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1457082859; Mon, 30 Jan 2023 11:33:11 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 30 Jan 2023 11:33:09 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 30 Jan 2023 11:33:09 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH 3/6] arm64: dts: mt8192: Add video-codec nodes Date: Mon, 30 Jan 2023 11:33:02 +0800 Message-ID: <20230130033305.31830-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> References: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add video-codec lat and core nodes for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado Tested-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 59 ++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index ef4fcefa2bfc..9b51cce4c25d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1520,6 +1520,65 @@ power-domains =3D <&spm MT8192_POWER_DOMAIN_ISP2>; }; =20 + vcodec_dec: video-codec@16000000 { + compatible =3D "mediatek,mt8192-vcodec-dec"; + reg =3D <0 0x16000000 0 0x1000>; + mediatek,scp =3D <&scp>; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0x16000000 0 0x26000>; + + video-codec@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0x0 0x10000 0 0x800>; + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + video-codec@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + interrupts =3D ; + iommus =3D <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names =3D "sel", "soc-vdec", "soc-lat", "vdec", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + }; + larb5: larb@1600d000 { compatible =3D "mediatek,mt8192-smi-larb"; reg =3D <0 0x1600d000 0 0x1000>; --=20 2.18.0 From nobody Thu Nov 14 06:56:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE6C5C54EAA for ; Mon, 30 Jan 2023 03:33:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235398AbjA3Dda (ORCPT ); Sun, 29 Jan 2023 22:33:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235438AbjA3DdU (ORCPT ); Sun, 29 Jan 2023 22:33:20 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 044181C336; 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Mon, 30 Jan 2023 11:33:11 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 30 Jan 2023 11:33:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 30 Jan 2023 11:33:10 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , , , Allen-KH Cheng Subject: [PATCH 4/6] media: dt-bindings: media: mediatek: vcodec: adapt to the 'clock-names' of different platforms Date: Mon, 30 Jan 2023 11:33:03 +0800 Message-ID: <20230130033305.31830-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> References: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yunfei Dong mt8195 and mt8192 have different clock numbers, separate 'clock-names' according to compatible name. Signed-off-by: Yunfei Dong Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- .../media/mediatek,vcodec-subdev-decoder.yaml | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index 7efc70ae4406..51c0ff7baa52 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -110,15 +110,12 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. =20 clocks: + minItems: 4 maxItems: 5 =20 clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top + minItems: 4 + maxItems: 5 =20 assigned-clocks: maxItems: 1 @@ -160,6 +157,38 @@ then: required: - interrupts =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-vcodec-dec + then: + properties: + clock-names: + items: + - const: sel + - const: soc-vdec + - const: soc-lat + - const: vdec + - const: top + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-vcodec-dec + then: + properties: + clock-names: + items: + - const: sel + - const: vdec + - const: lat + - const: top + additionalProperties: false =20 examples: --=20 2.18.0 From nobody Thu Nov 14 06:56:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D8BCC54EAA for ; Mon, 30 Jan 2023 03:33:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235637AbjA3Ddd (ORCPT ); Sun, 29 Jan 2023 22:33:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235514AbjA3DdY (ORCPT ); Sun, 29 Jan 2023 22:33:24 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18DBB20D21; Sun, 29 Jan 2023 19:33:19 -0800 (PST) X-UUID: d35d5cf8a04e11ed945fc101203acc17-20230130 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KEWfprtLcsm395hD7ACF+KmAQ+ogRYh8vluT9gQ1Uyc=; b=OdBH5p/DeURuSrhvLbnXMoMm5gdllOZyHcm0ar/fmOgVp/bHKrW40gcwt9Xof5HXtuMINWAKe7NojyZ4TBmMiyT4wseM/6/fjFVRiKgEF5IZKuPVo7xhN934rIVyw8P8Mu63QyMukmoWmbCgOG0DOXixl52KJiMfpKEjtWSzQY0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:d4251ee1-c969-41db-b289-66ee14839d0c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:3ca2d6b,CLOUDID:9eff4d8d-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: d35d5cf8a04e11ed945fc101203acc17-20230130 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 852202809; Mon, 30 Jan 2023 11:33:13 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 30 Jan 2023 11:33:11 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 30 Jan 2023 11:33:11 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , , , "Allen-KH Cheng" Subject: [PATCH 5/6] media: dt-bindings: media: mediatek: vcodec: Change the max reg value to 2 Date: Mon, 30 Jan 2023 11:33:04 +0800 Message-ID: <20230130033305.31830-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> References: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yunfei Dong Need to add racing control register base in device node for mt8195 support inner racing mode. Changing the max reg value from 1 to 2. Adding the description for VDEC_SYS and VDEC_MISC. Signed-off-by: Yunfei Dong Signed-off-by: Allen-KH Cheng Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index 51c0ff7baa52..cfd13a6b6b68 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -61,7 +61,10 @@ properties: - mediatek,mt8195-vcodec-dec =20 reg: - maxItems: 1 + minItems: 1 + items: + - description: VDEC_SYS register space + - description: VDEC_RACING_CTRL register space =20 iommus: minItems: 1 @@ -98,6 +101,7 @@ patternProperties: =20 reg: maxItems: 1 + description: VDEC_MISC register space =20 interrupts: maxItems: 1 --=20 2.18.0 From nobody Thu Nov 14 06:56:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 005F3C54EED for ; Mon, 30 Jan 2023 03:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235667AbjA3Ddh (ORCPT ); Sun, 29 Jan 2023 22:33:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235529AbjA3DdY (ORCPT ); Sun, 29 Jan 2023 22:33:24 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A00FA21949; Sun, 29 Jan 2023 19:33:20 -0800 (PST) X-UUID: d35f8bfea04e11ed945fc101203acc17-20230130 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=by1eY5KmwL6RPgc+Jxj9BAxI9cqcfKeDQSdyxly48P4=; b=DD9xA3As+1yt1yTWoeKn78KXMcAwY+LlTudth6Z9FjmR9IGAxW0OAUcEfm1zBEgIU34VW5dr4dFwEzjiOP0Xe/hFOjNpnNEONG8pS6vURsK+1Ouk2eMF7CrmUuPUaG8GwsdLCvkcSv+T3Ucdzfh03ise4/BQhXLdkdmXUwr9vF0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:3888990b-3b41-43f8-a2f6-a9bb1db7f57e,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:3ca2d6b,CLOUDID:3c01ddf6-ff42-4fb0-b929-626456a83c14,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: d35f8bfea04e11ed945fc101203acc17-20230130 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 322740554; Mon, 30 Jan 2023 11:33:13 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 30 Jan 2023 11:33:12 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 30 Jan 2023 11:33:12 +0800 From: Allen-KH Cheng To: Mauro Carvalho Chehab , Matthias Brugger , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , , , "Allen-KH Cheng" Subject: [PATCH 6/6] arm64: dts: mt8195: Add video decoder node Date: Mon, 30 Jan 2023 11:33:05 +0800 Message-ID: <20230130033305.31830-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> References: <20230130033305.31830-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yunfei Dong Add video decoder node to mt8195 device tree. Signed-off-by: Yunfei Dong Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 9db5f9157ce3..04abd9a08d15 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2196,6 +2196,76 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_CAM>; }; =20 + video-codec@18000000 { + compatible =3D "mediatek,mt8195-vcodec-dec"; + mediatek,scp =3D <&scp>; + iommus =3D <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0 0x18000000 0 0x1000>, + <0 0x18004000 0 0x1000>; + ranges =3D <0 0 0 0x18000000 0 0x26000>; + + video-codec@2000 { + compatible =3D "mediatek,mtk-vcodec-lat-soc"; + reg =3D <0 0x2000 0 0x800>; + iommus =3D <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names =3D "sel", "vdec", "lat", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x10000 0 0x800>; + interrupts =3D ; + iommus =3D <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names =3D "sel", "vdec", "lat", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts =3D ; + iommus =3D <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names =3D "sel", "vdec", "lat", "top"; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible =3D "mediatek,mt8195-smi-larb"; reg =3D <0 0x1800d000 0 0x1000>; --=20 2.18.0