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Sun, 29 Jan 2023 16:57:27 -0800 From: Shanker Donthineni To: Thomas Gleixner , Marc Zyngier , Michael Walle CC: Sebastian Andrzej Siewior , Hans de Goede , Wolfram Sang , Shanker Donthineni , Subject: [PATCH 1/5] genirq: Use hlist for managing resend handlers Date: Sun, 29 Jan 2023 18:57:21 -0600 Message-ID: <20230130005725.3517597-2-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230130005725.3517597-1-sdonthineni@nvidia.com> References: <20230130005725.3517597-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EF:EE_|DS7PR12MB8252:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d464cdb-3107-40a0-498d-08db025cf908 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YdQp8WWMUvSQBFIHGn2H3hisqRQv8qxCftO/0RCj/nqpenhDPvfF9HY0CpAYyI6ecdpBJL2regUXc5Qq0P/VwSe7gaYZVPb4EA7xC1CNBEbC9u8Ih6em/5xGL8G5YtUB/Lz7QAjd+rlD8I/cLvMR2KX6m1Omw5++Op36q1cJJfX6CHiVNGrIfqM81gDTm3OBGzjKdHGCJV658kp3bTil9zK2/gub18mQlaDHcjPMijo0vcT/6u18k+CjnhWMMwKn1SvCZPpyPmpis82DYutNpTQZSfWrjtgizeqrL6UYwTa9E5DOC7cqFOMRoSm2woIORj65Xz6l+d+3lyRQ24YhJSqLyMI647WiIUaNZUeMjFiro9o40D+KDn7r8JguQWAPKvIWBdisK4B1ZIoUn0EdNw6A+zuRdrLmPkPAFhEm/azaDC/fkA6RHeL6ENCgZ90bpKxidalEpgnRtmG/pr6ycUryM4Fd1VbbIwqs7QxNq9rDpFY6dMdQ3v+M18rmop9Ru+gplSr7N7f5i9Tuxy3mnl/1O4fNzc9SV3IvX7YaLe3MzzU4baAsb3wFooNdLL0MlwmCOzKY4VFqxAlsQlEGWhs9c+MOplgNGRlglKTT/fiVK3eGAY2s2znBKWziaa4bfzO4gJAnGU7xW32r8bbGttac7vndAw64ZSpCsQwb5Y9yUKZXqMOMDJRkUGLKKirmEVYvUXp5/0BNqosN5QYJvA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(39860400002)(396003)(136003)(376002)(451199018)(40470700004)(46966006)(36840700001)(66899018)(2906002)(8936002)(5660300002)(41300700001)(86362001)(83380400001)(26005)(70206006)(1076003)(6666004)(110136005)(4326008)(70586007)(40460700003)(8676002)(186003)(478600001)(7696005)(426003)(47076005)(336012)(2616005)(40480700001)(82310400005)(316002)(36756003)(82740400003)(54906003)(7636003)(356005)(36860700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 00:57:34.0280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d464cdb-3107-40a0-498d-08db025cf908 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8252 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current implementation utilizes a bitmap for managing IRQ resend handlers, which is allocated based on the SPARSE_IRQ/NR_IRQS macros. However, this method may not efficiently utilize memory during runtime, particularly when IRQ_BITMAP_BITS is large. This proposed patch aims to address this issue by using hlist to manage IRQ resend handlers instead of relying on static memory allocation. Additionally, a new function, clear_irq_resend(), is introduced and called from irq_shutdown to ensure a graceful teardown of IRQD. Signed-off-by: Shanker Donthineni --- include/linux/irqdesc.h | 3 +++ kernel/irq/chip.c | 1 + kernel/irq/internals.h | 1 + kernel/irq/irqdesc.c | 6 ++++++ kernel/irq/resend.c | 36 +++++++++++++++++++++--------------- 5 files changed, 32 insertions(+), 15 deletions(-) diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index 844a8e30e6de..d9451d456a73 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -102,6 +102,9 @@ struct irq_desc { int parent_irq; struct module *owner; const char *name; +#ifdef CONFIG_HARDIRQS_SW_RESEND + struct hlist_node resend_node; +#endif } ____cacheline_internodealigned_in_smp; =20 #ifdef CONFIG_SPARSE_IRQ diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 49e7bc871fec..2eac5532c3c8 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -306,6 +306,7 @@ static void __irq_disable(struct irq_desc *desc, bool m= ask); void irq_shutdown(struct irq_desc *desc) { if (irqd_is_started(&desc->irq_data)) { + clear_irq_resend(desc); desc->depth =3D 1; if (desc->irq_data.chip->irq_shutdown) { desc->irq_data.chip->irq_shutdown(&desc->irq_data); diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 5fdc0b557579..2fd17057ed4b 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -113,6 +113,7 @@ irqreturn_t handle_irq_event(struct irq_desc *desc); =20 /* Resending of interrupts :*/ int check_irq_resend(struct irq_desc *desc, bool inject); +void clear_irq_resend(struct irq_desc *desc); bool irq_wait_for_poll(struct irq_desc *desc); void __irq_wake_thread(struct irq_desc *desc, struct irqaction *action); =20 diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index fd0996274401..21a968bc468b 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -415,6 +415,9 @@ static struct irq_desc *alloc_desc(int irq, int node, u= nsigned int flags, desc_set_defaults(irq, desc, node, affinity, owner); irqd_set(&desc->irq_data, flags); kobject_init(&desc->kobj, &irq_kobj_type); +#ifdef CONFIG_HARDIRQS_SW_RESEND + INIT_HLIST_NODE(&desc->resend_node); +#endif =20 return desc; =20 @@ -581,6 +584,9 @@ int __init early_irq_init(void) mutex_init(&desc[i].request_mutex); init_waitqueue_head(&desc[i].wait_for_threads); desc_set_defaults(i, &desc[i], node, NULL, NULL); +#ifdef CONFIG_HARDIRQS_SW_RESEND + INIT_HLIST_NODE(&desc->resend_node); +#endif } return arch_early_irq_init(); } diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c index 0c46e9fe3a89..f2b23871cbef 100644 --- a/kernel/irq/resend.c +++ b/kernel/irq/resend.c @@ -21,8 +21,9 @@ =20 #ifdef CONFIG_HARDIRQS_SW_RESEND =20 -/* Bitmap to handle software resend of interrupts: */ -static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS); +/* hlist_head to handle software resend of interrupts: */ +static HLIST_HEAD(irq_resend_list); +static DEFINE_RAW_SPINLOCK(irq_resend_lock); =20 /* * Run software resends of IRQ's @@ -30,18 +31,16 @@ static DECLARE_BITMAP(irqs_resend, IRQ_BITMAP_BITS); static void resend_irqs(struct tasklet_struct *unused) { struct irq_desc *desc; - int irq; - - while (!bitmap_empty(irqs_resend, nr_irqs)) { - irq =3D find_first_bit(irqs_resend, nr_irqs); - clear_bit(irq, irqs_resend); - desc =3D irq_to_desc(irq); - if (!desc) - continue; + struct hlist_node *n; + + raw_spin_lock_irq(&irq_resend_lock); + hlist_for_each_entry_safe(desc, n, &irq_resend_list, resend_node) { + hlist_del_init(&desc->resend_node); local_irq_disable(); desc->handle_irq(desc); local_irq_enable(); } + raw_spin_unlock_irq(&irq_resend_lock); } =20 /* Tasklet to handle resend: */ @@ -49,8 +48,6 @@ static DECLARE_TASKLET(resend_tasklet, resend_irqs); =20 static int irq_sw_resend(struct irq_desc *desc) { - unsigned int irq =3D irq_desc_get_irq(desc); - /* * Validate whether this interrupt can be safely injected from * non interrupt context @@ -70,16 +67,25 @@ static int irq_sw_resend(struct irq_desc *desc) */ if (!desc->parent_irq) return -EINVAL; - irq =3D desc->parent_irq; } =20 - /* Set it pending and activate the softirq: */ - set_bit(irq, irqs_resend); + /* Add to resend_list and activate the softirq: */ + raw_spin_lock(&irq_resend_lock); + hlist_add_head(&desc->resend_node, &irq_resend_list); + raw_spin_unlock(&irq_resend_lock); tasklet_schedule(&resend_tasklet); return 0; } =20 +void clear_irq_resend(struct irq_desc *desc) +{ + raw_spin_lock(&irq_resend_lock); + hlist_del_init(&desc->resend_node); + raw_spin_unlock(&irq_resend_lock); +} #else +void clear_irq_resend(struct irq_desc *desc) {} + static int irq_sw_resend(struct irq_desc *desc) { return -EINVAL; --=20 2.25.1 From nobody Sat Sep 13 22:28:05 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8700C61DA4 for ; Mon, 30 Jan 2023 00:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235134AbjA3A5y (ORCPT ); Sun, 29 Jan 2023 19:57:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230148AbjA3A5o (ORCPT ); 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Sun, 29 Jan 2023 16:57:28 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 29 Jan 2023 16:57:28 -0800 Received: from SDONTHINENI-DESKTOP.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Sun, 29 Jan 2023 16:57:28 -0800 From: Shanker Donthineni To: Thomas Gleixner , Marc Zyngier , Michael Walle CC: Sebastian Andrzej Siewior , Hans de Goede , Wolfram Sang , Shanker Donthineni , Subject: [PATCH 2/5] genirq: Allocate IRQ descriptors at boot time for !SPARSEIRQ Date: Sun, 29 Jan 2023 18:57:22 -0600 Message-ID: <20230130005725.3517597-3-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230130005725.3517597-1-sdonthineni@nvidia.com> References: <20230130005725.3517597-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT079:EE_|MW3PR12MB4426:EE_ X-MS-Office365-Filtering-Correlation-Id: e61e8bca-fa0b-4812-91c1-08db025cfb72 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 00:57:38.0331 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e61e8bca-fa0b-4812-91c1-08db025cfb72 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4426 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove the use of statically allocated arrays for IRQ descriptors. Instead, allocate the necessary NR_IRQ descriptors during the boot time in early_irq_init(). Signed-off-by: Shanker Donthineni --- kernel/irq/irqdesc.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 21a968bc468b..a4911f7ebb07 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -556,27 +556,24 @@ int __init early_irq_init(void) =20 #else /* !CONFIG_SPARSE_IRQ */ =20 -struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp =3D { - [0 ... NR_IRQS-1] =3D { - .handle_irq =3D handle_bad_irq, - .depth =3D 1, - .lock =3D __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock), - } -}; +static struct irq_desc *irq_descs; =20 int __init early_irq_init(void) { - int count, i, node =3D first_online_node; + int i, node =3D first_online_node; struct irq_desc *desc; =20 init_irq_default_affinity(); =20 printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS); =20 - desc =3D irq_desc; - count =3D ARRAY_SIZE(irq_desc); + desc =3D kmalloc_array(NR_IRQS, sizeof(*desc), GFP_KERNEL | __GFP_ZERO); + if (desc =3D=3D NULL) + return -ENOMEM; + + irq_descs =3D desc; =20 - for (i =3D 0; i < count; i++) { + for (i =3D 0; i < NR_IRQS; i++) { desc[i].kstat_irqs =3D alloc_percpu(unsigned int); alloc_masks(&desc[i], node); raw_spin_lock_init(&desc[i].lock); @@ -593,7 +590,7 @@ int __init early_irq_init(void) =20 struct irq_desc *irq_to_desc(unsigned int irq) { - return (irq < NR_IRQS) ? irq_desc + irq : NULL; + return (irq < NR_IRQS) ? irq_descs + irq : NULL; } EXPORT_SYMBOL(irq_to_desc); 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Sun, 29 Jan 2023 16:57:28 -0800 From: Shanker Donthineni To: Thomas Gleixner , Marc Zyngier , Michael Walle CC: Sebastian Andrzej Siewior , Hans de Goede , Wolfram Sang , Shanker Donthineni , Subject: [PATCH 3/5] genirq: Introduce two helper functions Date: Sun, 29 Jan 2023 18:57:23 -0600 Message-ID: <20230130005725.3517597-4-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230130005725.3517597-1-sdonthineni@nvidia.com> References: <20230130005725.3517597-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EF:EE_|BL0PR12MB4995:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c8611bb-fcc8-45aa-c0ce-08db025cfb01 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vkh4scsXdwc2BT2zNRzAkk92boWbCVSLtmF5keWhXC4OdjUbOclouKU1F3iqTsGpI3ZazDh8ymxmbY9EnXB4p7X6Sl0V4txb1tjBqow0bCen7o4TdOqoEbMeW6weu3rl3A8nWzXauBnTLfVNfO9DKim3c3oodYMc32g1yYEwJQPUiWerRT2PNwwiKMb0mmKcPkUIGa29nMo8I1WvyUa5sVHUw+ZAyVn3IxgpkcXFHXKszXXZtK6d8Es1n2GGN/Ie6TtozJmyx2Wm+kkGvau3oq1IhagrLqhLWeVpcEPPeJrB4Auy8FviXFR8sNFOZ6Z8GNdQ8hbdivNU77YL9WgEkb0WRZQQs3JWmBb8zypeRGtUZd6ghv6DCCA3I3c3I2RerKCWlV3DkQnz5HwYfpAzqPcpmor0H0Rq4+CgX08Ts21kNr9iObMdA4sgD0Siwq0rJY9u+N8zV3uGwNMEsfdeURPg9VB1jjDjMckfpqNSdg2bz5BBqPRuYEsGkhH+PfVJAEKvmzTHip9dOckB6XLmhpbds1h1ZGrhPsprwV40SWhASQTbkRQyGBz4W8udQnffYUaVtqhMtiYeC2KJf4gBnbkGSFr3rkvC8EwTdrV8XTAhy6j3482ydUzQIt2iFS6XO7qZaRLRVlOz7nY6Wq1QC8a8jOoMnwdt0q77QjYHoa0= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(39850400004)(376002)(346002)(136003)(451199018)(46966006)(36840700001)(83380400001)(2616005)(86362001)(47076005)(426003)(336012)(7636003)(82740400003)(82310400005)(356005)(36860700001)(2906002)(7696005)(36756003)(1076003)(186003)(26005)(478600001)(40480700001)(6666004)(8676002)(8936002)(4326008)(41300700001)(70586007)(70206006)(54906003)(5660300002)(110136005)(316002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 00:57:37.3249 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c8611bb-fcc8-45aa-c0ce-08db025cfb01 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4995 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce helper functions irq_find_free_area() and irq_find_next_irq(). The first function is used to locate available free space for a new IRQ, and the second one is used to find the next valid IRQ. These helper functions will be later modified to utilize the Maple data structure in a later patch. Additionally, in order to align the moving to the new data structure, the IRQ_BITMAP_BITS is renamed to MAX_SPARSE_IRQS. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 4 ++-- kernel/irq/irqdesc.c | 28 +++++++++++++++++++--------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 2fd17057ed4b..5d741b0e7d5e 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,9 +12,9 @@ #include =20 #ifdef CONFIG_SPARSE_IRQ -# define IRQ_BITMAP_BITS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS (NR_IRQS + 8196) #else -# define IRQ_BITMAP_BITS NR_IRQS +# define MAX_SPARSE_IRQS NR_IRQS #endif =20 #define istate core_internal_state__do_not_mess_with_it diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index a4911f7ebb07..aacfb4826c5e 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -131,7 +131,18 @@ int nr_irqs =3D NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); =20 static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); +static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); + +static int irq_find_free_area(unsigned int from, unsigned int cnt) +{ + return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, + from, cnt, 0); +} + +static unsigned int irq_find_next_irq(unsigned int offset) +{ + return find_next_bit(allocated_irqs, nr_irqs, offset); +} =20 #ifdef CONFIG_SPARSE_IRQ =20 @@ -519,7 +530,7 @@ static int alloc_descs(unsigned int start, unsigned int= cnt, int node, =20 static int irq_expand_nr_irqs(unsigned int nr) { - if (nr > IRQ_BITMAP_BITS) + if (nr > MAX_SPARSE_IRQS) return -ENOMEM; nr_irqs =3D nr; return 0; @@ -537,11 +548,11 @@ int __init early_irq_init(void) printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n", NR_IRQS, nr_irqs, initcnt); =20 - if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) - nr_irqs =3D IRQ_BITMAP_BITS; + if (WARN_ON(nr_irqs > MAX_SPARSE_IRQS)) + nr_irqs =3D MAX_SPARSE_IRQS; =20 - if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) - initcnt =3D IRQ_BITMAP_BITS; + if (WARN_ON(initcnt > MAX_SPARSE_IRQS)) + initcnt =3D MAX_SPARSE_IRQS; =20 if (initcnt > nr_irqs) nr_irqs =3D initcnt; @@ -813,8 +824,7 @@ __irq_alloc_descs(int irq, unsigned int from, unsigned = int cnt, int node, =20 mutex_lock(&sparse_irq_lock); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 00:57:39.0642 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5de7dc50-5068-417b-4c0c-08db025cfc12 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5320 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When the !SPARSEIRQ code path is executed, the function irq_expand_nr_irqs() returns -ENOMEM. However, the SPARSEIRQ version of the function can be safely used in both cases, as nr_irqs =3D MAX_SPARSE_IRQS =3D NR_IRQS. Signed-off-by: Shanker Donthineni --- kernel/irq/irqdesc.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index aacfb4826c5e..247a0718d028 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -144,6 +144,14 @@ static unsigned int irq_find_next_irq(unsigned int off= set) return find_next_bit(allocated_irqs, nr_irqs, offset); } =20 +static int irq_expand_nr_irqs(unsigned int nr) +{ + if (nr > MAX_SPARSE_IRQS) + return -ENOMEM; + nr_irqs =3D nr; + return 0; +} + #ifdef CONFIG_SPARSE_IRQ =20 static void irq_kobj_release(struct kobject *kobj); @@ -528,14 +536,6 @@ static int alloc_descs(unsigned int start, unsigned in= t cnt, int node, return -ENOMEM; } =20 -static int irq_expand_nr_irqs(unsigned int nr) -{ - if (nr > MAX_SPARSE_IRQS) - return -ENOMEM; - nr_irqs =3D nr; - return 0; -} - int __init early_irq_init(void) { int i, initcnt, node =3D first_online_node; @@ -630,11 +630,6 @@ static inline int alloc_descs(unsigned int start, unsi= gned int cnt, int node, return start; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2023 00:57:41.8921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85e95a8d-3bdd-4ca5-ccf8-08db025cfdc1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4254 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current implementation uses a static bitmap and a radix tree to manage IRQ allocation and irq_desc pointer store respectively. However, the size of the bitmap is constrained by the build time macro MAX_SPARSE_IRQS, which may not be sufficient to support the high-end servers, particularly those with GICv4.1 hardware, which require a large interrupt space to cover LPIs and vSGIs The maple tree is a highly efficient data structure for storing non-overlapping ranges and can handle a large number of entries, up to ULONG_MAX. It can be utilized for both storing IRQD and identifying available free spaces. The IRQD management can be simplified by switching to a maple tree data structure, which offers greater flexibility and scalability. To support modern servers, the maximum number of IRQs has been increased to INT_MAX, which provides a more adequate value than the previous limit of NR_IRQS+8192. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 2 +- kernel/irq/irqdesc.c | 51 ++++++++++++++++++++++++------------------ 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 5d741b0e7d5e..e35de737802c 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,7 +12,7 @@ #include =20 #ifdef CONFIG_SPARSE_IRQ -# define MAX_SPARSE_IRQS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS INT_MAX #else # define MAX_SPARSE_IRQS NR_IRQS #endif diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 247a0718d028..06be5f924a7c 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #include "internals.h" @@ -131,17 +132,37 @@ int nr_irqs =3D NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); =20 static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); +static struct maple_tree sparse_irqs =3D MTREE_INIT_EXT(sparse_irqs, + MT_FLAGS_ALLOC_RANGE | + MT_FLAGS_LOCK_EXTERN | + MT_FLAGS_USE_RCU, sparse_irq_lock); =20 static int irq_find_free_area(unsigned int from, unsigned int cnt) { - return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, - from, cnt, 0); + MA_STATE(mas, &sparse_irqs, 0, 0); + + if (mas_empty_area(&mas, from, MAX_SPARSE_IRQS, cnt)) + return -ENOSPC; + return mas.index; } =20 static unsigned int irq_find_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + struct irq_desc *desc =3D mt_next(&sparse_irqs, offset, nr_irqs); + + return desc ? irq_desc_get_irq(desc) : nr_irqs; +} + +static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + WARN_ON(mas_store_gfp(&mas, desc, GFP_KERNEL) !=3D 0); +} + +static void delete_irq_desc(unsigned int irq) +{ + MA_STATE(mas, &sparse_irqs, irq, irq); + mas_erase(&mas); } =20 static int irq_expand_nr_irqs(unsigned int nr) @@ -363,26 +384,14 @@ static void irq_sysfs_del(struct irq_desc *desc) {} =20 #endif /* CONFIG_SYSFS */ =20 -static RADIX_TREE(irq_desc_tree, GFP_KERNEL); - -static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) -{ - radix_tree_insert(&irq_desc_tree, irq, desc); -} - struct irq_desc *irq_to_desc(unsigned int irq) { - return radix_tree_lookup(&irq_desc_tree, irq); + return mtree_load(&sparse_irqs, irq); } #ifdef CONFIG_KVM_BOOK3S_64_HV_MODULE EXPORT_SYMBOL_GPL(irq_to_desc); #endif =20 -static void delete_irq_desc(unsigned int irq) -{ - radix_tree_delete(&irq_desc_tree, irq); -} - #ifdef CONFIG_SMP static void free_masks(struct irq_desc *desc) { @@ -527,7 +536,6 @@ static int alloc_descs(unsigned int start, unsigned int= cnt, int node, irq_sysfs_add(start + i, desc); irq_add_debugfs_entry(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; =20 err: @@ -559,7 +567,6 @@ int __init early_irq_init(void) =20 for (i =3D 0; i < initcnt; i++) { desc =3D alloc_desc(i, node, 0, NULL, NULL); - set_bit(i, allocated_irqs); irq_insert_desc(i, desc); } return arch_early_irq_init(); @@ -613,6 +620,7 @@ static void free_desc(unsigned int irq) raw_spin_lock_irqsave(&desc->lock, flags); desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL); raw_spin_unlock_irqrestore(&desc->lock, flags); + delete_irq_desc(irq); } =20 static inline int alloc_descs(unsigned int start, unsigned int cnt, int no= de, @@ -625,15 +633,15 @@ static inline int alloc_descs(unsigned int start, uns= igned int cnt, int node, struct irq_desc *desc =3D irq_to_desc(start + i); =20 desc->owner =3D owner; + irq_insert_desc(start + i, desc); } - bitmap_set(allocated_irqs, start, cnt); return start; } =20 void irq_mark_irq(unsigned int irq) { mutex_lock(&sparse_irq_lock); - bitmap_set(allocated_irqs, irq, 1); + irq_insert_desc(irq, irq_descs + irq); mutex_unlock(&sparse_irq_lock); } =20 @@ -777,7 +785,6 @@ void irq_free_descs(unsigned int from, unsigned int cnt) for (i =3D 0; i < cnt; i++) free_desc(from + i); =20 - bitmap_clear(allocated_irqs, from, cnt); mutex_unlock(&sparse_irq_lock); } EXPORT_SYMBOL_GPL(irq_free_descs); --=20 2.25.1