From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C11E8C38142 for ; Fri, 27 Jan 2023 18:26:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235275AbjA0S0W (ORCPT ); Fri, 27 Jan 2023 13:26:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235072AbjA0S0Q (ORCPT ); Fri, 27 Jan 2023 13:26:16 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C39D7B40A for ; Fri, 27 Jan 2023 10:26:15 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id x5so2411924plr.2 for ; Fri, 27 Jan 2023 10:26:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iGqgvezQ/AlpTuqgVROWAp2lac08ioX9ghbgFT6R5zs=; b=IoRffA7eaBKD5TnGEAMzpERUl+R39LOxAlgfDLhDNga+rN9SbFYLfdz9WFRgJCTeRN 9Updpbd1OZtc//enWU826k0AachdF3yKioeNtgxkt9/kIfGqMeggP3NJkMHCVrn38zEt o0ySxQgMwR7DstBzrONN9sUSnnkIYSCZmjlPUaPZycJTqTBIKNAj0Y+IKQKTWXZUV/g1 Hbr1Yw2D00RYz6wcO9p7KP1dPScebiMdJ1Wz7lqeW/m8MLImzr1r9OBpSxBUtGPDMeaU EKmOy6JcaGBPxAZXqtqvKGClyDQ4IZH3V1Pgrky1d4NUmTsNJDKgHZ/O9226Ve6thdSn TZ6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iGqgvezQ/AlpTuqgVROWAp2lac08ioX9ghbgFT6R5zs=; b=kEFC6RLZliSHLbMvOOEVc1ApJwYA8Lw0Bjpu72GCChhqXAoYWiBSahHyjDB9MWxu6x 6kkmdYL0rDw1mpXziY/j44JxKzFlJdB2Ber9y2tRn2C6G/Z0ii37xkg5JgeNd65DDFwn UXkvtsYrD2HVKFY58meaNDXxB5CnsQpgQpDI1fLCKz+p4iRF+J8UfylEvUiwewzBZ/KV wvNVZv4vjoh59Dz1tKxZyp/hV6Npbhbzc9Arb4YNpxp6VOcOS5b07ozWnsIwCJNLihhP XPJU9MWllWW4v3cMjyditYEjx5zazsD+PrWCly50hknj2I9WTHytS+PHVaUyzTPJdmPi p7tA== X-Gm-Message-State: AO0yUKW7Hwq0baU/7aRLyIgFWOr2bW1FfaW6NiTvPZTwIBdLdULBg4+O gcgiZLFwisk+Qvf6Q1yU3r0VL0lBq+Kw/OWl X-Google-Smtp-Source: AK7set+cnIlp7JbMlNK7BW+W2Y23IVQIWZv8DFzQh9nYmsI7NrsZq7emEqdZjMsHA/iQQGK1DvKKNA== X-Received: by 2002:a17:902:f54c:b0:196:f82:14c9 with SMTP id h12-20020a170902f54c00b001960f8214c9mr17447443plf.57.1674843974605; Fri, 27 Jan 2023 10:26:14 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:14 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Date: Fri, 27 Jan 2023 10:25:45 -0800 Message-Id: <20230127182558.2416400-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" KVM module needs to know how many hardware counters and the counter width that the platform supports. Otherwise, it will not be able to show optimal value of virtual counters to the guest. The virtual hardware counters also need to have the same width as the logical hardware counters for simplicity. However, there shouldn't be mapping between virtual hardware counters and logical hardware counters. As we don't support hetergeneous harts or counters with different width as of now, the implementation relies on the counter width of the first available programmable counter. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- drivers/perf/riscv_pmu_sbi.c | 37 ++++++++++++++++++++++++++++++++-- include/linux/perf/riscv_pmu.h | 3 +++ 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index f6507ef..6b53adc 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -44,7 +44,7 @@ static const struct attribute_group *riscv_pmu_attr_group= s[] =3D { }; =20 /* - * RISC-V doesn't have hetergenous harts yet. This need to be part of + * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ static union sbi_pmu_ctr_info *pmu_ctr_list; @@ -52,6 +52,9 @@ static bool riscv_pmu_use_irq; static unsigned int riscv_pmu_irq_num; static unsigned int riscv_pmu_irq; =20 +/* Cache the available counters in a bitmask */ +static unsigned long cmask; + struct sbi_pmu_event_data { union { union { @@ -267,6 +270,37 @@ static bool pmu_sbi_ctr_is_fw(int cidx) return (info->type =3D=3D SBI_PMU_CTR_TYPE_FW) ? true : false; } =20 +/* + * Returns the counter width of a programmable counter and number of hardw= are + * counters. As we don't support heterogeneous CPUs yet, it is okay to just + * return the counter width of the first programmable counter. + */ +int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr) +{ + int i; + union sbi_pmu_ctr_info *info; + u32 hpm_width =3D 0, hpm_count =3D 0; + + if (!cmask) + return -EINVAL; + + for_each_set_bit(i, &cmask, RISCV_MAX_COUNTERS) { + info =3D &pmu_ctr_list[i]; + if (!info) + continue; + if (!hpm_width && info->csr !=3D CSR_CYCLE && info->csr !=3D CSR_INSTRET) + hpm_width =3D info->width; + if (info->type =3D=3D SBI_PMU_CTR_TYPE_HW) + hpm_count++; + } + + *hw_ctr_width =3D hpm_width; + *num_hw_ctr =3D hpm_count; + + return 0; +} +EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); + static int pmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; @@ -812,7 +846,6 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) static int pmu_sbi_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu =3D NULL; - unsigned long cmask =3D 0; int ret =3D -ENODEV; int num_counters; =20 diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index e17e86a..a1c3f77 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -73,6 +73,9 @@ void riscv_pmu_legacy_skip_init(void); static inline void riscv_pmu_legacy_skip_init(void) {}; #endif struct riscv_pmu *riscv_pmu_alloc(void); +#ifdef CONFIG_RISCV_PMU_SBI +int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); +#endif =20 #endif /* CONFIG_RISCV_PMU */ =20 --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BABEC38142 for ; Fri, 27 Jan 2023 18:26:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235301AbjA0S0Z (ORCPT ); Fri, 27 Jan 2023 13:26:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235096AbjA0S0R (ORCPT ); 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Fri, 27 Jan 2023 10:26:15 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 02/14] perf: RISC-V: Improve privilege mode filtering for perf Date: Fri, 27 Jan 2023 10:25:46 -0800 Message-Id: <20230127182558.2416400-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the host driver doesn't have any method to identify if the requested perf event is from kvm or bare metal. As KVM runs in HS mode, there are no separate hypervisor privilege mode to distinguish between the attributes for guest/host. Improve the privilege mode filtering by using the event specific config1 field. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- drivers/perf/riscv_pmu_sbi.c | 27 ++++++++++++++++++++++----- include/linux/perf/riscv_pmu.h | 2 ++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 6b53adc..e862b13 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -301,6 +301,27 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num= _hw_ctr) } EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); =20 +static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) +{ + unsigned long cflags =3D 0; + bool guest_events =3D false; + + if (event->attr.config1 & RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS) + guest_events =3D true; + if (event->attr.exclude_kernel) + cflags |=3D guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG= _SET_SINH; + if (event->attr.exclude_user) + cflags |=3D guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG= _SET_UINH; + if (guest_events && event->attr.exclude_hv) + cflags |=3D SBI_PMU_CFG_FLAG_SET_SINH; + if (event->attr.exclude_host) + cflags |=3D SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH; + if (event->attr.exclude_guest) + cflags |=3D SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH; + + return cflags; +} + static int pmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; @@ -311,11 +332,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *even= t) uint64_t cbase =3D 0; unsigned long cflags =3D 0; =20 - if (event->attr.exclude_kernel) - cflags |=3D SBI_PMU_CFG_FLAG_SET_SINH; - if (event->attr.exclude_user) - cflags |=3D SBI_PMU_CFG_FLAG_SET_UINH; - + cflags =3D pmu_sbi_get_filter_flags(event); /* retrieve the available counter index */ #if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index a1c3f77..1c42146 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -26,6 +26,8 @@ =20 #define RISCV_PMU_STOP_FLAG_RESET 1 =20 +#define RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS 0x1 + struct cpu_hw_events { /* currently enabled events */ int n_events; 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Fri, 27 Jan 2023 10:26:16 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:16 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions Date: Fri, 27 Jan 2023 10:25:47 -0800 Message-Id: <20230127182558.2416400-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch fixes/improve few minor things in SBI PMU extension definition. 1. Align all the firmware event names. 2. Add macros for bit positions in cache event ID & ops. The changes were small enough to combine them together instead of creating 1 liner patches. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4ca7fba..f21c026 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t { SBI_PMU_FW_IPI_SENT =3D 6, SBI_PMU_FW_IPI_RECVD =3D 7, SBI_PMU_FW_FENCE_I_SENT =3D 8, - SBI_PMU_FW_FENCE_I_RECVD =3D 9, + SBI_PMU_FW_FENCE_I_RCVD =3D 9, SBI_PMU_FW_SFENCE_VMA_SENT =3D 10, SBI_PMU_FW_SFENCE_VMA_RCVD =3D 11, SBI_PMU_FW_SFENCE_VMA_ASID_SENT =3D 12, @@ -215,6 +215,9 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06 #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01 =20 +#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3 +#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1 + #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF =20 /* Flags defined for config matching function */ --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B93EC61D97 for ; Fri, 27 Jan 2023 18:26:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235284AbjA0S0c (ORCPT ); Fri, 27 Jan 2023 13:26:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234055AbjA0S0T (ORCPT ); Fri, 27 Jan 2023 13:26:19 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E791B7B405 for ; Fri, 27 Jan 2023 10:26:17 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id 5so5885398plo.3 for ; Fri, 27 Jan 2023 10:26:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=izgQjGebJOE3RdsQHdegT8RbHZUq8xzpqR3/LUH4GSg=; b=a9q6O59eBw3CpprTPbzQxW83Q7UrY2+lKmZmXjuTmVoRmWq832uyL21I+/u/2jlFsO bTlm0YBWf2ah/OxNoOPiZxfWIeGbfnN6qqpFy+vDApROfAjY7xLdi+oHeD5YAzXrntLp 0iA7A84/LEUf3mVNSHCXRjpqYhD5EyLDz8/2zyHnDr7cKiUp7p2pzS596BsBKHsnBxAk G89h93eoTjPyxN8e6Txu2tZ0uIjZaYWgpUApxOIgGu3sq4yuNH7SSPIAbXdbH2l+GwV5 PzoXrmBsDm+Di6HYC9puIB+BtcJFyZ4EposGAB4Xp8Pyn5GQ/BX/pp2f8FI38oYMDVU5 OtMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=izgQjGebJOE3RdsQHdegT8RbHZUq8xzpqR3/LUH4GSg=; b=seizOioNcZDlVGj5079cHPB7c4bFmKtLKtO0W+kj/GmgHRqkL+CUzxonGpaZF78hLy YzvguDD74yR1hnyBqQiHz2x24w1bzeab4BM9GwUnBo75wKwOLAeVb7+gH0sU9LfWSaBL guYsSIW56xx7xV+haxTGt7DfIv5puozzbzBb+TJUcxhQ6i1f02YGoWDTPnmVApcpcBTN KIPoZ1zkae3xaqArEkub/PlcWc1rqGxke9xIrQq0GNXFJ1c/Xb0Hr0JVkABXMjggKoq3 2zt3D/5HLq4H9efFdnanCERf3XsLapCR68lu1SXyV9CZqktZ8f2zKquY97PM/I9RTYT5 mXnA== X-Gm-Message-State: AFqh2kqX7+QocRr+kEEb/Sjqn3n2nIljJfNQObGdngK3Bj2lRnNdBbaf xqeFi/4DGjJeyz+Nh8zguVukAYO6O/HQyvkY X-Google-Smtp-Source: AMrXdXvB7tRUnB3Hfypgm0M3o3xtG8B8LuON2IbfpnFe7fWjhVF0jWMVK4kOMJuFNqdvYFt/7ZMBfA== X-Received: by 2002:a17:902:6a89:b0:194:88a3:6e28 with SMTP id n9-20020a1709026a8900b0019488a36e28mr38634507plk.51.1674843977309; Fri, 27 Jan 2023 10:26:17 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:17 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Date: Fri, 27 Jan 2023 10:25:48 -0800 Message-Id: <20230127182558.2416400-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently the probe function just checks if an SBI extension is registered or not. However, the extension may not want to advertise itself depending on some other condition. An additional extension specific probe function will allow extensions to decide if they want to be advertised to the caller or not. Any extension that does not require additional dependency checks can avoid implementing this function. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 3 +++ arch/riscv/kvm/vcpu_sbi_base.c | 13 +++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index f79478a..45ba341 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -29,6 +29,9 @@ struct kvm_vcpu_sbi_extension { int (*handler)(struct kvm_vcpu *vcpu, struct kvm_run *run, unsigned long *out_val, struct kvm_cpu_trap *utrap, bool *exit); + + /* Extension specific probe function */ + unsigned long (*probe)(struct kvm_vcpu *vcpu); }; =20 void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run= ); diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c index 5d65c63..846d518 100644 --- a/arch/riscv/kvm/vcpu_sbi_base.c +++ b/arch/riscv/kvm/vcpu_sbi_base.c @@ -19,6 +19,7 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, { int ret =3D 0; struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + const struct kvm_vcpu_sbi_extension *sbi_ext; =20 switch (cp->a6) { case SBI_EXT_BASE_GET_SPEC_VERSION: @@ -43,8 +44,16 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcp= u, struct kvm_run *run, */ kvm_riscv_vcpu_sbi_forward(vcpu, run); *exit =3D true; - } else - *out_val =3D kvm_vcpu_sbi_find_ext(cp->a0) ? 1 : 0; + } else { + sbi_ext =3D kvm_vcpu_sbi_find_ext(cp->a0); + if (sbi_ext) { + if (sbi_ext->probe) + *out_val =3D sbi_ext->probe(vcpu); + else + *out_val =3D 1; + } else + *out_val =3D 0; + } break; case SBI_EXT_BASE_GET_MVENDORID: *out_val =3D vcpu->arch.mvendorid; --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0D54C54EAA for ; Fri, 27 Jan 2023 18:26:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235348AbjA0S0f (ORCPT ); Fri, 27 Jan 2023 13:26:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235261AbjA0S0T (ORCPT ); Fri, 27 Jan 2023 13:26:19 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26B547E075 for ; Fri, 27 Jan 2023 10:26:18 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id o13so5376403pjg.2 for ; Fri, 27 Jan 2023 10:26:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=75NYeBzTa+D//nXwSO0c9cu0uNpb/RJgMmwNWXsNQ7A=; b=YY7c/gb7KD4BgGwCl4QuD8RpNT7TTipby8rQS1fM8ewCQdAAVE7CoiEkS36lf3TY1+ j3OpeGdZzI/FiuYvcGelaEpd818JPNjfPw5HRXDaKrEsFrqQR+6h3u2BoRBgd9QlAccY HDaOvbsPh9oJjc7aXIhCOrLyevo+m6Ry6cj+mJZ8grdtEokiLxkJS3Wgb67hSnJ3ny3B fdGvutiKC31lsRsHB07vjTgOC5Mh7oUjuEQX5QwOVbq5DU0s+Ur+Y7Z/GcKfyw3I0xA7 lPMsCdqnd8ySESkWIsbXcv5QzXJOfH01v3I0e1Tj1NG1M9eSLmeKg5cOtxQhNaIVEsDH tagA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=75NYeBzTa+D//nXwSO0c9cu0uNpb/RJgMmwNWXsNQ7A=; b=ssonuVYikUJI15+aAeieYSlCZt8y0F3o4fYlCBcQYN4M1bA8q9HahxzpkAbfp/qoMf 9UR3CDyj9xtGyHrA46tf5ZTgHeWOVax+NW3fvPjY2eVI5pbIuIL7ZCpMl4fn3ZeUY0VO Guvgg8LHlJYjk0lBnlmBAtvPXWZ/yHkKmxCN3dO3FpEBEafdMlKyAffnlAZfCpWcSUIv zCgWpOHC2Vf45Bk8twfITgyVGpriW4JC+f/nXwujO01i7EjvK/2To9lUbNvM0usAvD0K 3faSP55EuLPptjPTSs3YJa7ehE+EuXY8XD+wZs7VdUpw/0F30XKMYupM6+xovG8gqc8O 1+TQ== X-Gm-Message-State: AFqh2kpQRgmV4tR5toDZ3/Wk81ttxuRveh6+WlUeXGTnjukmAK8xJmse 4+ZZvGiI0rSB+d9nMjcbhJ6v0k2Oq/i74Lpk X-Google-Smtp-Source: AMrXdXtpndneDdeSSBdxCsMnxxzoCdgvpXuk7zeWfLXM+d7saHZXmYD4+9nx/fhrb0dq0pShXiEOXQ== X-Received: by 2002:a17:902:7c93:b0:194:98f0:108e with SMTP id y19-20020a1709027c9300b0019498f0108emr34153952pll.13.1674843978225; Fri, 27 Jan 2023 10:26:18 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:17 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 05/14] RISC-V: KVM: Return correct code for hsm stop function Date: Fri, 27 Jan 2023 10:25:49 -0800 Message-Id: <20230127182558.2416400-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to the SBI specification, the stop function can only return error code SBI_ERR_FAILED. However, currently it returns -EINVAL which will be mapped SBI_ERR_INVALID_PARAM. Return an linux error code that maps to SBI_ERR_FAILED i.e doesn't map to any other SBI error code. While EACCES is not the best error code to describe the situation, it is close enough and will be replaced with SBI error codes directly anyways. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kvm/vcpu_sbi_hsm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c index 2e915ca..619ac0f 100644 --- a/arch/riscv/kvm/vcpu_sbi_hsm.c +++ b/arch/riscv/kvm/vcpu_sbi_hsm.c @@ -42,7 +42,7 @@ static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu) static int kvm_sbi_hsm_vcpu_stop(struct kvm_vcpu *vcpu) { if (vcpu->arch.power_off) - return -EINVAL; + return -EACCES; =20 kvm_riscv_vcpu_power_off(vcpu); =20 --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59E0AC38142 for ; Fri, 27 Jan 2023 18:26:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234971AbjA0S0j (ORCPT ); Fri, 27 Jan 2023 13:26:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235072AbjA0S0W (ORCPT ); Fri, 27 Jan 2023 13:26:22 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47595841B1 for ; Fri, 27 Jan 2023 10:26:20 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id d9so5849243pll.9 for ; Fri, 27 Jan 2023 10:26:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dXwA+He5Gl75oa0P0/Izb/PHhFUIRPdbLW1x5GmAqWI=; b=b1KgQDhzP3LBMu0UWWE4gvo2MupDUaDq7RN2Q1+oBsyYEk5RIMm8udeSuJy/Vzj8Q6 tZ3Oh2W3Y+iOHXD6rRMREkMG3UUnzd3BhamUanWUdTnzvFWM35Y1JFZ4GpLGQKU17DCE 14YA+N927/6cyYscb/r9wMchv/BRNWcGAsjtIfE7h0JnB254PdPotP/2NFgIRJkfTTbP uQLli0QHjFe+Z8WAhY/x/RXB13KQRkYCYer4S6jYXoV5lwa7SPR5SaDtrOG0RlwL96cE 3qoLEECh8r/yax1PSm9aclMgysV7A7DUSnIoOAzUHML08r8U/BDcVdJx4AEfSQbJrw7p buRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dXwA+He5Gl75oa0P0/Izb/PHhFUIRPdbLW1x5GmAqWI=; b=xJl337ks7TR+VsQIMq4hgsDWKpNhIFIIWtc2443OkVRICILdeCxqpbXs9C8jzsgqG8 9Qto1a+Veahgy8aNz+IgFvqcjcfTbo5WHq4lQ8Ot6yUaS9xE91ojrCc3RDN4Cko3j9oL iLZd1CRjBF7QljFSLdKxae2w8I+y1P4aRXH890dcM3xBd/A3+WTbq+UYBCQ1fpeGSYyJ CcHFDqC4i6wf37oekPaYt4hFX2DnmAb80s3RrDc2FmMr0q9xc02z1peWQyZ7px8b+mRM a4gPBA74vYXeXv7XO0A2LwPJ4on9UHLaQoriAZUDg8Q0vBWP5nkS4WpA1cTq++kv/C6z NtrA== X-Gm-Message-State: AO0yUKW0Zf7MHp7t8UOaVgyNgEJk5tYGAFhOeMaQLFZc0v32A2RXQjrS 8cjoKasnvzYm26AamrTWiz42z6coQ4gpCmNq X-Google-Smtp-Source: AK7set/d8UQnl3xzAz8dwQLfXoVWd9ZiHFXIDlsZ1LSYXK3+r5JgV9haxNf31lLbOh0Ae01YKHG44A== X-Received: by 2002:a17:903:244f:b0:192:7845:e0cc with SMTP id l15-20020a170903244f00b001927845e0ccmr7260781pls.68.1674843979140; Fri, 27 Jan 2023 10:26:19 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:18 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Date: Fri, 27 Jan 2023 10:25:50 -0800 Message-Id: <20230127182558.2416400-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the SBI extension handle is expected to return Linux error code. The top SBI layer converts the Linux error code to SBI specific error code that can be returned to guest invoking the SBI calls. This model works as long as SBI error codes have 1-to-1 mappings between them. However, that may not be true always. This patch attempts to disassociate both these error codes by allowing the SBI extension implementation to return SBI specific error codes as well. The extension will continue to return the Linux error specific code which will indicate any problem *with* the extension emulation while the SBI specific error will indicate the problem *of* the emulation. Suggested-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 10 ++++-- arch/riscv/kvm/vcpu_sbi.c | 46 ++++++++------------------ arch/riscv/kvm/vcpu_sbi_base.c | 38 ++++++++++------------ arch/riscv/kvm/vcpu_sbi_hsm.c | 29 +++++++++-------- arch/riscv/kvm/vcpu_sbi_replace.c | 47 ++++++++++++++------------- arch/riscv/kvm/vcpu_sbi_v01.c | 11 +++---- 6 files changed, 84 insertions(+), 97 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 45ba341..38407b3 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -18,6 +18,12 @@ struct kvm_vcpu_sbi_context { int return_handled; }; =20 +struct kvm_vcpu_sbi_ext_data { + unsigned long out_val; + unsigned long err_val; + bool uexit; +}; + struct kvm_vcpu_sbi_extension { unsigned long extid_start; unsigned long extid_end; @@ -27,8 +33,8 @@ struct kvm_vcpu_sbi_extension { * specific error codes. */ int (*handler)(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long *out_val, struct kvm_cpu_trap *utrap, - bool *exit); + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap); =20 /* Extension specific probe function */ unsigned long (*probe)(struct kvm_vcpu *vcpu); diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index f96991d..aa42da6 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -12,26 +12,6 @@ #include #include =20 -static int kvm_linux_err_map_sbi(int err) -{ - switch (err) { - case 0: - return SBI_SUCCESS; - case -EPERM: - return SBI_ERR_DENIED; - case -EINVAL: - return SBI_ERR_INVALID_PARAM; - case -EFAULT: - return SBI_ERR_INVALID_ADDRESS; - case -EOPNOTSUPP: - return SBI_ERR_NOT_SUPPORTED; - case -EALREADY: - return SBI_ERR_ALREADY_AVAILABLE; - default: - return SBI_ERR_FAILURE; - }; -} - #ifndef CONFIG_RISCV_SBI_V01 static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01 =3D { .extid_start =3D -1UL, @@ -125,11 +105,10 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, s= truct kvm_run *run) { int ret =3D 1; bool next_sepc =3D true; - bool userspace_exit =3D false; struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; const struct kvm_vcpu_sbi_extension *sbi_ext; struct kvm_cpu_trap utrap =3D { 0 }; - unsigned long out_val =3D 0; + struct kvm_vcpu_sbi_ext_data edata_out =3D { 0 }; bool ext_is_v01 =3D false; =20 sbi_ext =3D kvm_vcpu_sbi_find_ext(cp->a7); @@ -139,13 +118,22 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, s= truct kvm_run *run) cp->a7 <=3D SBI_EXT_0_1_SHUTDOWN) ext_is_v01 =3D true; #endif - ret =3D sbi_ext->handler(vcpu, run, &out_val, &utrap, &userspace_exit); + ret =3D sbi_ext->handler(vcpu, run, &edata_out, &utrap); } else { /* Return error for unsupported SBI calls */ cp->a0 =3D SBI_ERR_NOT_SUPPORTED; goto ecall_done; } =20 + /* + * When the SBI extension returns a Linux error code, it exits the ioctl + * loop and forwards the error to userspace. + */ + if (ret < 0) { + next_sepc =3D false; + goto ecall_done; + } + /* Handle special error cases i.e trap, exit or userspace forward */ if (utrap.scause) { /* No need to increment sepc or exit ioctl loop */ @@ -157,24 +145,18 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, s= truct kvm_run *run) } =20 /* Exit ioctl loop or Propagate the error code the guest */ - if (userspace_exit) { + if (edata_out.uexit) { next_sepc =3D false; ret =3D 0; } else { - /** - * SBI extension handler always returns an Linux error code. Convert - * it to the SBI specific error code that can be propagated the SBI - * caller. - */ - ret =3D kvm_linux_err_map_sbi(ret); - cp->a0 =3D ret; + cp->a0 =3D edata_out.err_val; ret =3D 1; } ecall_done: if (next_sepc) cp->sepc +=3D 4; if (!ext_is_v01) - cp->a1 =3D out_val; + cp->a1 =3D edata_out.out_val; =20 return ret; } diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c index 846d518..84885e5 100644 --- a/arch/riscv/kvm/vcpu_sbi_base.c +++ b/arch/riscv/kvm/vcpu_sbi_base.c @@ -14,24 +14,23 @@ #include =20 static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, - unsigned long *out_val, - struct kvm_cpu_trap *trap, bool *exit) + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *trap) { - int ret =3D 0; struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; const struct kvm_vcpu_sbi_extension *sbi_ext; =20 switch (cp->a6) { case SBI_EXT_BASE_GET_SPEC_VERSION: - *out_val =3D (KVM_SBI_VERSION_MAJOR << + edata->out_val =3D (KVM_SBI_VERSION_MAJOR << SBI_SPEC_VERSION_MAJOR_SHIFT) | KVM_SBI_VERSION_MINOR; break; case SBI_EXT_BASE_GET_IMP_ID: - *out_val =3D KVM_SBI_IMPID; + edata->out_val =3D KVM_SBI_IMPID; break; case SBI_EXT_BASE_GET_IMP_VERSION: - *out_val =3D LINUX_VERSION_CODE; + edata->out_val =3D LINUX_VERSION_CODE; break; case SBI_EXT_BASE_PROBE_EXT: if ((cp->a0 >=3D SBI_EXT_EXPERIMENTAL_START && @@ -43,33 +42,33 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vc= pu, struct kvm_run *run, * forward it to the userspace */ kvm_riscv_vcpu_sbi_forward(vcpu, run); - *exit =3D true; + edata->uexit =3D true; } else { sbi_ext =3D kvm_vcpu_sbi_find_ext(cp->a0); if (sbi_ext) { if (sbi_ext->probe) - *out_val =3D sbi_ext->probe(vcpu); + edata->out_val =3D sbi_ext->probe(vcpu); else - *out_val =3D 1; + edata->out_val =3D 1; } else - *out_val =3D 0; + edata->out_val =3D 0; } break; case SBI_EXT_BASE_GET_MVENDORID: - *out_val =3D vcpu->arch.mvendorid; + edata->out_val =3D vcpu->arch.mvendorid; break; case SBI_EXT_BASE_GET_MARCHID: - *out_val =3D vcpu->arch.marchid; + edata->out_val =3D vcpu->arch.marchid; break; case SBI_EXT_BASE_GET_MIMPID: - *out_val =3D vcpu->arch.mimpid; + edata->out_val =3D vcpu->arch.mimpid; break; default: - ret =3D -EOPNOTSUPP; + edata->err_val =3D SBI_ERR_NOT_SUPPORTED; break; } =20 - return ret; + return 0; } =20 const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base =3D { @@ -79,17 +78,16 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base = =3D { }; =20 static int kvm_sbi_ext_forward_handler(struct kvm_vcpu *vcpu, - struct kvm_run *run, - unsigned long *out_val, - struct kvm_cpu_trap *utrap, - bool *exit) + struct kvm_run *run, + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) { /* * Both SBI experimental and vendor extensions are * unconditionally forwarded to userspace. */ kvm_riscv_vcpu_sbi_forward(vcpu, run); - *exit =3D true; + edata->uexit =3D true; return 0; } =20 diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c index 619ac0f..5fb526c 100644 --- a/arch/riscv/kvm/vcpu_sbi_hsm.c +++ b/arch/riscv/kvm/vcpu_sbi_hsm.c @@ -21,9 +21,9 @@ static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu) =20 target_vcpu =3D kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid); if (!target_vcpu) - return -EINVAL; + return SBI_ERR_INVALID_PARAM; if (!target_vcpu->arch.power_off) - return -EALREADY; + return SBI_ERR_ALREADY_AVAILABLE; =20 reset_cntx =3D &target_vcpu->arch.guest_reset_context; /* start address */ @@ -42,7 +42,7 @@ static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu) static int kvm_sbi_hsm_vcpu_stop(struct kvm_vcpu *vcpu) { if (vcpu->arch.power_off) - return -EACCES; + return SBI_ERR_FAILURE; =20 kvm_riscv_vcpu_power_off(vcpu); =20 @@ -57,7 +57,7 @@ static int kvm_sbi_hsm_vcpu_get_status(struct kvm_vcpu *v= cpu) =20 target_vcpu =3D kvm_get_vcpu_by_id(vcpu->kvm, target_vcpuid); if (!target_vcpu) - return -EINVAL; + return SBI_ERR_INVALID_PARAM; if (!target_vcpu->arch.power_off) return SBI_HSM_STATE_STARTED; else if (vcpu->stat.generic.blocking) @@ -67,9 +67,8 @@ static int kvm_sbi_hsm_vcpu_get_status(struct kvm_vcpu *v= cpu) } =20 static int kvm_sbi_ext_hsm_handler(struct kvm_vcpu *vcpu, struct kvm_run *= run, - unsigned long *out_val, - struct kvm_cpu_trap *utrap, - bool *exit) + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) { int ret =3D 0; struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; @@ -88,27 +87,29 @@ static int kvm_sbi_ext_hsm_handler(struct kvm_vcpu *vcp= u, struct kvm_run *run, case SBI_EXT_HSM_HART_STATUS: ret =3D kvm_sbi_hsm_vcpu_get_status(vcpu); if (ret >=3D 0) { - *out_val =3D ret; - ret =3D 0; + edata->out_val =3D ret; + edata->err_val =3D 0; } - break; + return 0; case SBI_EXT_HSM_HART_SUSPEND: switch (cp->a0) { case SBI_HSM_SUSPEND_RET_DEFAULT: kvm_riscv_vcpu_wfi(vcpu); break; case SBI_HSM_SUSPEND_NON_RET_DEFAULT: - ret =3D -EOPNOTSUPP; + ret =3D SBI_ERR_NOT_SUPPORTED; break; default: - ret =3D -EINVAL; + ret =3D SBI_ERR_INVALID_PARAM; } break; default: - ret =3D -EOPNOTSUPP; + ret =3D SBI_ERR_NOT_SUPPORTED; } =20 - return ret; + edata->err_val =3D ret; + + return 0; } =20 const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm =3D { diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_re= place.c index 03a0198..abeb55f 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -14,15 +14,16 @@ #include =20 static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, - unsigned long *out_val, - struct kvm_cpu_trap *utrap, bool *exit) + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) { - int ret =3D 0; struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; u64 next_cycle; =20 - if (cp->a6 !=3D SBI_EXT_TIME_SET_TIMER) - return -EINVAL; + if (cp->a6 !=3D SBI_EXT_TIME_SET_TIMER) { + edata->err_val =3D SBI_ERR_INVALID_PARAM; + return 0; + } =20 #if __riscv_xlen =3D=3D 32 next_cycle =3D ((u64)cp->a1 << 32) | (u64)cp->a0; @@ -31,7 +32,7 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, #endif kvm_riscv_vcpu_timer_next_event(vcpu, next_cycle); =20 - return ret; + return 0; } =20 const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time =3D { @@ -41,8 +42,8 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time =3D= { }; =20 static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *= run, - unsigned long *out_val, - struct kvm_cpu_trap *utrap, bool *exit) + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) { int ret =3D 0; unsigned long i; @@ -51,8 +52,10 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, unsigned long hmask =3D cp->a0; unsigned long hbase =3D cp->a1; =20 - if (cp->a6 !=3D SBI_EXT_IPI_SEND_IPI) - return -EINVAL; + if (cp->a6 !=3D SBI_EXT_IPI_SEND_IPI) { + edata->err_val =3D SBI_ERR_INVALID_PARAM; + return 0; + } =20 kvm_for_each_vcpu(i, tmp, vcpu->kvm) { if (hbase !=3D -1UL) { @@ -76,10 +79,9 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi =3D= { }; =20 static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_ru= n *run, - unsigned long *out_val, - struct kvm_cpu_trap *utrap, bool *exit) + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) { - int ret =3D 0; struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; unsigned long hmask =3D cp->a0; unsigned long hbase =3D cp->a1; @@ -116,10 +118,10 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu= *vcpu, struct kvm_run *run */ break; default: - ret =3D -EOPNOTSUPP; + edata->err_val =3D SBI_ERR_NOT_SUPPORTED; } =20 - return ret; + return 0; } =20 const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence =3D { @@ -130,14 +132,13 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfen= ce =3D { =20 static int kvm_sbi_ext_srst_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, - unsigned long *out_val, - struct kvm_cpu_trap *utrap, bool *exit) + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) { struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; unsigned long funcid =3D cp->a6; u32 reason =3D cp->a1; u32 type =3D cp->a0; - int ret =3D 0; =20 switch (funcid) { case SBI_EXT_SRST_RESET: @@ -146,24 +147,24 @@ static int kvm_sbi_ext_srst_handler(struct kvm_vcpu *= vcpu, kvm_riscv_vcpu_sbi_system_reset(vcpu, run, KVM_SYSTEM_EVENT_SHUTDOWN, reason); - *exit =3D true; + edata->uexit =3D true; break; case SBI_SRST_RESET_TYPE_COLD_REBOOT: case SBI_SRST_RESET_TYPE_WARM_REBOOT: kvm_riscv_vcpu_sbi_system_reset(vcpu, run, KVM_SYSTEM_EVENT_RESET, reason); - *exit =3D true; + edata->uexit =3D true; break; default: - ret =3D -EOPNOTSUPP; + edata->err_val =3D SBI_ERR_NOT_SUPPORTED; } break; default: - ret =3D -EOPNOTSUPP; + edata->err_val =3D SBI_ERR_NOT_SUPPORTED; } =20 - return ret; + return 0; } =20 const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst =3D { diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c index 489f225..c0ccc58 100644 --- a/arch/riscv/kvm/vcpu_sbi_v01.c +++ b/arch/riscv/kvm/vcpu_sbi_v01.c @@ -14,9 +14,8 @@ #include =20 static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *= run, - unsigned long *out_val, - struct kvm_cpu_trap *utrap, - bool *exit) + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) { ulong hmask; int i, ret =3D 0; @@ -33,7 +32,7 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, * handled in kernel so we forward these to user-space */ kvm_riscv_vcpu_sbi_forward(vcpu, run); - *exit =3D true; + edata->uexit =3D true; break; case SBI_EXT_0_1_SET_TIMER: #if __riscv_xlen =3D=3D 32 @@ -65,7 +64,7 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, case SBI_EXT_0_1_SHUTDOWN: kvm_riscv_vcpu_sbi_system_reset(vcpu, run, KVM_SYSTEM_EVENT_SHUTDOWN, 0); - *exit =3D true; + edata->uexit =3D true; break; case SBI_EXT_0_1_REMOTE_FENCE_I: case SBI_EXT_0_1_REMOTE_SFENCE_VMA: @@ -103,7 +102,7 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcp= u, struct kvm_run *run, } break; default: - ret =3D -EINVAL; + edata->err_val =3D SBI_ERR_NOT_SUPPORTED; break; } =20 --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5DB2C61D97 for ; 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Fri, 27 Jan 2023 10:26:20 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:19 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 07/14] RISC-V: KVM: Add skeleton support for perf Date: Fri, 27 Jan 2023 10:25:51 -0800 Message-Id: <20230127182558.2416400-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch only adds barebore structure of perf implementation. Most of the function returns zero at this point and will be implemented fully in the future. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_host.h | 3 + arch/riscv/include/asm/kvm_vcpu_pmu.h | 76 ++++++++++++++ arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 5 + arch/riscv/kvm/vcpu_pmu.c | 145 ++++++++++++++++++++++++++ 5 files changed, 230 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_pmu.h create mode 100644 arch/riscv/kvm/vcpu_pmu.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 93f43a3..f9874b4 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -18,6 +18,7 @@ #include #include #include +#include =20 #define KVM_MAX_VCPUS 1024 =20 @@ -228,6 +229,8 @@ struct kvm_vcpu_arch { =20 /* Don't run the VCPU (blocked) */ bool pause; + + struct kvm_pmu pmu; }; =20 static inline void kvm_arch_hardware_unsetup(void) {} diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h new file mode 100644 index 0000000..3f43a43 --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#ifndef __KVM_VCPU_RISCV_PMU_H +#define __KVM_VCPU_RISCV_PMU_H + +#include +#include +#include + +#ifdef CONFIG_RISCV_PMU_SBI +#define RISCV_KVM_MAX_FW_CTRS 32 +#define RISCV_MAX_COUNTERS 64 + +/* Per virtual pmu counter data */ +struct kvm_pmc { + u8 idx; + struct perf_event *perf_event; + uint64_t counter_val; + union sbi_pmu_ctr_info cinfo; + /* Event monitoring status */ + bool started; +}; + +/* PMU data structure per vcpu */ +struct kvm_pmu { + struct kvm_pmc pmc[RISCV_MAX_COUNTERS]; + /* Number of the virtual firmware counters available */ + int num_fw_ctrs; + /* Number of the virtual hardware counters available */ + int num_hw_ctrs; + /* A flag to indicate that pmu initialization is done */ + bool init_done; + /* Bit map of all the virtual counter used */ + DECLARE_BITMAP(pmc_in_use, RISCV_MAX_COUNTERS); +}; + +#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu) +#define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) + +int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_= base, + unsigned long ctr_mask, unsigned long flag, uint64_t ival, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_b= ase, + unsigned long ctr_mask, unsigned long flag, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long = ctr_base, + unsigned long ctr_mask, unsigned long flag, + unsigned long eidx, uint64_t evtdata, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); + +#else +struct kvm_pmu { +}; + +static inline int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) +{ + return 0; +} +static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {} +static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {} +#endif /* CONFIG_RISCV_PMU_SBI */ +#endif /* !__KVM_VCPU_RISCV_PMU_H */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 019df920..5de1053 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -25,3 +25,4 @@ kvm-y +=3D vcpu_sbi_base.o kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_hsm.o kvm-y +=3D vcpu_timer.o +kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7c08567..b746f21 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -137,6 +137,7 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) =20 WRITE_ONCE(vcpu->arch.irqs_pending, 0); WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); + kvm_riscv_vcpu_pmu_reset(vcpu); =20 vcpu->arch.hfence_head =3D 0; vcpu->arch.hfence_tail =3D 0; @@ -194,6 +195,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) /* Setup VCPU timer */ kvm_riscv_vcpu_timer_init(vcpu); =20 + /* setup performance monitoring */ + kvm_riscv_vcpu_pmu_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); =20 @@ -216,6 +220,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) /* Cleanup VCPU timer */ kvm_riscv_vcpu_timer_deinit(vcpu); =20 + kvm_riscv_vcpu_pmu_deinit(vcpu); /* Free unused pages pre-allocated for G-stage page table mappings */ kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); } diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c new file mode 100644 index 0000000..d3fd551 --- /dev/null +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) + +int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _ext_data *edata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + edata->out_val =3D kvm_pmu_num_counters(kvpmu); + + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + if (cidx > RISCV_MAX_COUNTERS || cidx =3D=3D 1) { + edata->err_val =3D SBI_ERR_INVALID_PARAM; + return 0; + } + + edata->out_val =3D kvpmu->pmc[cidx].cinfo.value; + + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_= base, + unsigned long ctr_mask, unsigned long flag, uint64_t ival, + struct kvm_vcpu_sbi_ext_data *edata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_b= ase, + unsigned long ctr_mask, unsigned long flag, + struct kvm_vcpu_sbi_ext_data *edata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long = ctr_base, + unsigned long ctr_mask, unsigned long flag, + unsigned long eidx, uint64_t evtdata, + struct kvm_vcpu_sbi_ext_data *edata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) +{ + int i =3D 0, num_fw_ctrs, ret, num_hw_ctrs =3D 0, hpm_width =3D 0; + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + + ret =3D riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs); + if (ret < 0) + return ret; + + if (!hpm_width || !num_hw_ctrs) { + pr_err("Cannot initialize VCPU with NULL hpmcounter width or number of c= ounters\n"); + return -EINVAL; + } + + if ((num_hw_ctrs + RISCV_KVM_MAX_FW_CTRS) > RISCV_MAX_COUNTERS) { + pr_warn("Limiting fw counters as hw & fw counters exceed maximum counter= s\n"); + num_fw_ctrs =3D RISCV_MAX_COUNTERS - num_hw_ctrs; + } else + num_fw_ctrs =3D RISCV_KVM_MAX_FW_CTRS; + + kvpmu->num_hw_ctrs =3D num_hw_ctrs; + kvpmu->num_fw_ctrs =3D num_fw_ctrs; + + /* + * There is no correlation between the logical hardware counter and virtu= al counters. + * However, we need to encode a hpmcounter CSR in the counter info field = so that + * KVM can trap n emulate the read. This works well in the migration use = case as + * KVM doesn't care if the actual hpmcounter is available in the hardware= or not. + */ + for (i =3D 0; i < kvm_pmu_num_counters(kvpmu); i++) { + /* TIME CSR shouldn't be read from perf interface */ + if (i =3D=3D 1) + continue; + pmc =3D &kvpmu->pmc[i]; + pmc->idx =3D i; + if (i < kvpmu->num_hw_ctrs) { + kvpmu->pmc[i].cinfo.type =3D SBI_PMU_CTR_TYPE_HW; + if (i < 3) + /* CY, IR counters */ + kvpmu->pmc[i].cinfo.width =3D 63; + else + kvpmu->pmc[i].cinfo.width =3D hpm_width; + /* + * The CSR number doesn't have any relation with the logical + * hardware counters. The CSR numbers are encoded sequentially + * to avoid maintaining a map between the virtual counter + * and CSR number. + */ + pmc->cinfo.csr =3D CSR_CYCLE + i; + } else { + pmc->cinfo.type =3D SBI_PMU_CTR_TYPE_FW; + pmc->cinfo.width =3D BITS_PER_LONG - 1; + } + } + + kvpmu->init_done =3D true; + + return 0; +} + +void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) +{ + /* TODO */ +} + +void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) +{ + kvm_riscv_vcpu_pmu_deinit(vcpu); +} --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFF2FC38142 for ; Fri, 27 Jan 2023 18:26:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233874AbjA0S0r (ORCPT ); Fri, 27 Jan 2023 13:26:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235295AbjA0S0Y (ORCPT ); Fri, 27 Jan 2023 13:26:24 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D4407C327 for ; Fri, 27 Jan 2023 10:26:21 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id jm10so5833414plb.13 for ; Fri, 27 Jan 2023 10:26:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yZBj71qSb3+Aqnn9b5ZzRJQhfdhAJ0+/w4jzSKSrSG0=; b=aNBa46TcUSAaIYzEsEXoxK+K6UaJ27trR2LRtWhlroeZP8+4qMn4qHDpVUaLXyOqqS SsxYp5Ild2HPTcXbRh+qJZ9WgicgtHl2E1GbkiuBr0GDbj8CCl6SqD8SYOAKx6pczEjl MJ3iCXE43O9o1sqIYxImQvfN0UiiNGNKiGDPWPn0gzNqDbF5ouyQdT911q2Pk/OZ6YQT 2FoeisVf6i+eAomU9JIxZ9t/5x7aksViIfhATp/SNSCFNmn4q1xjP4Iad/sCTGyRkA/T hYmUwi3atuAJmSBf8bh0NqKY9uFcp05HGs3LpQZ1vpGQ/FeXTNC7LFoqO/Afpc57xcL5 4pfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yZBj71qSb3+Aqnn9b5ZzRJQhfdhAJ0+/w4jzSKSrSG0=; b=zhh5oBfJtk3J/gE1bUv2U/pbGS4mayN4FG1WA/1XJlDtVMGk3evXSDNnl3xrKlLCC3 CvoGObGbW+nx1ToIlIJVp3h4BKc5kLw8EuTP1iQHxf3JDTD0HBWmtTMLRwG2gz47BcRx ucP5674mHpc3Dv1YZec5qivGmeDs1zki2Vh937/oVfSRRT11AUKF9gDZr8rn7EFvdnC7 UqtyN09NGBBluJ2Q+nVE5dVTrBNP0wmoL/KSdxP/odX6ZVbKK2htEzWIkWJxqEc/iYl6 BWkEjfC1TXCd7oAnx9aq5OY5Vu+iFaaeiyZZwF0JqLCzH3FR9j3S2bX26rPJBdaddp7j TCoA== X-Gm-Message-State: AFqh2kqW+ntRUOXVoDQEadJr7r9gvqBEgLQMZ6etfJM/gRJJJr8aNmIT qdTcp4b6BAyOWZ4KuMgnrBeV3VIR+ecFM35+ X-Google-Smtp-Source: AMrXdXuFU4CliLgiqYcpuV5y49cJy2dQOPdEQpLWatH40jjemOVctQNIrj/jMPv+twKCdl6e5nlWmA== X-Received: by 2002:a17:902:8b83:b0:194:ab28:3268 with SMTP id ay3-20020a1709028b8300b00194ab283268mr34680188plb.34.1674843980961; Fri, 27 Jan 2023 10:26:20 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:20 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 08/14] RISC-V: KVM: Add SBI PMU extension support Date: Fri, 27 Jan 2023 10:25:52 -0800 Message-Id: <20230127182558.2416400-9-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SBI PMU extension allows KVM guests to configure/start/stop/query about the PMU counters in virtualized enviornment as well. In order to allow that, KVM implements the entire SBI PMU extension. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kvm/Makefile | 2 +- arch/riscv/kvm/vcpu_sbi.c | 11 +++++ arch/riscv/kvm/vcpu_sbi_pmu.c | 86 +++++++++++++++++++++++++++++++++++ 3 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/kvm/vcpu_sbi_pmu.c diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 5de1053..278e97c 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -25,4 +25,4 @@ kvm-y +=3D vcpu_sbi_base.o kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_hsm.o kvm-y +=3D vcpu_timer.o -kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o +kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o vcpu_sbi_pmu.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index aa42da6..04a3b4b 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -20,6 +20,16 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_= v01 =3D { }; #endif =20 +#ifdef CONFIG_RISCV_PMU_SBI +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu; +#else +static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu =3D { + .extid_start =3D -1UL, + .extid_end =3D -1UL, + .handler =3D NULL, +}; +#endif + static const struct kvm_vcpu_sbi_extension *sbi_ext[] =3D { &vcpu_sbi_ext_v01, &vcpu_sbi_ext_base, @@ -28,6 +38,7 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] =3D= { &vcpu_sbi_ext_rfence, &vcpu_sbi_ext_srst, &vcpu_sbi_ext_hsm, + &vcpu_sbi_ext_pmu, &vcpu_sbi_ext_experimental, &vcpu_sbi_ext_vendor, }; diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c new file mode 100644 index 0000000..73aab30 --- /dev/null +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include + +static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *= run, + struct kvm_vcpu_sbi_ext_data *edata, + struct kvm_cpu_trap *utrap) +{ + int ret =3D 0; + struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + unsigned long funcid =3D cp->a6; + uint64_t temp; + + /* Return not supported if PMU is not initialized */ + if (!kvpmu->init_done) + return -EINVAL; + + switch (funcid) { + case SBI_EXT_PMU_NUM_COUNTERS: + ret =3D kvm_riscv_vcpu_pmu_num_ctrs(vcpu, edata); + break; + case SBI_EXT_PMU_COUNTER_GET_INFO: + ret =3D kvm_riscv_vcpu_pmu_ctr_info(vcpu, cp->a0, edata); + break; + case SBI_EXT_PMU_COUNTER_CFG_MATCH: +#if defined(CONFIG_32BIT) + temp =3D ((uint64_t)cp->a5 << 32) | cp->a4; +#else + temp =3D cp->a4; +#endif + /* + * This can fail if perf core framework fails to create an event. + * Forward the error to the user space because its an error happened + * within host kernel. The other option would be convert this to + * an SBI error and forward to the guest. + */ + ret =3D kvm_riscv_vcpu_pmu_ctr_cfg_match(vcpu, cp->a0, cp->a1, + cp->a2, cp->a3, temp, edata); + break; + case SBI_EXT_PMU_COUNTER_START: +#if defined(CONFIG_32BIT) + temp =3D ((uint64_t)cp->a4 << 32) | cp->a3; +#else + temp =3D cp->a3; +#endif + ret =3D kvm_riscv_vcpu_pmu_ctr_start(vcpu, cp->a0, cp->a1, cp->a2, + temp, edata); + break; + case SBI_EXT_PMU_COUNTER_STOP: + ret =3D kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, edata); + break; + case SBI_EXT_PMU_COUNTER_FW_READ: + ret =3D kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, edata); + break; + default: + edata->err_val =3D SBI_ERR_NOT_SUPPORTED; + } + + return ret; +} + +unsigned long kvm_sbi_ext_pmu_probe(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + return kvpmu->init_done; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu =3D { + .extid_start =3D SBI_EXT_PMU, + .extid_end =3D SBI_EXT_PMU, + .handler =3D kvm_sbi_ext_pmu_handler, + .probe =3D kvm_sbi_ext_pmu_probe, +}; --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1212C38142 for ; Fri, 27 Jan 2023 18:26:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234609AbjA0S0t (ORCPT ); Fri, 27 Jan 2023 13:26:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235132AbjA0S01 (ORCPT ); Fri, 27 Jan 2023 13:26:27 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97D8F7F6AB for ; Fri, 27 Jan 2023 10:26:22 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id p24so5845052plw.11 for ; Fri, 27 Jan 2023 10:26:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VYOVEt3jt/KSlQQ1kq4H/LNDYTWOBqHX+UHxFdJqK+A=; b=kmh1lQGUzNyTV+SJvoAKXkHkMGjivjZAJea6T5Hr7EIlrPYBaMWMvcEiaLpqyM/KtS ePUoVDqeA8FMW6jaejIY4R3VgjOlyByf9TehWXCybvPMj+3uRjKWKop61ca/PFAC6MT4 u3APAiin9cC4fpcKBa+GtGHu3seYOHxtbVJgMIUBvfzxemER3gL+mJmlsb0jlsOtQ+oS uOR1c9hgmjpmrfdg2V/+etjez1klBx34/ATu64GSwu4Arvg8fJLRv0JOESyyZq5JJ4hV TMtYAzqqBm3p15eDA0DYzPXUxJxBvUsdN3ACp+QtTe86hJ8JnVWhd0xd34wW7zvkSCt7 3xuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VYOVEt3jt/KSlQQ1kq4H/LNDYTWOBqHX+UHxFdJqK+A=; b=VUrX+ancO7YXE+ZCa1yGq4OioxrO90Uw2GqSFi7yhM0IEnetaNk5iA8RfBuCziJa6y RzHO8Cs5mEmWBXbERloHO3miSh+hT7Sl/qPCQOenxk1G8b+xmaqunZcbbPxZbAmc1OWs WtcGDy+1+qyBq8aBEtPEwoce1dCP5hVx8YKsVveNyP5hxu5qXE1opawnCr/z+7V5CTiq 1jX4O6u0Nk+/DaZqhtp5V3CoZkKDQ5Il6vMvsWdqsu/jF5+XpPb5OvMZQXKG5VslmNy7 oxrjaXUOtnVOGd3P+izUILhhBhoeJ92b9gUtFBrGVIsU8s8dbLpZxT0tn3LD/L2k3KwI uleQ== X-Gm-Message-State: AFqh2krkU6EzHtx3g69kcl9aINX95ce4wvW4JLwLns0zXgenETy/ydFe 6pFUq9/bIJVSfLJ25BO3Jvx4fH5HWfLigm+D X-Google-Smtp-Source: AMrXdXv28M1C5TJfJZfYHoZMjXL4lC3hCwkbE2KMfgzJPjpOMAP1NeiIdUKuchXc6Zc48jYRIYXapQ== X-Received: by 2002:a17:902:e811:b0:194:5066:fc20 with SMTP id u17-20020a170902e81100b001945066fc20mr51140337plg.40.1674843981856; Fri, 27 Jan 2023 10:26:21 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:21 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Date: Fri, 27 Jan 2023 10:25:53 -0800 Message-Id: <20230127182558.2416400-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The privilege mode filtering feature must be available in the host so that the host can inhibit the counters while the execution is in HS mode. Otherwise, the guests may have access to critical guest information. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kvm/vcpu_pmu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index d3fd551..7713927 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -79,6 +79,14 @@ int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); struct kvm_pmc *pmc; =20 + /* + * PMU functionality should be only available to guests if privilege mode + * filtering is available in the host. Otherwise, guest will always count + * events while the execution is in hypervisor mode. + */ + if (!riscv_isa_extension_available(NULL, SSCOFPMF)) + return 0; + ret =3D riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs); if (ret < 0) return ret; --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F603C54EAA for ; Fri, 27 Jan 2023 18:26:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234842AbjA0S0x (ORCPT ); Fri, 27 Jan 2023 13:26:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235328AbjA0S02 (ORCPT ); Fri, 27 Jan 2023 13:26:28 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C12083959 for ; Fri, 27 Jan 2023 10:26:23 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id b10so5377367pjo.1 for ; Fri, 27 Jan 2023 10:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zm221noYPDv16VavlZywICLYGigsQ3r83tHpYQ6Bets=; b=ZcBhDH5tOacQHuA94vrShOzYvQg6QtjBICmN2cS9lLp1eNzFB5yxsNZPBOaH2GNR6m M5ZLuxW0OtCybveoStp55DxKU8uE0CxX5PfGQPKUBBnGgNvfRWDLBHWWcQjmA0eZe3bS 0gICApwRPkQqa5+iA0bzYwDiu+ARraoCbqtymSf1RtjJ56UefDcSvvHA9neCIP/RLe+L Kq89X4xXUrnImpbZxkgb6zSUkHEl9QULQMfmpvOi2kCMFN1Fd9u6yshUOIupfzv7+26D FQzOb1OxA5eOjhxcYwlwt3DoLbjMDjg9TaRwKVBqiHlJ9uZ+TfYZQI2DY6/BwGy43OOh EyfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zm221noYPDv16VavlZywICLYGigsQ3r83tHpYQ6Bets=; b=yOzytGGAwVZGaBXvfcaVQTpz8JjQ3PGUdmEUv52Xa6s47I94trM14Aq2SQdtfd2g0R FMg8ZiDcsjCTXUflRCmuzoWkhriKnHREJaGl5caNjJXjHlo0RRXOvMHASlEXel+WWTBu +3crtxuNkj+KdrOxm94ATYnmcBnbxBfo8MZuGGcEFeO48nhVxxCDZG07aDi1Q5oz6zLC r3C5F05gLW3YDmk9xuk7/DcJrLDAkSamdsCD220SuCyt026/KTxmuM+1kFCQXznJtmtR gu2fPGsT9EB59PCLdUkw7rnYsyv4i0sKzlrLLSW8xYHfCfN/DY5lK+c3de+uFcLaW7Op 61HQ== X-Gm-Message-State: AO0yUKVPbTZdOTEgAcw41EjEL2tN7vTwApDB7/VraqHpByf1qg+pc+Lr J5UV60WbpIJH5XrdrJde1vdpL3Br/juTEvr/ X-Google-Smtp-Source: AK7set8xtB8ZM17fWbgG9a9Hf0U5T4cRhB4mYsKyZy5+8l5WFp0aHNt9s3X7BhTHmtZJUgE/ku0LCQ== X-Received: by 2002:a05:6a20:8423:b0:bc:5a6:1b2a with SMTP id c35-20020a056a20842300b000bc05a61b2amr9264595pzd.49.1674843982840; Fri, 27 Jan 2023 10:26:22 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:22 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Date: Fri, 27 Jan 2023 10:25:54 -0800 Message-Id: <20230127182558.2416400-11-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Any guest must not get access to any hpmcounter including cycle/instret without any checks. We achieve that by disabling all the bits except TM bit in hcounteren. However, instret and cycle access for guest user space can be enabled upon explicit request (via ONE REG) or on first trap from VU mode to maintain ABI requirement in the future. This patch doesn't support that as ONE REG interface is not settled yet. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kvm/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 58c5489..c5d400f 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -49,7 +49,8 @@ int kvm_arch_hardware_enable(void) hideleg |=3D (1UL << IRQ_VS_EXT); csr_write(CSR_HIDELEG, hideleg); =20 - csr_write(CSR_HCOUNTEREN, -1UL); + /* VS should access only the time counter directly. Everything else shoul= d trap */ + csr_write(CSR_HCOUNTEREN, 0x02); =20 csr_write(CSR_HVIP, 0); =20 --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 088CBC61D97 for ; Fri, 27 Jan 2023 18:26:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235196AbjA0S04 (ORCPT ); Fri, 27 Jan 2023 13:26:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235303AbjA0S0g (ORCPT ); Fri, 27 Jan 2023 13:26:36 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87A2386E81 for ; Fri, 27 Jan 2023 10:26:24 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id m11so5397969pji.0 for ; Fri, 27 Jan 2023 10:26:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2eB56PlxVYYG9BW+idfsAIH60JlcBASeIP8IcBFqjbQ=; b=6tHALczfMbO8hse+3nrl1EO2mLFyq7flzJfTD3DpnSn2HXfxrnmud2b1bJLig7zxsC nbMCPzVzxWzfujxyIf3eM9MR3OpgNMIjwoO8ZOmLNNhMHi3n91saw1z16D3JdgLOR/4Z hl4TwdItUXrD6ixIe9gzHpd+70KjkqhLApicV8ke19vKhGbW7RtqcaqBgU4vRhojWRBH tfPbkA/cS2eonmVQKajbTs9Y40yZ5rJgSiq7h9X3lF7eKKpYieg0se7+8xtyI7UQk59Q 9KQWR7a3SMnndznUFFGX8jqJDkQS3sqrVaKWKImVrHp7RCW3k6MjZBqg/+bPCaHemItz NiCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2eB56PlxVYYG9BW+idfsAIH60JlcBASeIP8IcBFqjbQ=; b=gOV8Edma7toL0V4VMn0bDgCLSN6xT2sAojg32bHm7i8ORxpxuczpnFXJvkcVKAh1TF kBwr06q3aD/k21tc2Gx+XDVUsYNne8jcXY6URl+LIeQzmjr/gY/MA96fC8kA3fx3DQhw VsMEuVxrtjBM2M0q7ljcROOwXHDgqEd7k1bgvfrKG409/liH99syCil/SFu9jSotmTwG 4TXab9+ocwJij4o1iyHKzX3ufu2nLT3KLAJxcFcqnxQi11CNq0X+udYBmgXq4i24Ji3u uomRBd5nP4/wbvdqSA0p8s3vEWq5dO1mcgbRzIS86ie3Ssp6PJw3rJzpwYhjudPB81UK 7Zsw== X-Gm-Message-State: AO0yUKWB7osMS+hIhYmgBdC6ClDraxqnW7Hq45p+vWAX+FVMSvfaiD8/ 9YQ4zRt3peUeHVNV4SYB5rb5PHpleBjYVpdb X-Google-Smtp-Source: AK7set+oYbUUwtd4EAD6XiA8CIBGPbEJJpjDsAhrh7noLsI76uIOCbGORCnptpGlJUW1uUZsqmEGgA== X-Received: by 2002:a17:902:d4c8:b0:196:357f:9398 with SMTP id o8-20020a170902d4c800b00196357f9398mr10667341plg.34.1674843983718; Fri, 27 Jan 2023 10:26:23 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:23 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Date: Fri, 27 Jan 2023 10:25:55 -0800 Message-Id: <20230127182558.2416400-12-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As the KVM guests only see the virtual PMU counters, all hpmcounter access should trap and KVM emulates the read access on behalf of guests. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 16 ++++++++++ arch/riscv/kvm/vcpu_insn.c | 4 ++- arch/riscv/kvm/vcpu_pmu.c | 45 ++++++++++++++++++++++++++- 3 files changed, 63 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 3f43a43..022d45d 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -43,6 +43,19 @@ struct kvm_pmu { #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu) #define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) =20 +#if defined(CONFIG_32BIT) +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ +{ .base =3D CSR_CYCLEH, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_r= ead_hpm }, \ +{ .base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_re= ad_hpm }, +#else +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ +{ .base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_re= ad_hpm }, +#endif + +int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, + unsigned long *val, unsigned long new_val, + unsigned long wr_mask); + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _ext_data *edata); int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_ext_data *edata); @@ -65,6 +78,9 @@ void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); #else struct kvm_pmu { }; +#define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ +{ .base =3D 0, .count =3D 0, .func =3D NULL }, + =20 static inline int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) { diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 0bb5276..f689337 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -213,7 +213,9 @@ struct csr_func { unsigned long wr_mask); }; =20 -static const struct csr_func csr_funcs[] =3D { }; +static const struct csr_func csr_funcs[] =3D { + KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS +}; =20 /** * kvm_riscv_vcpu_csr_return -- Handle CSR read/write after user space diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 7713927..894053a 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -17,6 +17,44 @@ =20 #define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) =20 +static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + unsigned long *out_val) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + u64 enabled, running; + + pmc =3D &kvpmu->pmc[cidx]; + if (!pmc->perf_event) + return -EINVAL; + + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &r= unning); + *out_val =3D pmc->counter_val; + + return 0; +} + +int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, + unsigned long *val, unsigned long new_val, + unsigned long wr_mask) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int cidx, ret =3D KVM_INSN_CONTINUE_NEXT_SEPC; + + if (!kvpmu || !kvpmu->init_done) + return KVM_INSN_EXIT_TO_USER_SPACE; + + if (wr_mask) + return KVM_INSN_ILLEGAL_TRAP; + + cidx =3D csr_num - CSR_CYCLE; + + if (pmu_ctr_read(vcpu, cidx, val) < 0) + return KVM_INSN_EXIT_TO_USER_SPACE; + + return ret; +} + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _ext_data *edata) { struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); @@ -69,7 +107,12 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_ext_data *edata) { - /* TODO */ + int ret; + + ret =3D pmu_ctr_read(vcpu, cidx, &edata->out_val); + if (ret =3D=3D -EINVAL) + edata->err_val =3D SBI_ERR_INVALID_PARAM; + return 0; } =20 --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF364C54EAA for ; Fri, 27 Jan 2023 18:27:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235350AbjA0S06 (ORCPT ); Fri, 27 Jan 2023 13:26:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235351AbjA0S0g (ORCPT ); Fri, 27 Jan 2023 13:26:36 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C26386E8E for ; Fri, 27 Jan 2023 10:26:25 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id o13so5376648pjg.2 for ; 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Fri, 27 Jan 2023 10:26:24 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:24 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 12/14] RISC-V: KVM: Implement perf support without sampling Date: Fri, 27 Jan 2023 10:25:56 -0800 Message-Id: <20230127182558.2416400-13-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RISC-V SBI PMU & Sscofpmf ISA extension allows supporting perf in the virtualization enviornment as well. KVM implementation relies on SBI PMU extension for the most part while trapping & emulating the CSRs read for counter access. This patch doesn't have the event sampling support yet. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kvm/vcpu_pmu.c | 366 +++++++++++++++++++++++++++++++++++++- 1 file changed, 360 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 894053a..73dccf7 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -12,10 +12,190 @@ #include #include #include +#include #include #include =20 #define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) +#define get_event_type(x) (((x) & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16) +#define get_event_code(x) ((x) & SBI_PMU_EVENT_IDX_CODE_MASK) + + +static enum perf_hw_id hw_event_perf_map[SBI_PMU_HW_GENERAL_MAX] =3D { + [SBI_PMU_HW_CPU_CYCLES] =3D PERF_COUNT_HW_CPU_CYCLES, + [SBI_PMU_HW_INSTRUCTIONS] =3D PERF_COUNT_HW_INSTRUCTIONS, + [SBI_PMU_HW_CACHE_REFERENCES] =3D PERF_COUNT_HW_CACHE_REFERENCES, + [SBI_PMU_HW_CACHE_MISSES] =3D PERF_COUNT_HW_CACHE_MISSES, + [SBI_PMU_HW_BRANCH_INSTRUCTIONS] =3D PERF_COUNT_HW_BRANCH_INSTRUCTIONS, + [SBI_PMU_HW_BRANCH_MISSES] =3D PERF_COUNT_HW_BRANCH_MISSES, + [SBI_PMU_HW_BUS_CYCLES] =3D PERF_COUNT_HW_BUS_CYCLES, + [SBI_PMU_HW_STALLED_CYCLES_FRONTEND] =3D PERF_COUNT_HW_STALLED_CYCLES_FRO= NTEND, + [SBI_PMU_HW_STALLED_CYCLES_BACKEND] =3D PERF_COUNT_HW_STALLED_CYCLES_BACK= END, + [SBI_PMU_HW_REF_CPU_CYCLES] =3D PERF_COUNT_HW_REF_CPU_CYCLES, +}; + +static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc) +{ + u64 counter_val_mask =3D GENMASK(pmc->cinfo.width, 0); + u64 sample_period; + + if (!pmc->counter_val) + sample_period =3D counter_val_mask + 1; + else + sample_period =3D (-pmc->counter_val) & counter_val_mask; + + return sample_period; +} + +static u32 kvm_pmu_get_perf_event_type(unsigned long eidx) +{ + enum sbi_pmu_event_type etype =3D get_event_type(eidx); + u32 type =3D PERF_TYPE_MAX; + + switch (etype) { + case SBI_PMU_EVENT_TYPE_HW: + type =3D PERF_TYPE_HARDWARE; + break; + case SBI_PMU_EVENT_TYPE_CACHE: + type =3D PERF_TYPE_HW_CACHE; + break; + case SBI_PMU_EVENT_TYPE_RAW: + case SBI_PMU_EVENT_TYPE_FW: + type =3D PERF_TYPE_RAW; + break; + default: + break; + } + + return type; +} + +static bool kvm_pmu_is_fw_event(unsigned long eidx) +{ + return get_event_type(eidx) =3D=3D SBI_PMU_EVENT_TYPE_FW; +} + +static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc) +{ + if (pmc->perf_event) { + perf_event_disable(pmc->perf_event); + perf_event_release_kernel(pmc->perf_event); + pmc->perf_event =3D NULL; + } +} + +static u64 kvm_pmu_get_perf_event_hw_config(u32 sbi_event_code) +{ + return hw_event_perf_map[sbi_event_code]; +} + +static u64 kvm_pmu_get_perf_event_cache_config(u32 sbi_event_code) +{ + u64 config =3D U64_MAX; + unsigned int cache_type, cache_op, cache_result; + + /* All the cache event masks lie within 0xFF. No separate masking is nece= sssary */ + cache_type =3D (sbi_event_code & SBI_PMU_EVENT_CACHE_ID_CODE_MASK) >> + SBI_PMU_EVENT_CACHE_ID_SHIFT; + cache_op =3D (sbi_event_code & SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK) >> + SBI_PMU_EVENT_CACHE_OP_SHIFT; + cache_result =3D sbi_event_code & SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK; + + if (cache_type >=3D PERF_COUNT_HW_CACHE_MAX || + cache_op >=3D PERF_COUNT_HW_CACHE_OP_MAX || + cache_result >=3D PERF_COUNT_HW_CACHE_RESULT_MAX) + return config; + + config =3D cache_type | (cache_op << 8) | (cache_result << 16); + + return config; +} + +static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_= data) +{ + enum sbi_pmu_event_type etype =3D get_event_type(eidx); + u32 ecode =3D get_event_code(eidx); + u64 config =3D U64_MAX; + + switch (etype) { + case SBI_PMU_EVENT_TYPE_HW: + if (ecode < SBI_PMU_HW_GENERAL_MAX) + config =3D kvm_pmu_get_perf_event_hw_config(ecode); + break; + case SBI_PMU_EVENT_TYPE_CACHE: + config =3D kvm_pmu_get_perf_event_cache_config(ecode); + break; + case SBI_PMU_EVENT_TYPE_RAW: + config =3D evt_data & RISCV_PMU_RAW_EVENT_MASK; + break; + case SBI_PMU_EVENT_TYPE_FW: + if (ecode < SBI_PMU_FW_MAX) + config =3D (1ULL << 63) | ecode; + break; + default: + break; + } + + return config; +} + +static int kvm_pmu_get_fixed_pmc_index(unsigned long eidx) +{ + u32 etype =3D kvm_pmu_get_perf_event_type(eidx); + u32 ecode =3D get_event_code(eidx); + + if (etype !=3D SBI_PMU_EVENT_TYPE_HW) + return -EINVAL; + + if (ecode =3D=3D SBI_PMU_HW_CPU_CYCLES) + return 0; + else if (ecode =3D=3D SBI_PMU_HW_INSTRUCTIONS) + return 2; + else + return -EINVAL; +} + +static int kvm_pmu_get_programmable_pmc_index(struct kvm_pmu *kvpmu, unsig= ned long eidx, + unsigned long cbase, unsigned long cmask) +{ + int ctr_idx =3D -1; + int i, pmc_idx; + int min, max; + + if (kvm_pmu_is_fw_event(eidx)) { + /* Firmware counters are mapped 1:1 starting from num_hw_ctrs for simpli= city */ + min =3D kvpmu->num_hw_ctrs; + max =3D min + kvpmu->num_fw_ctrs; + } else { + /* First 3 counters are reserved for fixed counters */ + min =3D 3; + max =3D kvpmu->num_hw_ctrs; + } + + for_each_set_bit(i, &cmask, BITS_PER_LONG) { + pmc_idx =3D i + cbase; + if ((pmc_idx >=3D min && pmc_idx < max) && + !test_bit(pmc_idx, kvpmu->pmc_in_use)) { + ctr_idx =3D pmc_idx; + break; + } + } + + return ctr_idx; +} + +static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsigned long eidx, + unsigned long cbase, unsigned long cmask) +{ + int ret; + + /* Fixed counters need to be have fixed mapping as they have different wi= dth */ + ret =3D kvm_pmu_get_fixed_pmc_index(eidx); + if (ret >=3D 0) + return ret; + + return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask); +} =20 static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, unsigned long *out_val) @@ -34,6 +214,16 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned= long cidx, return 0; } =20 +static int kvm_pmu_validate_counter_mask(struct kvm_pmu *kvpmu, unsigned l= ong ctr_base, + unsigned long ctr_mask) +{ + /* Make sure the we have a valid counter mask requested from the caller */ + if (!ctr_mask || (ctr_base + __fls(ctr_mask) >=3D kvm_pmu_num_counters(kv= pmu))) + return -EINVAL; + + return 0; +} + int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, unsigned long new_val, unsigned long wr_mask) @@ -83,7 +273,39 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu,= unsigned long ctr_base, unsigned long ctr_mask, unsigned long flag, uint64_t ival, struct kvm_vcpu_sbi_ext_data *edata) { - /* TODO */ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int i, pmc_index, sbiret =3D 0; + struct kvm_pmc *pmc; + + if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + /* Start the counters that have been configured and requested by the gues= t */ + for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { + pmc_index =3D i + ctr_base; + if (!test_bit(pmc_index, kvpmu->pmc_in_use)) + continue; + pmc =3D &kvpmu->pmc[pmc_index]; + if (flag & SBI_PMU_START_FLAG_SET_INIT_VALUE) + pmc->counter_val =3D ival; + if (pmc->perf_event) { + if (unlikely(pmc->started)) { + sbiret =3D SBI_ERR_ALREADY_STARTED; + continue; + } + perf_event_period(pmc->perf_event, kvm_pmu_get_sample_period(pmc)); + perf_event_enable(pmc->perf_event); + pmc->started =3D true; + } else { + sbiret =3D SBI_ERR_INVALID_PARAM; + } + } + +out: + edata->err_val =3D sbiret; + return 0; } =20 @@ -91,7 +313,45 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, = unsigned long ctr_base, unsigned long ctr_mask, unsigned long flag, struct kvm_vcpu_sbi_ext_data *edata) { - /* TODO */ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + int i, pmc_index, sbiret =3D 0; + u64 enabled, running; + struct kvm_pmc *pmc; + + if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + /* Stop the counters that have been configured and requested by the guest= */ + for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { + pmc_index =3D i + ctr_base; + if (!test_bit(pmc_index, kvpmu->pmc_in_use)) + continue; + pmc =3D &kvpmu->pmc[pmc_index]; + if (pmc->perf_event) { + if (pmc->started) { + /* Stop counting the counter */ + perf_event_disable(pmc->perf_event); + pmc->started =3D false; + } else + sbiret =3D SBI_ERR_ALREADY_STOPPED; + + if (flag & SBI_PMU_STOP_FLAG_RESET) { + /* Relase the counter if this is a reset request */ + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, + &enabled, &running); + kvm_pmu_release_perf_event(pmc); + clear_bit(pmc_index, kvpmu->pmc_in_use); + } + } else { + sbiret =3D SBI_ERR_INVALID_PARAM; + } + } + +out: + edata->err_val =3D sbiret; + return 0; } =20 @@ -100,7 +360,89 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *= vcpu, unsigned long ctr_ba unsigned long eidx, uint64_t evtdata, struct kvm_vcpu_sbi_ext_data *edata) { - /* TODO */ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct perf_event *event; + int ctr_idx; + u32 etype =3D kvm_pmu_get_perf_event_type(eidx); + u64 config; + struct kvm_pmc *pmc; + int sbiret =3D 0; + struct perf_event_attr attr =3D { + .type =3D etype, + .size =3D sizeof(struct perf_event_attr), + .pinned =3D true, + /* + * It should never reach here if the platform doesn't support the sscofp= mf + * extension as mode filtering won't work without it. + */ + .exclude_host =3D true, + .exclude_hv =3D true, + .exclude_user =3D !!(flag & SBI_PMU_CFG_FLAG_SET_UINH), + .exclude_kernel =3D !!(flag & SBI_PMU_CFG_FLAG_SET_SINH), + .config1 =3D RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS, + }; + + if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + if (kvm_pmu_is_fw_event(eidx)) { + sbiret =3D SBI_ERR_NOT_SUPPORTED; + goto out; + } + + /* + * SKIP_MATCH flag indicates the caller is aware of the assigned counter + * for this event. Just do a sanity check if it already marked used. + */ + if (flag & SBI_PMU_CFG_FLAG_SKIP_MATCH) { + if (!test_bit(ctr_base + __ffs(ctr_mask), kvpmu->pmc_in_use)) { + sbiret =3D SBI_ERR_FAILURE; + goto out; + } + ctr_idx =3D ctr_base + __ffs(ctr_mask); + } else { + + ctr_idx =3D pmu_get_pmc_index(kvpmu, eidx, ctr_base, ctr_mask); + if (ctr_idx < 0) { + sbiret =3D SBI_ERR_NOT_SUPPORTED; + goto out; + } + } + + pmc =3D &kvpmu->pmc[ctr_idx]; + kvm_pmu_release_perf_event(pmc); + pmc->idx =3D ctr_idx; + + config =3D kvm_pmu_get_perf_event_config(eidx, evtdata); + attr.config =3D config; + if (flag & SBI_PMU_CFG_FLAG_CLEAR_VALUE) { + //TODO: Do we really want to clear the value in hardware counter + pmc->counter_val =3D 0; + } + + /* + * Set the default sample_period for now. The guest specified value + * will be updated in the start call. + */ + attr.sample_period =3D kvm_pmu_get_sample_period(pmc); + + event =3D perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc); + if (IS_ERR(event)) { + pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); + return PTR_ERR(event); + } + + set_bit(ctr_idx, kvpmu->pmc_in_use); + pmc->perf_event =3D event; + if (flag & SBI_PMU_CFG_FLAG_AUTO_START) + perf_event_enable(pmc->perf_event); + + edata->out_val =3D ctr_idx; +out: + edata->err_val =3D sbiret; + return 0; } =20 @@ -164,9 +506,9 @@ int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) kvpmu->pmc[i].cinfo.type =3D SBI_PMU_CTR_TYPE_HW; if (i < 3) /* CY, IR counters */ - kvpmu->pmc[i].cinfo.width =3D 63; + pmc->cinfo.width =3D 63; else - kvpmu->pmc[i].cinfo.width =3D hpm_width; + pmc->cinfo.width =3D hpm_width; /* * The CSR number doesn't have any relation with the logical * hardware counters. The CSR numbers are encoded sequentially @@ -187,7 +529,19 @@ int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) =20 void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) { - /* TODO */ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + int i; + + if (!kvpmu) + return; + + for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_MAX_COUNTERS) { + pmc =3D &kvpmu->pmc[i]; + pmc->counter_val =3D 0; + kvm_pmu_release_perf_event(pmc); + } + bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); } =20 void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5194CC54EAA for ; Fri, 27 Jan 2023 18:27:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235422AbjA0S1J (ORCPT ); Fri, 27 Jan 2023 13:27:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235361AbjA0S0l (ORCPT ); Fri, 27 Jan 2023 13:26:41 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49FBA86EA4 for ; Fri, 27 Jan 2023 10:26:26 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id nn18-20020a17090b38d200b0022bfb584987so5533642pjb.2 for ; Fri, 27 Jan 2023 10:26:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GryYCsA0yB0D+er6B3vBmQcLGa+75ViLyEbdS+lBcgo=; b=lHG0Ie1rTp5lC9PUj6YQU6LNQROHBz/272/cbOF9xQ+6C+Cw38RwiPJZjGnwle8ZKl /G2yvqUFWR7sDaj9BoAfegij6enI9Yd6tCcexmxqWE2GURfI1iNdE2/RIGoFMtz5orEw f6WhXD9gUaM+VROyoeeNoYbfT8A6gbhBjlZg7lmvEjxFxLm/OX8OnQ0xAXIsOW6j+ivU 3uKQh0IKBpHrzlAxgCL6pmbbMWj5U4mFToSwd6wuLhO18fo5W8adTVtFaDFvw3HH7gbC HDBMBkhhbTEeC5mTDSDC6NgCl5gX3KvglWS3VmBMCsJ9m3riwfYFalE0q9I5S2cZ4krY 9Ozg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GryYCsA0yB0D+er6B3vBmQcLGa+75ViLyEbdS+lBcgo=; b=RCdZLkA1vtKgF1uRu2w6KOvAVoqoNn0+3Utqr2KvP4/rHq0yT8LOxmzPIdaDzBrmjX SmFkOFqlQeMseZIgI059f9f8sQeq4kiwJTli1lHfUKT4kUnW6KO58J7/yaTYH6zfybcm TEnhRNbJYkOZW7KJOU3yhm4KPak6ft9VqBrXc9XlAK+j3qYT2xyeB55aWLxA+Jsob8VR GOYlmm8ksCU1FpJz3I6VmA5jUO4SYDuR6MXDWWpPVaDLrtaZ5broff32QLpyy2stU6kq CxAxSN5ApODlKzIeP+4XS3DIGp3FZpyvHuLrQX/tQPFMyorYjyzl7mjPmI6Z/p5cTf3X mYzw== X-Gm-Message-State: AFqh2ko96+nTq+34GU/IKGbncgksQkLy1InvM4SCuSb4tmRHNJRgyI4c OcX/HlUy1nh50dIEvlMC8iCTpr4xcUCZlnIi X-Google-Smtp-Source: AMrXdXtwhrGvRJDshZBYkWk+n45XcY8z1cBLChY8kIMUk+uU4qS2IBsiCRy6f2rdq9A7AB4oC8aoNw== X-Received: by 2002:a17:903:1211:b0:194:d999:33f0 with SMTP id l17-20020a170903121100b00194d99933f0mr34943270plh.31.1674843985569; Fri, 27 Jan 2023 10:26:25 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:25 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 13/14] RISC-V: KVM: Support firmware events Date: Fri, 27 Jan 2023 10:25:57 -0800 Message-Id: <20230127182558.2416400-14-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SBI PMU extension defines a set of firmware events which can provide useful information to guests about number of SBI calls. As hypervisor implements the SBI PMU extension, these firmware events corresponds to ecall invocations between VS->HS mode. All other firmware events will always report zero if monitored as KVM doesn't implement them. This patch adds all the infrastructure required to support firmware events. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 16 +++ arch/riscv/kvm/vcpu_pmu.c | 144 +++++++++++++++++++------- 2 files changed, 124 insertions(+), 36 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 022d45d..b235e7e 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -17,6 +17,14 @@ #define RISCV_KVM_MAX_FW_CTRS 32 #define RISCV_MAX_COUNTERS 64 =20 +struct kvm_fw_event { + /* Current value of the event */ + unsigned long value; + + /* Event monitoring status */ + bool started; +}; + /* Per virtual pmu counter data */ struct kvm_pmc { u8 idx; @@ -25,11 +33,14 @@ struct kvm_pmc { union sbi_pmu_ctr_info cinfo; /* Event monitoring status */ bool started; + /* Monitoring event ID */ + unsigned long event_idx; }; =20 /* PMU data structure per vcpu */ struct kvm_pmu { struct kvm_pmc pmc[RISCV_MAX_COUNTERS]; + struct kvm_fw_event fw_event[RISCV_KVM_MAX_FW_CTRS]; /* Number of the virtual firmware counters available */ int num_fw_ctrs; /* Number of the virtual hardware counters available */ @@ -52,6 +63,7 @@ struct kvm_pmu { { .base =3D CSR_CYCLE, .count =3D 31, .func =3D kvm_riscv_vcpu_pmu_re= ad_hpm }, #endif =20 +int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid); int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, unsigned long new_val, unsigned long wr_mask); @@ -81,6 +93,10 @@ struct kvm_pmu { #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \ { .base =3D 0, .count =3D 0, .func =3D NULL }, =20 +static inline int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsign= ed long fid) +{ + return 0; +} =20 static inline int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) { diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 73dccf7..b8d6aba 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -203,12 +203,15 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsign= ed long cidx, struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); struct kvm_pmc *pmc; u64 enabled, running; + int fevent_code; =20 pmc =3D &kvpmu->pmc[cidx]; - if (!pmc->perf_event) - return -EINVAL; =20 - pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &r= unning); + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + fevent_code =3D get_event_code(pmc->event_idx); + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; + } else if (pmc->perf_event) + pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &= running); *out_val =3D pmc->counter_val; =20 return 0; @@ -224,6 +227,55 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pm= u *kvpmu, unsigned long ct return 0; } =20 +static int kvm_pmu_create_perf_event(struct kvm_pmc *pmc, int ctr_idx, + struct perf_event_attr *attr, unsigned long flag, + unsigned long eidx, unsigned long evtdata) +{ + struct perf_event *event; + + kvm_pmu_release_perf_event(pmc); + pmc->idx =3D ctr_idx; + + attr->config =3D kvm_pmu_get_perf_event_config(eidx, evtdata); + if (flag & SBI_PMU_CFG_FLAG_CLEAR_VALUE) { + //TODO: Do we really want to clear the value in hardware counter + pmc->counter_val =3D 0; + } + + /* + * Set the default sample_period for now. The guest specified value + * will be updated in the start call. + */ + attr->sample_period =3D kvm_pmu_get_sample_period(pmc); + + event =3D perf_event_create_kernel_counter(attr, -1, current, NULL, pmc); + if (IS_ERR(event)) { + pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); + return PTR_ERR(event); + } + + pmc->perf_event =3D event; + if (flag & SBI_PMU_CFG_FLAG_AUTO_START) + perf_event_enable(pmc->perf_event); + + return 0; +} + +int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + struct kvm_fw_event *fevent; + + if (!kvpmu || fid >=3D SBI_PMU_FW_MAX) + return -EINVAL; + + fevent =3D &kvpmu->fw_event[fid]; + if (fevent->started) + fevent->value++; + + return 0; +} + int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_nu= m, unsigned long *val, unsigned long new_val, unsigned long wr_mask) @@ -276,6 +328,7 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu,= unsigned long ctr_base, struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); int i, pmc_index, sbiret =3D 0; struct kvm_pmc *pmc; + int fevent_code; =20 if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret =3D SBI_ERR_INVALID_PARAM; @@ -290,7 +343,22 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu= , unsigned long ctr_base, pmc =3D &kvpmu->pmc[pmc_index]; if (flag & SBI_PMU_START_FLAG_SET_INIT_VALUE) pmc->counter_val =3D ival; - if (pmc->perf_event) { + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + fevent_code =3D get_event_code(pmc->event_idx); + if (fevent_code >=3D SBI_PMU_FW_MAX) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + /* Check if the counter was already started for some reason */ + if (kvpmu->fw_event[fevent_code].started) { + sbiret =3D SBI_ERR_ALREADY_STARTED; + continue; + } + + kvpmu->fw_event[fevent_code].started =3D true; + kvpmu->fw_event[fevent_code].value =3D pmc->counter_val; + } else if (pmc->perf_event) { if (unlikely(pmc->started)) { sbiret =3D SBI_ERR_ALREADY_STARTED; continue; @@ -317,6 +385,7 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, = unsigned long ctr_base, int i, pmc_index, sbiret =3D 0; u64 enabled, running; struct kvm_pmc *pmc; + int fevent_code; =20 if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret =3D SBI_ERR_INVALID_PARAM; @@ -329,7 +398,18 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,= unsigned long ctr_base, if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; pmc =3D &kvpmu->pmc[pmc_index]; - if (pmc->perf_event) { + if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + fevent_code =3D get_event_code(pmc->event_idx); + if (fevent_code >=3D SBI_PMU_FW_MAX) { + sbiret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + if (!kvpmu->fw_event[fevent_code].started) + sbiret =3D SBI_ERR_ALREADY_STOPPED; + + kvpmu->fw_event[fevent_code].started =3D false; + } else if (pmc->perf_event) { if (pmc->started) { /* Stop counting the counter */ perf_event_disable(pmc->perf_event); @@ -342,11 +422,14 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu= , unsigned long ctr_base, pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &running); kvm_pmu_release_perf_event(pmc); - clear_bit(pmc_index, kvpmu->pmc_in_use); } } else { sbiret =3D SBI_ERR_INVALID_PARAM; } + if (flag & SBI_PMU_STOP_FLAG_RESET) { + pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; + clear_bit(pmc_index, kvpmu->pmc_in_use); + } } =20 out: @@ -361,12 +444,11 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu = *vcpu, unsigned long ctr_ba struct kvm_vcpu_sbi_ext_data *edata) { struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); - struct perf_event *event; - int ctr_idx; + int ctr_idx, sbiret =3D 0, ret; u32 etype =3D kvm_pmu_get_perf_event_type(eidx); - u64 config; - struct kvm_pmc *pmc; - int sbiret =3D 0; + struct kvm_pmc *pmc =3D NULL; + bool is_fevent; + unsigned long event_code; struct perf_event_attr attr =3D { .type =3D etype, .size =3D sizeof(struct perf_event_attr), @@ -387,7 +469,9 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *v= cpu, unsigned long ctr_ba goto out; } =20 - if (kvm_pmu_is_fw_event(eidx)) { + event_code =3D get_event_code(eidx); + is_fevent =3D kvm_pmu_is_fw_event(eidx); + if (is_fevent && event_code >=3D SBI_PMU_FW_MAX) { sbiret =3D SBI_ERR_NOT_SUPPORTED; goto out; } @@ -412,33 +496,17 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu = *vcpu, unsigned long ctr_ba } =20 pmc =3D &kvpmu->pmc[ctr_idx]; - kvm_pmu_release_perf_event(pmc); - pmc->idx =3D ctr_idx; - - config =3D kvm_pmu_get_perf_event_config(eidx, evtdata); - attr.config =3D config; - if (flag & SBI_PMU_CFG_FLAG_CLEAR_VALUE) { - //TODO: Do we really want to clear the value in hardware counter - pmc->counter_val =3D 0; - } - - /* - * Set the default sample_period for now. The guest specified value - * will be updated in the start call. - */ - attr.sample_period =3D kvm_pmu_get_sample_period(pmc); - - event =3D perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc); - if (IS_ERR(event)) { - pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ER= R(event)); - return PTR_ERR(event); + if (is_fevent) { + if (flag & SBI_PMU_CFG_FLAG_AUTO_START) + kvpmu->fw_event[event_code].started =3D true; + } else { + ret =3D kvm_pmu_create_perf_event(pmc, ctr_idx, &attr, flag, eidx, evtda= ta); + if (ret) + return ret; } =20 set_bit(ctr_idx, kvpmu->pmc_in_use); - pmc->perf_event =3D event; - if (flag & SBI_PMU_CFG_FLAG_AUTO_START) - perf_event_enable(pmc->perf_event); - + pmc->event_idx =3D eidx; edata->out_val =3D ctr_idx; out: edata->err_val =3D sbiret; @@ -489,6 +557,7 @@ int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) =20 kvpmu->num_hw_ctrs =3D num_hw_ctrs; kvpmu->num_fw_ctrs =3D num_fw_ctrs; + memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); =20 /* * There is no correlation between the logical hardware counter and virtu= al counters. @@ -502,6 +571,7 @@ int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) continue; pmc =3D &kvpmu->pmc[i]; pmc->idx =3D i; + pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; if (i < kvpmu->num_hw_ctrs) { kvpmu->pmc[i].cinfo.type =3D SBI_PMU_CTR_TYPE_HW; if (i < 3) @@ -540,8 +610,10 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) pmc =3D &kvpmu->pmc[i]; pmc->counter_val =3D 0; kvm_pmu_release_perf_event(pmc); + pmc->event_idx =3D SBI_PMU_EVENT_IDX_INVALID; } bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); + memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); } =20 void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) --=20 2.25.1 From nobody Sun Sep 14 01:41:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAC9BC61DA4 for ; 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Fri, 27 Jan 2023 10:26:26 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jc5-20020a17090325c500b00189d4c666c8sm3195219plb.153.2023.01.27.10.26.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 10:26:26 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , Heiko Stuebner , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Will Deacon Subject: [PATCH v3 14/14] RISC-V: KVM: Increment firmware pmu events Date: Fri, 27 Jan 2023 10:25:58 -0800 Message-Id: <20230127182558.2416400-15-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127182558.2416400-1-atishp@rivosinc.com> References: <20230127182558.2416400-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" KVM supports firmware events now. Invoke the firmware event increment function from appropriate places. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- arch/riscv/kvm/tlb.c | 4 ++++ arch/riscv/kvm/vcpu_sbi_replace.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c index 309d79b..b797f7c 100644 --- a/arch/riscv/kvm/tlb.c +++ b/arch/riscv/kvm/tlb.c @@ -181,6 +181,7 @@ void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu) =20 void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu) { + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_RCVD); local_flush_icache_all(); } =20 @@ -264,15 +265,18 @@ void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu) d.addr, d.size, d.order); break; case KVM_RISCV_HFENCE_VVMA_ASID_GVA: + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); kvm_riscv_local_hfence_vvma_asid_gva( READ_ONCE(v->vmid), d.asid, d.addr, d.size, d.order); break; case KVM_RISCV_HFENCE_VVMA_ASID_ALL: + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); kvm_riscv_local_hfence_vvma_asid_all( READ_ONCE(v->vmid), d.asid); break; case KVM_RISCV_HFENCE_VVMA_GVA: + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD); kvm_riscv_local_hfence_vvma_gva( READ_ONCE(v->vmid), d.addr, d.size, d.order); diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_re= place.c index abeb55f..71a671e 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run = *run, @@ -25,6 +26,7 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, return 0; } =20 + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_SET_TIMER); #if __riscv_xlen =3D=3D 32 next_cycle =3D ((u64)cp->a1 << 32) | (u64)cp->a0; #else @@ -57,6 +59,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, return 0; } =20 + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_IPI_SENT); kvm_for_each_vcpu(i, tmp, vcpu->kvm) { if (hbase !=3D -1UL) { if (tmp->vcpu_id < hbase) @@ -67,6 +70,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, ret =3D kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT); if (ret < 0) break; + kvm_riscv_vcpu_pmu_incr_fw(tmp, SBI_PMU_FW_IPI_RECVD); } =20 return ret; @@ -90,6 +94,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vc= pu, struct kvm_run *run switch (funcid) { case SBI_EXT_RFENCE_REMOTE_FENCE_I: kvm_riscv_fence_i(vcpu->kvm, hbase, hmask); + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_SENT); break; case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: if (cp->a2 =3D=3D 0 && cp->a3 =3D=3D 0) @@ -97,6 +102,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *v= cpu, struct kvm_run *run else kvm_riscv_hfence_vvma_gva(vcpu->kvm, hbase, hmask, cp->a2, cp->a3, PAGE_SHIFT); + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_SENT); break; case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: if (cp->a2 =3D=3D 0 && cp->a3 =3D=3D 0) @@ -107,6 +113,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *= vcpu, struct kvm_run *run hbase, hmask, cp->a2, cp->a3, PAGE_SHIFT, cp->a4); + kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_SENT); break; case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: --=20 2.25.1