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Fri, 27 Jan 2023 11:41:50 +0000 From: Joey Gouly To: Andrew Jones , , CC: , Alexandru Elisei , Christoffer Dall , Fuad Tabba , Jean-Philippe Brucker , Joey Gouly , Marc Zyngier , Mark Rutland , Oliver Upton , Paolo Bonzini , Quentin Perret , Steven Price , Suzuki K Poulose , "Thomas Huth" , Will Deacon , Zenghui Yu , , , , Subject: [RFC kvm-unit-tests 07/27] arm: realm: Make uart available before MMU is enabled Date: Fri, 27 Jan 2023 11:40:48 +0000 Message-ID: <20230127114108.10025-8-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230127114108.10025-1-joey.gouly@arm.com> References: <20230127112248.136810-1-suzuki.poulose@arm.com> <20230127114108.10025-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT011:EE_|DU0PR08MB9797:EE_|DBAEUR03FT047:EE_|AS2PR08MB8406:EE_ X-MS-Office365-Filtering-Correlation-Id: 68e1093a-f634-4120-7a58-08db005b853d x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 11:42:08.0479 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68e1093a-f634-4120-7a58-08db005b853d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT047.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB8406 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A Realm must access any emulated I/O mappings with the PTE_NS_SHARED bit se= t. This is modelled as a PTE attribute, but is actually part of the address. So, when MMU is disabled, the "physical address" must reflect this bit set.= We access the UART early before the MMU is enabled. So, make sure the UART is accessed always with the bit set. Signed-off-by: Joey Gouly --- lib/arm/io.c | 24 +++++++++++++++++++++++- lib/arm64/asm/pgtable.h | 5 +++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/lib/arm/io.c b/lib/arm/io.c index 343e1082..f7c6c771 100644 --- a/lib/arm/io.c +++ b/lib/arm/io.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include =20 #include "io.h" =20 @@ -29,6 +31,24 @@ static struct spinlock uart_lock; #define UART_EARLY_BASE (u8 *)(unsigned long)CONFIG_UART_EARLY_BASE static volatile u8 *uart0_base =3D UART_EARLY_BASE; =20 +static inline volatile u8 *get_uart_base(void) +{ + /* + * The address of the UART base may be different + * based on whether we are running with/without + * MMU enabled. + * + * For realms, we must force to use the shared physical + * alias with MMU disabled, to make sure the I/O can + * be emulated. + * When the MMU is turned ON, the mappings are created + * appropriately. + */ + if (mmu_enabled()) + return uart0_base; + return (u8 *)arm_shared_phys_alias((void *)uart0_base); +} + static void uart0_init(void) { /* @@ -81,9 +101,11 @@ void io_init(void) =20 void puts(const char *s) { + volatile u8 *uart_base =3D get_uart_base(); + spin_lock(&uart_lock); while (*s) - writeb(*s++, uart0_base); + writeb(*s++, uart_base); spin_unlock(&uart_lock); } =20 diff --git a/lib/arm64/asm/pgtable.h b/lib/arm64/asm/pgtable.h index 5b9f40b0..871c03e9 100644 --- a/lib/arm64/asm/pgtable.h +++ b/lib/arm64/asm/pgtable.h @@ -28,6 +28,11 @@ extern unsigned long prot_ns_shared; */ #define PTE_NS_SHARED (prot_ns_shared) =20 +static inline unsigned long arm_shared_phys_alias(void *addr) +{ + return ((unsigned long)addr | PTE_NS_SHARED); +} + /* * Highest possible physical address supported. */ --=20 2.17.1